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amd64_edac: Fix csrows size and pages computation
Make sure code pays attention to K8 having only one DCT, reformat and cleanup code, correct debug messages, remove unused code. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
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0a5dfc3140
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10de6497a5
1 changed files with 28 additions and 22 deletions
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@ -2087,6 +2087,7 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
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u32 cs_mode, nr_pages;
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u32 cs_mode, nr_pages;
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u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
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u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
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/*
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/*
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* The math on this doesn't look right on the surface because x/2*4 can
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* The math on this doesn't look right on the surface because x/2*4 can
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* be simplified to x*2 but this expression makes use of the fact that
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* be simplified to x*2 but this expression makes use of the fact that
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@ -2098,9 +2099,9 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
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nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
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nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
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edac_dbg(0, " (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
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edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
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edac_dbg(0, " nr_pages/channel= %u channel-count = %d\n",
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csrow_nr, dct, cs_mode);
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nr_pages, pvt->channel_count);
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edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
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return nr_pages;
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return nr_pages;
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}
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}
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@ -2111,15 +2112,14 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
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*/
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*/
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static int init_csrows(struct mem_ctl_info *mci)
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static int init_csrows(struct mem_ctl_info *mci)
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{
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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struct csrow_info *csrow;
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struct csrow_info *csrow;
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struct dimm_info *dimm;
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struct dimm_info *dimm;
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struct amd64_pvt *pvt = mci->pvt_info;
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u64 base, mask;
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u32 val;
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int i, j, empty = 1;
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enum mem_type mtype;
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enum edac_type edac_mode;
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enum edac_type edac_mode;
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enum mem_type mtype;
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int i, j, empty = 1;
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int nr_pages = 0;
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int nr_pages = 0;
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u32 val;
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amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
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amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
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@ -2129,29 +2129,35 @@ static int init_csrows(struct mem_ctl_info *mci)
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pvt->mc_node_id, val,
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pvt->mc_node_id, val,
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!!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
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!!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
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/*
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* We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
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*/
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for_each_chip_select(i, 0, pvt) {
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for_each_chip_select(i, 0, pvt) {
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csrow = mci->csrows[i];
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bool row_dct0 = !!csrow_enabled(i, 0, pvt);
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bool row_dct1 = false;
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if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {
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if (boot_cpu_data.x86 != 0xf)
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edac_dbg(1, "----CSROW %d VALID for MC node %d\n",
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row_dct1 = !!csrow_enabled(i, 1, pvt);
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i, pvt->mc_node_id);
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if (!row_dct0 && !row_dct1)
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continue;
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continue;
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}
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csrow = mci->csrows[i];
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empty = 0;
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empty = 0;
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if (csrow_enabled(i, 0, pvt))
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nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
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if (csrow_enabled(i, 1, pvt))
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nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
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get_cs_base_and_mask(pvt, i, 0, &base, &mask);
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edac_dbg(1, "MC node: %d, csrow: %d\n",
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/* 8 bytes of resolution */
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pvt->mc_node_id, i);
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if (row_dct0)
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nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
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/* K8 has only one DCT */
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if (boot_cpu_data.x86 != 0xf && row_dct1)
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nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
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mtype = amd64_determine_memory_type(pvt, i);
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mtype = amd64_determine_memory_type(pvt, i);
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edac_dbg(1, " for MC node %d csrow %d:\n", pvt->mc_node_id, i);
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edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
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edac_dbg(1, " nr_pages: %u\n",
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nr_pages * pvt->channel_count);
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/*
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/*
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* determine whether CHIPKILL or JUST ECC or NO ECC is operating
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* determine whether CHIPKILL or JUST ECC or NO ECC is operating
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