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UniPhier ARM SoC fixes for v4.9
- Add "select ARCH_HAS_RESET_CONTROLLER" in Kconfig - Rename wrongly-named mioctrl to sdctrl -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYC3TPAAoJED2LAQed4NsGBWQP/1YQ452mR1/5aO4HtlxapkKD Pn2GUPxxdnEJgCeUCQJbZJLZQKG8NfXvzRDuyRFlpUGvtHXB79W/zF7Qbh0XJQh4 flnNhPio6aeeyj6Mu9f2fZTzymxF7KeTgk2OAJjzi7BzRvOyrFQkkl6dquxmxfVz 0DO7VXiTewLtGTClesYXdj4Tr5zlR0PeyjBCw9nf3guy4RiQXXt5KXQvOXjHzFFl FZJcAN6hdJ2yh1LHyipXb4WnNl7YUro+OanesUU0Hg1wfCw4hmcjD4/BgO2y82kT ORTeN6Vrbvn8uBq/qxtJK/gzD/Kk/cyTQIe5pf9oW1WoZpyDS6PvLKErlv/+OkzX fsDG67ZaOn3lnGkP7R938gfjAefppWoxQSUMTiVWFjKO7TPSh3KjDAV2zRXr4Qfc +C/iRAHSMLB3JWZgYMKMy2N1QepqEynUeq2yWGd1FU/PbAjd/lb0fvWQR6eyySim JCby/nL6zJaxv1OLbRo4yeUN3LBGxEDsFCbO5z9ilZ9LTfPwiquUfIN/PDDigADY kqQJ+Mx1/5QhB9IH0fnzmMIQ+LNgZgxgahU1ZD3+q0HTlyb4lplJipQDwgo+k8k+ L6/LMa2VNk/Mj7klNb8QNTI2o5d8mHc+AJ7EWgwDA9RR9TfXJT2VE95IFdAfB893 jWqA+1RKB2dsyPwr4E9B =ucuF -----END PGP SIGNATURE----- Merge tag 'uniphier-fixes-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into fixes UniPhier ARM SoC fixes for v4.9 - Add "select ARCH_HAS_RESET_CONTROLLER" in Kconfig - Rename wrongly-named mioctrl to sdctrl * tag 'uniphier-fixes-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: change MIO node to SD control node ARM: dts: uniphier: change MIO node to SD control node reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
10e15a639c
7 changed files with 51 additions and 49 deletions
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@ -6,25 +6,25 @@ System reset
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Required properties:
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Required properties:
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- compatible: should be one of the following:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
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"socionext,uniphier-sld3-reset" - for sLD3 SoC.
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"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
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"socionext,uniphier-ld4-reset" - for LD4 SoC.
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"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
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"socionext,uniphier-pro4-reset" - for Pro4 SoC.
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"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
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"socionext,uniphier-sld8-reset" - for sLD8 SoC.
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"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
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"socionext,uniphier-pro5-reset" - for Pro5 SoC.
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"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
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"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
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"socionext,uniphier-ld11-reset" - for LD11 SoC.
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"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
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"socionext,uniphier-ld20-reset" - for LD20 SoC.
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- #reset-cells: should be 1.
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- #reset-cells: should be 1.
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Example:
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Example:
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sysctrl@61840000 {
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sysctrl@61840000 {
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compatible = "socionext,uniphier-ld20-sysctrl",
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compatible = "socionext,uniphier-ld11-sysctrl",
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"simple-mfd", "syscon";
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"simple-mfd", "syscon";
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reg = <0x61840000 0x4000>;
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reg = <0x61840000 0x4000>;
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reset {
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reset {
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compatible = "socionext,uniphier-ld20-reset";
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compatible = "socionext,uniphier-ld11-reset";
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#reset-cells = <1>;
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#reset-cells = <1>;
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};
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};
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@ -32,30 +32,30 @@ Example:
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};
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};
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Media I/O (MIO) reset
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Media I/O (MIO) reset, SD reset
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---------------------
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-------------------------------
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Required properties:
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Required properties:
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- compatible: should be one of the following:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
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"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
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"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
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"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
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"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
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"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
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"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
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"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
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"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
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"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
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"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
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"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
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"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
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"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
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"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
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- #reset-cells: should be 1.
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- #reset-cells: should be 1.
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Example:
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Example:
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mioctrl@59810000 {
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mioctrl@59810000 {
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compatible = "socionext,uniphier-ld20-mioctrl",
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compatible = "socionext,uniphier-ld11-mioctrl",
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"simple-mfd", "syscon";
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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reg = <0x59810000 0x800>;
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reset {
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reset {
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compatible = "socionext,uniphier-ld20-mio-reset";
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compatible = "socionext,uniphier-ld11-mio-reset";
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#reset-cells = <1>;
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#reset-cells = <1>;
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};
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};
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@ -68,24 +68,24 @@ Peripheral reset
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Required properties:
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Required properties:
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- compatible: should be one of the following:
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- compatible: should be one of the following:
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"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
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"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
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"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
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"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
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"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
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"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
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"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
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"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
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"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
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"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
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"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
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"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
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"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
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- #reset-cells: should be 1.
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- #reset-cells: should be 1.
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Example:
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Example:
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perictrl@59820000 {
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perictrl@59820000 {
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compatible = "socionext,uniphier-ld20-perictrl",
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compatible = "socionext,uniphier-ld11-perictrl",
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"simple-mfd", "syscon";
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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reg = <0x59820000 0x200>;
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reset {
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reset {
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compatible = "socionext,uniphier-ld20-peri-reset";
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compatible = "socionext,uniphier-ld11-peri-reset";
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#reset-cells = <1>;
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#reset-cells = <1>;
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};
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};
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@ -184,11 +184,11 @@ &refclk {
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};
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};
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&mio_clk {
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&mio_clk {
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compatible = "socionext,uniphier-pro5-mio-clock";
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compatible = "socionext,uniphier-pro5-sd-clock";
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};
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};
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&mio_rst {
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&mio_rst {
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compatible = "socionext,uniphier-pro5-mio-reset";
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compatible = "socionext,uniphier-pro5-sd-reset";
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};
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};
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&peri_clk {
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&peri_clk {
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@ -197,11 +197,11 @@ &refclk {
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};
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};
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&mio_clk {
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&mio_clk {
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compatible = "socionext,uniphier-pxs2-mio-clock";
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compatible = "socionext,uniphier-pxs2-sd-clock";
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};
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};
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&mio_rst {
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&mio_rst {
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compatible = "socionext,uniphier-pxs2-mio-reset";
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compatible = "socionext,uniphier-pxs2-sd-reset";
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};
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};
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&peri_clk {
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&peri_clk {
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@ -1,6 +1,7 @@
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config ARCH_UNIPHIER
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoCs"
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bool "Socionext UniPhier SoCs"
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depends on ARCH_MULTI_V7
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depends on ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_AMBA
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select ARM_AMBA
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select ARM_GLOBAL_TIMER
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select ARM_GLOBAL_TIMER
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select ARM_GIC
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select ARM_GIC
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@ -190,6 +190,7 @@ config ARCH_THUNDER
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config ARCH_UNIPHIER
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoC Family"
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bool "Socionext UniPhier SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select PINCTRL
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help
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help
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This enables support for Socionext UniPhier SoC family.
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This enables support for Socionext UniPhier SoC family.
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@ -257,18 +257,18 @@ smpctrl@59800000 {
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reg = <0x59801000 0x400>;
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reg = <0x59801000 0x400>;
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};
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};
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mioctrl@59810000 {
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sdctrl@59810000 {
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compatible = "socionext,uniphier-mioctrl",
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compatible = "socionext,uniphier-ld20-sdctrl",
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"simple-mfd", "syscon";
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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reg = <0x59810000 0x800>;
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mio_clk: clock {
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sd_clk: clock {
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compatible = "socionext,uniphier-ld20-mio-clock";
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compatible = "socionext,uniphier-ld20-sd-clock";
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#clock-cells = <1>;
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#clock-cells = <1>;
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};
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};
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mio_rst: reset {
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sd_rst: reset {
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compatible = "socionext,uniphier-ld20-mio-reset";
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compatible = "socionext,uniphier-ld20-sd-reset";
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#reset-cells = <1>;
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#reset-cells = <1>;
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};
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};
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};
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};
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@ -154,7 +154,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
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UNIPHIER_RESET_END,
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UNIPHIER_RESET_END,
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};
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};
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const struct uniphier_reset_data uniphier_pro5_mio_reset_data[] = {
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const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
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UNIPHIER_MIO_RESET_SD(0, 0),
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UNIPHIER_MIO_RESET_SD(0, 0),
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UNIPHIER_MIO_RESET_SD(1, 1),
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UNIPHIER_MIO_RESET_SD(1, 1),
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UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
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UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
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@ -360,7 +360,7 @@ static const struct of_device_id uniphier_reset_match[] = {
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.compatible = "socionext,uniphier-ld20-reset",
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.compatible = "socionext,uniphier-ld20-reset",
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.data = uniphier_ld20_sys_reset_data,
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.data = uniphier_ld20_sys_reset_data,
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},
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},
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/* Media I/O reset */
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/* Media I/O reset, SD reset */
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{
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{
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.compatible = "socionext,uniphier-sld3-mio-reset",
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.compatible = "socionext,uniphier-sld3-mio-reset",
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.data = uniphier_sld3_mio_reset_data,
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.data = uniphier_sld3_mio_reset_data,
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@ -378,20 +378,20 @@ static const struct of_device_id uniphier_reset_match[] = {
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.data = uniphier_sld3_mio_reset_data,
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.data = uniphier_sld3_mio_reset_data,
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},
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},
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{
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{
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.compatible = "socionext,uniphier-pro5-mio-reset",
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.compatible = "socionext,uniphier-pro5-sd-reset",
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.data = uniphier_pro5_mio_reset_data,
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.data = uniphier_pro5_sd_reset_data,
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},
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},
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{
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{
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.compatible = "socionext,uniphier-pxs2-mio-reset",
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.compatible = "socionext,uniphier-pxs2-sd-reset",
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.data = uniphier_pro5_mio_reset_data,
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.data = uniphier_pro5_sd_reset_data,
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},
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},
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{
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{
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.compatible = "socionext,uniphier-ld11-mio-reset",
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.compatible = "socionext,uniphier-ld11-mio-reset",
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.data = uniphier_sld3_mio_reset_data,
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.data = uniphier_sld3_mio_reset_data,
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},
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},
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{
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{
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.compatible = "socionext,uniphier-ld20-mio-reset",
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.compatible = "socionext,uniphier-ld20-sd-reset",
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.data = uniphier_pro5_mio_reset_data,
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.data = uniphier_pro5_sd_reset_data,
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},
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},
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/* Peripheral reset */
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/* Peripheral reset */
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{
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{
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