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perf/arm-cmn: Fix the unhandled overflow status of counter 4 to 7
[ Upstream commit7f949f6f54
] The register por_dt_pmovsr Bits[7:0] indicates overflow from counters 7 to 0. But in arm_cmn_handle_irq(), only handled the overflow status of Bits[3:0] which results in unhandled overflow status of counters 4 to 7. So let the overflow status of DTC counters 4 to 7 to be handled. Fixes:0ba64770a2
("perf: Add Arm CMN-600 PMU driver") Signed-off-by: Jing Zhang <renyu.zj@linux.alibaba.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/1695612152-123633-1-git-send-email-renyu.zj@linux.alibaba.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1177,7 +1177,7 @@ static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
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u64 delta;
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int i;
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for (i = 0; i < CMN_DTM_NUM_COUNTERS; i++) {
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for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
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if (status & (1U << i)) {
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ret = IRQ_HANDLED;
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if (WARN_ON(!dtc->counters[i]))
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