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media: renesas: vsp1: Change V3U to be gen4

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V3U is actually gen4, not gen3. The same IP is also used in the
(not-yet-supported) V4H.

Change VI6_IP_VERSION_MODEL_VSPD_V3U to VI6_IP_VERSION_MODEL_VSPD_GEN4,
to represent the model correctly. V3U and V4H can still be
differentiated, if needed, with the VI6_IP_VERSION_SOC_xxx.

Also mark VI6_IP_VERSION_MODEL_VSPD_GEN4 as gen 4 in vsp1_device_info,
and update the code to correctly match for gen 4.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Tomi Valkeinen 2022-12-21 11:24:44 +02:00 committed by Laurent Pinchart
parent 0dc1d7a79a
commit 110d2bd7a2
7 changed files with 16 additions and 15 deletions
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4
drivers/media/platform/renesas/vsp1/vsp1_drv.c
View file

@ -818,9 +818,9 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
.wpf_count = 2,
.num_bru_inputs = 5,
}, {
.version = VI6_IP_VERSION_MODEL_VSPD_V3U,
.version = VI6_IP_VERSION_MODEL_VSPD_GEN4,
.model = "VSP2-D",
.gen = 3,
.gen = 4,
.features = VSP1_HAS_BRU | VSP1_HAS_EXT_DL,
.lif_count = 1,
.rpf_count = 5,

4
drivers/media/platform/renesas/vsp1/vsp1_hgo.c
View file

@ -196,10 +196,10 @@ struct vsp1_hgo *vsp1_hgo_create(struct vsp1_device *vsp1)
/* Initialize the control handler. */
v4l2_ctrl_handler_init(&hgo->ctrls.handler,
vsp1->info->gen == 3 ? 2 : 1);
vsp1->info->gen >= 3 ? 2 : 1);
hgo->ctrls.max_rgb = v4l2_ctrl_new_custom(&hgo->ctrls.handler,
&hgo_max_rgb_control, NULL);
if (vsp1->info->gen == 3)
if (vsp1->info->gen >= 3)
hgo->ctrls.num_bins =
v4l2_ctrl_new_custom(&hgo->ctrls.handler,
&hgo_num_bins_control, NULL);

1
drivers/media/platform/renesas/vsp1/vsp1_lif.c
View file

@ -114,6 +114,7 @@ static void lif_configure_stream(struct vsp1_entity *entity,
break;
case VI6_IP_VERSION_MODEL_VSPD_GEN3:
case VI6_IP_VERSION_MODEL_VSPD_GEN4:
default:
hbth = 0;
obth = 3000;

2
drivers/media/platform/renesas/vsp1/vsp1_regs.h
View file

@ -766,7 +766,7 @@
#define VI6_IP_VERSION_MODEL_VSPD_V3 (0x18 << 8)
#define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8)
#define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8)
#define VI6_IP_VERSION_MODEL_VSPD_V3U (0x1c << 8)
#define VI6_IP_VERSION_MODEL_VSPD_GEN4 (0x1c << 8)
/* RZ/G2L SoCs have no version register, So use 0x80 as the model version */
#define VI6_IP_VERSION_MODEL_VSPD_RZG2L (0x80 << 8)

12
drivers/media/platform/renesas/vsp1/vsp1_rpf.c
View file

@ -133,18 +133,18 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
* a fixed alpha value set through the V4L2_CID_ALPHA_COMPONENT control
* otherwise.
*
* The Gen3 RPF has extended alpha capability and can both multiply the
* The Gen3+ RPF has extended alpha capability and can both multiply the
* alpha channel by a fixed global alpha value, and multiply the pixel
* components to convert the input to premultiplied alpha.
*
* As alpha premultiplication is available in the BRx for both Gen2 and
* Gen3 we handle it there and use the Gen3 alpha multiplier for global
* Gen3+ we handle it there and use the Gen3 alpha multiplier for global
* alpha multiplication only. This however prevents conversion to
* premultiplied alpha if no BRx is present in the pipeline. If that use
* case turns out to be useful we will revisit the implementation (for
* Gen3 only).
*
* We enable alpha multiplication on Gen3 using the fixed alpha value
* We enable alpha multiplication on Gen3+ using the fixed alpha value
* set through the V4L2_CID_ALPHA_COMPONENT control when the input
* contains an alpha channel. On Gen2 the global alpha is ignored in
* that case.
@ -155,7 +155,7 @@ static void rpf_configure_stream(struct vsp1_entity *entity,
(fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED
: VI6_RPF_ALPH_SEL_ASEL_FIXED));
if (entity->vsp1->info->gen == 3) {
if (entity->vsp1->info->gen >= 3) {
u32 mult;
if (fmtinfo->alpha) {
@ -301,10 +301,10 @@ static void rpf_configure_partition(struct vsp1_entity *entity,
}
/*
* On Gen3 hardware the SPUVS bit has no effect on 3-planar
* On Gen3+ hardware the SPUVS bit has no effect on 3-planar
* formats. Swap the U and V planes manually in that case.
*/
if (vsp1->info->gen == 3 && format->num_planes == 3 &&
if (vsp1->info->gen >= 3 && format->num_planes == 3 &&
fmtinfo->swap_uv)
swap(mem.addr[1], mem.addr[2]);

4
drivers/media/platform/renesas/vsp1/vsp1_video.c
View file

@ -267,10 +267,10 @@ static int vsp1_video_pipeline_setup_partitions(struct vsp1_pipeline *pipe)
div_size = format->width;
/*
* Only Gen3 hardware requires image partitioning, Gen2 will operate
* Only Gen3+ hardware requires image partitioning, Gen2 will operate
* with a single partition that covers the whole output.
*/
if (vsp1->info->gen == 3) {
if (vsp1->info->gen >= 3) {
list_for_each_entry(entity, &pipe->entities, list_pipe) {
unsigned int entity_max;

4
drivers/media/platform/renesas/vsp1/vsp1_wpf.c
View file

@ -512,10 +512,10 @@ static void wpf_configure_partition(struct vsp1_entity *entity,
}
/*
* On Gen3 hardware the SPUVS bit has no effect on 3-planar
* On Gen3+ hardware the SPUVS bit has no effect on 3-planar
* formats. Swap the U and V planes manually in that case.
*/
if (vsp1->info->gen == 3 && format->num_planes == 3 &&
if (vsp1->info->gen >= 3 && format->num_planes == 3 &&
fmtinfo->swap_uv)
swap(mem.addr[1], mem.addr[2]);