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[ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later
Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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11179d8ca2
2 changed files with 11 additions and 5 deletions
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@ -599,7 +599,7 @@ config CPU_DCACHE_SIZE
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
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default y if CPU_ARM925T
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p)
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}
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if (i == ARRAY_SIZE(cache_policies))
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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if (cpu_architecture() >= CPU_ARCH_ARMv6) {
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printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
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cachepolicy = CPOLICY_WRITEBACK;
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}
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flush_cache_all();
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set_cr(cr_alignment);
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}
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@ -252,13 +256,15 @@ static void __init build_mem_type_table(void)
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int cpu_arch = cpu_architecture();
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int i;
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if (cpu_arch < CPU_ARCH_ARMv6) {
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#if defined(CONFIG_CPU_DCACHE_DISABLE)
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if (cachepolicy > CPOLICY_BUFFERED)
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cachepolicy = CPOLICY_BUFFERED;
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if (cachepolicy > CPOLICY_BUFFERED)
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cachepolicy = CPOLICY_BUFFERED;
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#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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if (cachepolicy > CPOLICY_WRITETHROUGH)
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cachepolicy = CPOLICY_WRITETHROUGH;
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if (cachepolicy > CPOLICY_WRITETHROUGH)
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cachepolicy = CPOLICY_WRITETHROUGH;
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#endif
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}
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if (cpu_arch < CPU_ARCH_ARMv5) {
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if (cachepolicy >= CPOLICY_WRITEALLOC)
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cachepolicy = CPOLICY_WRITEBACK;
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