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Merge branch 'topic/mv_xor' into for-linus
This commit is contained in:
commit
112db20e81
4 changed files with 84 additions and 22 deletions
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@ -1,7 +1,10 @@
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* Marvell XOR engines
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Required properties:
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- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"
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- compatible: Should be one of the following:
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- "marvell,orion-xor"
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- "marvell,armada-380-xor"
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- "marvell,armada-3700-xor".
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- reg: Should contain registers location and length (two sets)
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the first set is the low registers, the second set the high
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registers for the XOR engine.
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@ -332,7 +332,7 @@ config MPC512X_DMA
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config MV_XOR
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bool "Marvell XOR engine support"
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depends on PLAT_ORION
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depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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@ -31,6 +31,12 @@
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#include "dmaengine.h"
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#include "mv_xor.h"
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enum mv_xor_type {
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XOR_ORION,
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XOR_ARMADA_38X,
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XOR_ARMADA_37XX,
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};
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enum mv_xor_mode {
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XOR_MODE_IN_REG,
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XOR_MODE_IN_DESC,
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@ -477,7 +483,7 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
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dev_dbg(mv_chan_to_devp(mv_chan),
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"%s src_cnt: %d len: %u dest %pad flags: %ld\n",
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"%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
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__func__, src_cnt, len, &dest, flags);
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sw_desc = mv_chan_alloc_slot(mv_chan);
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@ -933,7 +939,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
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static struct mv_xor_chan *
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mv_xor_channel_add(struct mv_xor_device *xordev,
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struct platform_device *pdev,
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int idx, dma_cap_mask_t cap_mask, int irq, int op_in_desc)
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int idx, dma_cap_mask_t cap_mask, int irq)
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{
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int ret = 0;
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struct mv_xor_chan *mv_chan;
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@ -945,7 +951,10 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
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mv_chan->idx = idx;
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mv_chan->irq = irq;
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mv_chan->op_in_desc = op_in_desc;
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if (xordev->xor_type == XOR_ORION)
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mv_chan->op_in_desc = XOR_MODE_IN_REG;
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else
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mv_chan->op_in_desc = XOR_MODE_IN_DESC;
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dma_dev = &mv_chan->dmadev;
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@ -1085,6 +1094,33 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
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writel(0, base + WINDOW_OVERRIDE_CTRL(1));
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}
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static void
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mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
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{
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void __iomem *base = xordev->xor_high_base;
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u32 win_enable = 0;
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int i;
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for (i = 0; i < 8; i++) {
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writel(0, base + WINDOW_BASE(i));
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writel(0, base + WINDOW_SIZE(i));
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if (i < 4)
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writel(0, base + WINDOW_REMAP_HIGH(i));
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}
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/*
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* For Armada3700 open default 4GB Mbus window. The dram
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* related configuration are done at AXIS level.
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*/
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writel(0xffff0000, base + WINDOW_SIZE(0));
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win_enable |= 1;
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win_enable |= 3 << 16;
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writel(win_enable, base + WINDOW_BAR_ENABLE(0));
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writel(win_enable, base + WINDOW_BAR_ENABLE(1));
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writel(0, base + WINDOW_OVERRIDE_CTRL(0));
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writel(0, base + WINDOW_OVERRIDE_CTRL(1));
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}
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/*
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* Since this XOR driver is basically used only for RAID5, we don't
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* need to care about synchronizing ->suspend with DMA activity,
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@ -1129,6 +1165,11 @@ static int mv_xor_resume(struct platform_device *dev)
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XOR_INTR_MASK(mv_chan));
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}
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if (xordev->xor_type == XOR_ARMADA_37XX) {
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mv_xor_conf_mbus_windows_a3700(xordev);
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return 0;
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}
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dram = mv_mbus_dram_info();
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if (dram)
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mv_xor_conf_mbus_windows(xordev, dram);
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@ -1137,8 +1178,9 @@ static int mv_xor_resume(struct platform_device *dev)
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}
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static const struct of_device_id mv_xor_dt_ids[] = {
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{ .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG },
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{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC },
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{ .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
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{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
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{ .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
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{},
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};
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@ -1152,7 +1194,6 @@ static int mv_xor_probe(struct platform_device *pdev)
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struct resource *res;
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unsigned int max_engines, max_channels;
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int i, ret;
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int op_in_desc;
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dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
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@ -1180,12 +1221,30 @@ static int mv_xor_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, xordev);
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/*
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* We need to know which type of XOR device we use before
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* setting up. In non-dt case it can only be the legacy one.
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*/
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xordev->xor_type = XOR_ORION;
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if (pdev->dev.of_node) {
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const struct of_device_id *of_id =
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of_match_device(mv_xor_dt_ids,
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&pdev->dev);
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xordev->xor_type = (uintptr_t)of_id->data;
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}
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/*
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* (Re-)program MBUS remapping windows if we are asked to.
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*/
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dram = mv_mbus_dram_info();
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if (dram)
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mv_xor_conf_mbus_windows(xordev, dram);
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if (xordev->xor_type == XOR_ARMADA_37XX) {
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mv_xor_conf_mbus_windows_a3700(xordev);
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} else {
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dram = mv_mbus_dram_info();
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if (dram)
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mv_xor_conf_mbus_windows(xordev, dram);
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}
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/* Not all platforms can gate the clock, so it is not
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* an error if the clock does not exists.
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@ -1199,12 +1258,16 @@ static int mv_xor_probe(struct platform_device *pdev)
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* order for async_tx to perform well. So we limit the number
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* of engines and channels so that we take into account this
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* constraint. Note that we also want to use channels from
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* separate engines when possible.
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* separate engines when possible. For dual-CPU Armada 3700
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* SoC with single XOR engine allow using its both channels.
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*/
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max_engines = num_present_cpus();
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max_channels = min_t(unsigned int,
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MV_XOR_MAX_CHANNELS,
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DIV_ROUND_UP(num_present_cpus(), 2));
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if (xordev->xor_type == XOR_ARMADA_37XX)
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max_channels = num_present_cpus();
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else
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max_channels = min_t(unsigned int,
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MV_XOR_MAX_CHANNELS,
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DIV_ROUND_UP(num_present_cpus(), 2));
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if (mv_xor_engine_count >= max_engines)
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return 0;
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@ -1212,15 +1275,11 @@ static int mv_xor_probe(struct platform_device *pdev)
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if (pdev->dev.of_node) {
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struct device_node *np;
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int i = 0;
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const struct of_device_id *of_id =
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of_match_device(mv_xor_dt_ids,
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&pdev->dev);
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for_each_child_of_node(pdev->dev.of_node, np) {
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struct mv_xor_chan *chan;
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dma_cap_mask_t cap_mask;
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int irq;
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op_in_desc = (int)of_id->data;
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if (i >= max_channels)
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continue;
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}
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chan = mv_xor_channel_add(xordev, pdev, i,
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cap_mask, irq, op_in_desc);
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cap_mask, irq);
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if (IS_ERR(chan)) {
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ret = PTR_ERR(chan);
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irq_dispose_mapping(irq);
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@ -1266,8 +1325,7 @@ static int mv_xor_probe(struct platform_device *pdev)
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}
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chan = mv_xor_channel_add(xordev, pdev, i,
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cd->cap_mask, irq,
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XOR_MODE_IN_REG);
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cd->cap_mask, irq);
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if (IS_ERR(chan)) {
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ret = PTR_ERR(chan);
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goto err_channel_add;
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@ -85,6 +85,7 @@ struct mv_xor_device {
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void __iomem *xor_high_base;
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struct clk *clk;
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struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
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int xor_type;
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};
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/**
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