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clk: rockchip: add clock controller for the RK3399
Add the clock tree definition for the new RK3399 SoC. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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3 changed files with 1562 additions and 1 deletions
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@ -15,3 +15,4 @@ obj-y += clk-rk3188.o
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obj-y += clk-rk3228.o
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obj-y += clk-rk3288.o
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obj-y += clk-rk3368.o
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obj-y += clk-rk3399.o
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1540
drivers/clk/rockchip/clk-rk3399.c
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1540
drivers/clk/rockchip/clk-rk3399.c
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@ -34,7 +34,7 @@ struct clk;
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
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/* register positions shared by RK2928, RK3036, RK3066, RK3188, RK3228, RK3399 */
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#define RK2928_PLL_CON(x) ((x) * 0x4)
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#define RK2928_MODE_CON 0x40
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#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
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@ -93,6 +93,26 @@ struct clk;
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#define RK3368_EMMC_CON0 0x418
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#define RK3368_EMMC_CON1 0x41c
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#define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
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#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
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#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
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#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
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#define RK3399_GLB_SRST_FST 0x500
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#define RK3399_GLB_SRST_SND 0x504
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#define RK3399_GLB_CNT_TH 0x508
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#define RK3399_MISC_CON 0x50c
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#define RK3399_RST_CON 0x510
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#define RK3399_RST_ST 0x514
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#define RK3399_SDMMC_CON0 0x580
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#define RK3399_SDMMC_CON1 0x584
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#define RK3399_SDIO_CON0 0x588
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#define RK3399_SDIO_CON1 0x58c
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#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
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#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
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#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
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#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
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enum rockchip_pll_type {
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pll_rk3036,
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pll_rk3066,
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