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[MIPS] Misc fixes for plat_irq_dispatch functions

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o adds missing ST0_IM masks, which caused the logging of valid interrupts
   as spurious
 o stops pnx8550 to log every interrupt as spurious
 o adds cause register masks for ip22/ip32, which caused handling of masked
   interrupts
 o removes some superfluous parentheses in the SNI interrupt code

Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thiemo Seufer 2007-03-19 00:13:37 +00:00 committed by Ralf Baechle
parent 72ede9b189
commit 119537c092
13 changed files with 16 additions and 17 deletions
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2
arch/mips/ddb5xxx/ddb5477/irq.c
View file

@ -194,7 +194,7 @@ static void vrc5477_irq_dispatch(void)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status();
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7);

2
arch/mips/emma2rh/markeins/irq.c
View file

@ -115,7 +115,7 @@ void __init arch_init_irq(void)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7);

2
arch/mips/gt64120/ev64120/irq.c
View file

@ -48,7 +48,7 @@
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
do_IRQ(4);

2
arch/mips/gt64120/wrppmc/irq.c
View file

@ -32,7 +32,7 @@
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */

2
arch/mips/jazz/irq.c
View file

@ -122,7 +122,7 @@ static void ll_local_dev(void)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
unsigned int pending = read_c0_cause() & read_c0_status();
if (pending & IE_IRQ5)
write_c0_compare(0);

2
arch/mips/momentum/ocelot_c/irq.c
View file

@ -64,7 +64,7 @@ extern void ll_cpci_irq(void);
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status();
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & STATUSF_IP0)
do_IRQ(0);

7
arch/mips/philips/pnx8550/common/int.c
View file

@ -83,16 +83,15 @@ static void timer_irqdispatch(int irq)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP2)
hw0_irqdispatch(2);
else if (pending & STATUSF_IP7) {
if (read_c0_config7() & 0x01c0)
timer_irqdispatch(7);
}
spurious_interrupt();
} else
spurious_interrupt();
}
static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)

2
arch/mips/sgi-ip22/ip22-int.c
View file

@ -237,7 +237,7 @@ extern void indy_8254timer_irq(void);
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause();
/*
* First we check for r4k counter/timer IRQ.

2
arch/mips/sgi-ip32/ip32-irq.c
View file

@ -454,7 +454,7 @@ static void ip32_irq5(void)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause();
if (likely(pending & IE_IRQ0))
ip32_irq0();

2
arch/mips/sibyte/sb1250/irq.c
View file

@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void)
* blasting the high 32 bits.
*/
pending = read_c0_cause() & read_c0_status();
pending = read_c0_cause() & read_c0_status() & ST0_IM;
#ifdef CONFIG_SIBYTE_SB1250_PROF
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */

2
arch/mips/sni/pcimt.c
View file

@ -333,7 +333,7 @@ static void pcimt_hwint3(void)
static void sni_pcimt_hwint(void)
{
u32 pending = (read_c0_cause() & read_c0_status());
u32 pending = read_c0_cause() & read_c0_status();
if (pending & C_IRQ5)
do_IRQ (MIPS_CPU_IRQ_BASE + 7);

4
arch/mips/sni/pcit.c
View file

@ -271,7 +271,7 @@ static void pcit_hwint0(void)
static void sni_pcit_hwint(void)
{
u32 pending = (read_c0_cause() & read_c0_status());
u32 pending = read_c0_cause() & read_c0_status();
if (pending & C_IRQ1)
pcit_hwint1();
@ -285,7 +285,7 @@ static void sni_pcit_hwint(void)
static void sni_pcit_hwint_cplus(void)
{
u32 pending = (read_c0_cause() & read_c0_status());
u32 pending = read_c0_cause() & read_c0_status();
if (pending & C_IRQ0)
pcit_hwint0();

2
arch/mips/tx4927/common/tx4927_irq.c
View file

@ -416,7 +416,7 @@ static int tx4927_irq_nested(void)
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) /* cpu timer */
do_IRQ(TX4927_IRQ_CPU_TIMER);