x86/atomic: Fix smp_mb__{before,after}_atomic()
[ Upstream commit 69d927bba3
]
Recent probing at the Linux Kernel Memory Model uncovered a
'surprise'. Strongly ordered architectures where the atomic RmW
primitive implies full memory ordering and
smp_mb__{before,after}_atomic() are a simple barrier() (such as x86)
fail for:
*x = 1;
atomic_inc(u);
smp_mb__after_atomic();
r0 = *y;
Because, while the atomic_inc() implies memory order, it
(surprisingly) does not provide a compiler barrier. This then allows
the compiler to re-order like so:
atomic_inc(u);
*x = 1;
smp_mb__after_atomic();
r0 = *y;
Which the CPU is then allowed to re-order (under TSO rules) like:
atomic_inc(u);
r0 = *y;
*x = 1;
And this very much was not intended. Therefore strengthen the atomic
RmW ops to include a compiler barrier.
NOTE: atomic_{or,and,xor} and the bitops already had the compiler
barrier.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -177,6 +177,9 @@ These helper barriers exist because architectures have varying implicit
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ordering on their SMP atomic primitives. For example our TSO architectures
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provide full ordered atomics and these barriers are no-ops.
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NOTE: when the atomic RmW ops are fully ordered, they should also imply a
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compiler barrier.
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Thus:
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atomic_fetch_add();
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@ -50,7 +50,7 @@ static __always_inline void atomic_add(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "addl %1,%0"
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: "+m" (v->counter)
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: "ir" (i));
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: "ir" (i) : "memory");
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}
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/**
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@ -64,7 +64,7 @@ static __always_inline void atomic_sub(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "subl %1,%0"
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: "+m" (v->counter)
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: "ir" (i));
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: "ir" (i) : "memory");
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}
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/**
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@ -90,7 +90,7 @@ static __always_inline bool atomic_sub_and_test(int i, atomic_t *v)
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static __always_inline void atomic_inc(atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "incl %0"
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: "+m" (v->counter));
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: "+m" (v->counter) :: "memory");
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}
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/**
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@ -102,7 +102,7 @@ static __always_inline void atomic_inc(atomic_t *v)
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static __always_inline void atomic_dec(atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "decl %0"
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: "+m" (v->counter));
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: "+m" (v->counter) :: "memory");
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}
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/**
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@ -45,7 +45,7 @@ static __always_inline void atomic64_add(long i, atomic64_t *v)
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{
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asm volatile(LOCK_PREFIX "addq %1,%0"
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: "=m" (v->counter)
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: "er" (i), "m" (v->counter));
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: "er" (i), "m" (v->counter) : "memory");
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}
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/**
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@ -59,7 +59,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
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{
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asm volatile(LOCK_PREFIX "subq %1,%0"
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: "=m" (v->counter)
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: "er" (i), "m" (v->counter));
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: "er" (i), "m" (v->counter) : "memory");
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}
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/**
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@ -86,7 +86,7 @@ static __always_inline void atomic64_inc(atomic64_t *v)
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{
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asm volatile(LOCK_PREFIX "incq %0"
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: "=m" (v->counter)
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: "m" (v->counter));
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: "m" (v->counter) : "memory");
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}
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/**
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@ -99,7 +99,7 @@ static __always_inline void atomic64_dec(atomic64_t *v)
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{
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asm volatile(LOCK_PREFIX "decq %0"
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: "=m" (v->counter)
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: "m" (v->counter));
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: "m" (v->counter) : "memory");
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}
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/**
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@ -106,8 +106,8 @@ do { \
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#endif
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/* Atomic operations are already serializing on x86 */
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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#define __smp_mb__before_atomic() do { } while (0)
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#define __smp_mb__after_atomic() do { } while (0)
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#include <asm-generic/barrier.h>
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