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cxl/region: Verify target positions using the ordered target list
[ Upstream commit82a3e3a235
] When a root decoder is configured the interleave target list is read from the BIOS populated CFMWS structure. Per the CXL spec 3.1 Table 9-22 the target list is in interleave order. The CXL driver populates its decoder target list in the same order and stores it in 'struct cxl_switch_decoder' field "@target: active ordered target list in current decoder configuration" Given the promise of an ordered list, the driver can stop duplicating the work of BIOS and simply check target positions against the ordered list during region configuration. The simplified check against the ordered list is presented here. A follow-on patch will remove the unused code. For Modulo arithmetic this is not a fix, only a simplification. For XOR arithmetic this is a fix for HB IW of 3,6,12. Fixes:f9db85bfec
("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)") Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://patch.msgid.link/35d08d3aba08fee0f9b86ab1cef0c25116ca8a55.1719980933.git.alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 4 additions and 1 deletions
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@ -1528,10 +1528,13 @@ static int cxl_region_attach_position(struct cxl_region *cxlr,
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const struct cxl_dport *dport, int pos)
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{
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struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
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struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
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struct cxl_decoder *cxld = &cxlsd->cxld;
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int iw = cxld->interleave_ways;
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struct cxl_port *iter;
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int rc;
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if (cxlrd->calc_hb(cxlrd, pos) != dport) {
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if (dport != cxlrd->cxlsd.target[pos % iw]) {
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dev_dbg(&cxlr->dev, "%s:%s invalid target position for %s\n",
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dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
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dev_name(&cxlrd->cxlsd.cxld.dev));
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