ppc440spe-adma: adds updated ppc440spe adma driver

This patch adds new version of the PPC440SPe ADMA driver.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Anatolij Gustschin 2009-12-11 21:24:44 -07:00 committed by Dan Williams
parent 2e032b62c4
commit 12458ea06e
10 changed files with 5731 additions and 0 deletions

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@ -0,0 +1,93 @@
PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
Device nodes needed for operation of the ppc440spe-adma driver
are specified hereby. These are I2O/DMA, DMA and XOR nodes
for DMA engines and Memory Queue Module node. The latter is used
by ADMA driver for configuration of RAID-6 H/W capabilities of
the PPC440SPe. In addition to the nodes and properties described
below, the ranges property of PLB node must specify ranges for
DMA devices.
i) The I2O node
Required properties:
- compatible : "ibm,i2o-440spe";
- reg : <registers mapping>
- dcr-reg : <DCR registers range>
Example:
I2O: i2o@400100000 {
compatible = "ibm,i2o-440spe";
reg = <0x00000004 0x00100000 0x100>;
dcr-reg = <0x060 0x020>;
};
ii) The DMA node
Required properties:
- compatible : "ibm,dma-440spe";
- cell-index : 1 cell, hardware index of the DMA engine
(typically 0x0 and 0x1 for DMA0 and DMA1)
- reg : <registers mapping>
- dcr-reg : <DCR registers range>
- interrupts : <interrupt mapping for DMA0/1 interrupts sources:
2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
and DMA Error IRQ (on UIC1). The latter is common
for both DMA engines>.
- interrupt-parent : needed for interrupt mapping
Example:
DMA0: dma0@400100100 {
compatible = "ibm,dma-440spe";
cell-index = <0>;
reg = <0x00000004 0x00100100 0x100>;
dcr-reg = <0x060 0x020>;
interrupt-parent = <&DMA0>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <
0 &UIC0 0x14 4
1 &UIC1 0x16 4>;
};
iii) XOR Accelerator node
Required properties:
- compatible : "amcc,xor-accelerator";
- reg : <registers mapping>
- interrupts : <interrupt mapping for XOR interrupt source>
- interrupt-parent : for interrupt mapping
Example:
xor-accel@400200000 {
compatible = "amcc,xor-accelerator";
reg = <0x00000004 0x00200000 0x400>;
interrupt-parent = <&UIC1>;
interrupts = <0x1f 4>;
};
iv) Memory Queue Module node
Required properties:
- compatible : "ibm,mq-440spe";
- dcr-reg : <DCR registers range>
Example:
MQ0: mq {
compatible = "ibm,mq-440spe";
dcr-reg = <0x040 0x020>;
};

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/*
* Copyright (C) 2008-2009 DENX Software Engineering.
*
* Author: Yuri Tikhonov <yur@emcraft.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution in the
* file called COPYING.
*/
#ifndef _ASM_POWERPC_ASYNC_TX_H_
#define _ASM_POWERPC_ASYNC_TX_H_
#if defined(CONFIG_440SPe) || defined(CONFIG_440SP)
extern struct dma_chan *
ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap,
struct page **dst_lst, int dst_cnt, struct page **src_lst,
int src_cnt, size_t src_sz);
#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \
src_cnt, src_sz) \
ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \
src_cnt, src_sz)
#else
#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
__async_tx_find_channel(dep, type)
struct dma_chan *
__async_tx_find_channel(struct async_submit_ctl *submit,
enum dma_transaction_type tx_type);
#endif
#endif

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@ -157,4 +157,27 @@
#define L2C_SNP_SSR_32G 0x0000f000
#define L2C_SNP_ESR 0x00000800
/*
* DCR register offsets for 440SP/440SPe I2O/DMA controller.
* The base address is configured in the device tree.
*/
#define DCRN_I2O0_IBAL 0x006
#define DCRN_I2O0_IBAH 0x007
#define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */
/* 440SP/440SPe Software Reset DCR */
#define DCRN_SDR0_SRST 0x0200
#define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */
/* 440SP/440SPe Memory Queue DCR offsets */
#define DCRN_MQ0_XORBA 0x04
#define DCRN_MQ0_CF2H 0x06
#define DCRN_MQ0_CFBHL 0x0f
#define DCRN_MQ0_BAUH 0x10
/* HB/LL Paths Configuration Register */
#define MQ0_CFBHL_TPLM 28
#define MQ0_CFBHL_HBCL 23
#define MQ0_CFBHL_POLY 15
#endif /* __DCR_REGS_H__ */

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@ -116,6 +116,17 @@ config COH901318
help
Enable support for ST-Ericsson COH 901 318 DMA.
config AMCC_PPC440SPE_ADMA
tristate "AMCC PPC440SPe ADMA support"
depends on 440SPe || 440SP
select DMA_ENGINE
select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
help
Enable support for the AMCC PPC440SPe RAID engines.
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
config DMA_ENGINE
bool

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@ -11,3 +11,4 @@ obj-$(CONFIG_MX3_IPU) += ipu/
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_SH_DMAE) += shdma.o
obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/

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@ -0,0 +1 @@
obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += adma.o

5027
drivers/dma/ppc4xx/adma.c Normal file

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195
drivers/dma/ppc4xx/adma.h Normal file
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/*
* 2006-2009 (C) DENX Software Engineering.
*
* Author: Yuri Tikhonov <yur@emcraft.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of
* any kind, whether express or implied.
*/
#ifndef _PPC440SPE_ADMA_H
#define _PPC440SPE_ADMA_H
#include <linux/types.h>
#include "dma.h"
#include "xor.h"
#define to_ppc440spe_adma_chan(chan) \
container_of(chan, struct ppc440spe_adma_chan, common)
#define to_ppc440spe_adma_device(dev) \
container_of(dev, struct ppc440spe_adma_device, common)
#define tx_to_ppc440spe_adma_slot(tx) \
container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
/* Default polynomial (for 440SP is only available) */
#define PPC440SPE_DEFAULT_POLY 0x4d
#define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
#define PPC440SPE_ADMA_WATCHDOG_MSEC 3
#define PPC440SPE_ADMA_THRESHOLD 1
#define PPC440SPE_DMA0_ID 0
#define PPC440SPE_DMA1_ID 1
#define PPC440SPE_XOR_ID 2
#define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL
/* this is the XOR_CBBCR width */
#define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)
#define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
#define PPC440SPE_RXOR_RUN 0
#define MQ0_CF2H_RXOR_BS_MASK 0x1FF
#undef ADMA_LL_DEBUG
/**
* struct ppc440spe_adma_device - internal representation of an ADMA device
* @dev: device
* @dma_reg: base for DMAx register access
* @xor_reg: base for XOR register access
* @i2o_reg: base for I2O register access
* @id: HW ADMA Device selector
* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
* @dma_desc_pool: base of DMA descriptor region (DMA address)
* @pool_size: size of the pool
* @irq: DMAx or XOR irq number
* @err_irq: DMAx error irq number
* @common: embedded struct dma_device
*/
struct ppc440spe_adma_device {
struct device *dev;
struct dma_regs __iomem *dma_reg;
struct xor_regs __iomem *xor_reg;
struct i2o_regs __iomem *i2o_reg;
int id;
void *dma_desc_pool_virt;
dma_addr_t dma_desc_pool;
size_t pool_size;
int irq;
int err_irq;
struct dma_device common;
};
/**
* struct ppc440spe_adma_chan - internal representation of an ADMA channel
* @lock: serializes enqueue/dequeue operations to the slot pool
* @device: parent device
* @chain: device chain view of the descriptors
* @common: common dmaengine channel object members
* @all_slots: complete domain of slots usable by the channel
* @pending: allows batching of hardware operations
* @completed_cookie: identifier for the most recently completed operation
* @slots_allocated: records the actual size of the descriptor slot pool
* @hw_chain_inited: h/w descriptor chain initialization flag
* @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
* @needs_unmap: if buffers should not be unmapped upon final processing
* @pdest_page: P destination page for async validate operation
* @qdest_page: Q destination page for async validate operation
* @pdest: P dma addr for async validate operation
* @qdest: Q dma addr for async validate operation
*/
struct ppc440spe_adma_chan {
spinlock_t lock;
struct ppc440spe_adma_device *device;
struct list_head chain;
struct dma_chan common;
struct list_head all_slots;
struct ppc440spe_adma_desc_slot *last_used;
int pending;
dma_cookie_t completed_cookie;
int slots_allocated;
int hw_chain_inited;
struct tasklet_struct irq_tasklet;
u8 needs_unmap;
struct page *pdest_page;
struct page *qdest_page;
dma_addr_t pdest;
dma_addr_t qdest;
};
struct ppc440spe_rxor {
u32 addrl;
u32 addrh;
int len;
int xor_count;
int addr_count;
int desc_count;
int state;
};
/**
* struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
* @phys: hardware address of the hardware descriptor chain
* @group_head: first operation in a transaction
* @hw_next: pointer to the next descriptor in chain
* @async_tx: support for the async_tx api
* @slot_node: node on the iop_adma_chan.all_slots list
* @chain_node: node on the op_adma_chan.chain list
* @group_list: list of slots that make up a multi-descriptor transaction
* for example transfer lengths larger than the supported hw max
* @unmap_len: transaction bytecount
* @hw_desc: virtual address of the hardware descriptor chain
* @stride: currently chained or not
* @idx: pool index
* @slot_cnt: total slots used in an transaction (group of operations)
* @src_cnt: number of sources set in this descriptor
* @dst_cnt: number of destinations set in the descriptor
* @slots_per_op: number of slots per operation
* @descs_per_op: number of slot per P/Q operation see comment
* for ppc440spe_prep_dma_pqxor function
* @flags: desc state/type
* @reverse_flags: 1 if a corresponding rxor address uses reversed address order
* @xor_check_result: result of zero sum
* @crc32_result: result crc calculation
*/
struct ppc440spe_adma_desc_slot {
dma_addr_t phys;
struct ppc440spe_adma_desc_slot *group_head;
struct ppc440spe_adma_desc_slot *hw_next;
struct dma_async_tx_descriptor async_tx;
struct list_head slot_node;
struct list_head chain_node; /* node in channel ops list */
struct list_head group_list; /* list */
unsigned int unmap_len;
void *hw_desc;
u16 stride;
u16 idx;
u16 slot_cnt;
u8 src_cnt;
u8 dst_cnt;
u8 slots_per_op;
u8 descs_per_op;
unsigned long flags;
unsigned long reverse_flags[8];
#define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */
#define PPC440SPE_ZERO_P 1 /* clear P destionaion */
#define PPC440SPE_ZERO_Q 2 /* clear Q destination */
#define PPC440SPE_COHERENT 3 /* src/dst are coherent */
#define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */
#define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */
#define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */
#define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */
#define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */
#define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */
#define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */
#define PPC440SPE_DESC_PCHECK 13
#define PPC440SPE_DESC_QCHECK 14
#define PPC440SPE_DESC_RXOR_MSK 0x3
struct ppc440spe_rxor rxor_cursor;
union {
u32 *xor_check_result;
u32 *crc32_result;
};
};
#endif /* _PPC440SPE_ADMA_H */

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drivers/dma/ppc4xx/dma.h Normal file
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@ -0,0 +1,223 @@
/*
* 440SPe's DMA engines support header file
*
* 2006-2009 (C) DENX Software Engineering.
*
* Author: Yuri Tikhonov <yur@emcraft.com>
*
* This file is licensed under the term of the GNU General Public License
* version 2. The program licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef _PPC440SPE_DMA_H
#define _PPC440SPE_DMA_H
#include <linux/types.h>
/* Number of elements in the array with statical CDBs */
#define MAX_STAT_DMA_CDBS 16
/* Number of DMA engines available on the contoller */
#define DMA_ENGINES_NUM 2
/* Maximum h/w supported number of destinations */
#define DMA_DEST_MAX_NUM 2
/* FIFO's params */
#define DMA0_FIFO_SIZE 0x1000
#define DMA1_FIFO_SIZE 0x1000
#define DMA_FIFO_ENABLE (1<<12)
/* DMA Configuration Register. Data Transfer Engine PLB Priority: */
#define DMA_CFG_DXEPR_LP (0<<26)
#define DMA_CFG_DXEPR_HP (3<<26)
#define DMA_CFG_DXEPR_HHP (2<<26)
#define DMA_CFG_DXEPR_HHHP (1<<26)
/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
#define DMA_CFG_DFMPP_LP (0<<23)
#define DMA_CFG_DFMPP_HP (3<<23)
#define DMA_CFG_DFMPP_HHP (2<<23)
#define DMA_CFG_DFMPP_HHHP (1<<23)
/* DMA Configuration Register. Force 64-byte Alignment */
#define DMA_CFG_FALGN (1 << 19)
/*UIC0:*/
#define D0CPF_INT (1<<12)
#define D0CSF_INT (1<<11)
#define D1CPF_INT (1<<10)
#define D1CSF_INT (1<<9)
/*UIC1:*/
#define DMAE_INT (1<<9)
/* I2O IOP Interrupt Mask Register */
#define I2O_IOPIM_P0SNE (1<<3)
#define I2O_IOPIM_P0EM (1<<5)
#define I2O_IOPIM_P1SNE (1<<6)
#define I2O_IOPIM_P1EM (1<<8)
/* DMA CDB fields */
#define DMA_CDB_MSK (0xF)
#define DMA_CDB_64B_ADDR (1<<2)
#define DMA_CDB_NO_INT (1<<3)
#define DMA_CDB_STATUS_MSK (0x3)
#define DMA_CDB_ADDR_MSK (0xFFFFFFF0)
/* DMA CDB OpCodes */
#define DMA_CDB_OPC_NO_OP (0x00)
#define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
#define DMA_CDB_OPC_MULTICAST (0x05)
#define DMA_CDB_OPC_DFILL128 (0x24)
#define DMA_CDB_OPC_DCHECK128 (0x23)
#define DMA_CUED_XOR_BASE (0x10000000)
#define DMA_CUED_XOR_HB (0x00000008)
#ifdef CONFIG_440SP
#define DMA_CUED_MULT1_OFF 0
#define DMA_CUED_MULT2_OFF 8
#define DMA_CUED_MULT3_OFF 16
#define DMA_CUED_REGION_OFF 24
#define DMA_CUED_XOR_WIN_MSK (0xFC000000)
#else
#define DMA_CUED_MULT1_OFF 2
#define DMA_CUED_MULT2_OFF 10
#define DMA_CUED_MULT3_OFF 18
#define DMA_CUED_REGION_OFF 26
#define DMA_CUED_XOR_WIN_MSK (0xF0000000)
#endif
#define DMA_CUED_REGION_MSK 0x3
#define DMA_RXOR123 0x0
#define DMA_RXOR124 0x1
#define DMA_RXOR125 0x2
#define DMA_RXOR12 0x3
/* S/G addresses */
#define DMA_CDB_SG_SRC 1
#define DMA_CDB_SG_DST1 2
#define DMA_CDB_SG_DST2 3
/*
* DMAx engines Command Descriptor Block Type
*/
struct dma_cdb {
/*
* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
*/
u8 pad0[2]; /* reserved */
u8 attr; /* attributes */
u8 opc; /* opcode */
u32 sg1u; /* upper SG1 address */
u32 sg1l; /* lower SG1 address */
u32 cnt; /* SG count, 3B used */
u32 sg2u; /* upper SG2 address */
u32 sg2l; /* lower SG2 address */
u32 sg3u; /* upper SG3 address */
u32 sg3l; /* lower SG3 address */
};
/*
* DMAx hardware registers (p.515 in 440SPe UM 1.22)
*/
struct dma_regs {
u32 cpfpl;
u32 cpfph;
u32 csfpl;
u32 csfph;
u32 dsts;
u32 cfg;
u8 pad0[0x8];
u16 cpfhp;
u16 cpftp;
u16 csfhp;
u16 csftp;
u8 pad1[0x8];
u32 acpl;
u32 acph;
u32 s1bpl;
u32 s1bph;
u32 s2bpl;
u32 s2bph;
u32 s3bpl;
u32 s3bph;
u8 pad2[0x10];
u32 earl;
u32 earh;
u8 pad3[0x8];
u32 seat;
u32 sead;
u32 op;
u32 fsiz;
};
/*
* I2O hardware registers (p.528 in 440SPe UM 1.22)
*/
struct i2o_regs {
u32 ists;
u32 iseat;
u32 isead;
u8 pad0[0x14];
u32 idbel;
u8 pad1[0xc];
u32 ihis;
u32 ihim;
u8 pad2[0x8];
u32 ihiq;
u32 ihoq;
u8 pad3[0x8];
u32 iopis;
u32 iopim;
u32 iopiq;
u8 iopoq;
u8 pad4[3];
u16 iiflh;
u16 iiflt;
u16 iiplh;
u16 iiplt;
u16 ioflh;
u16 ioflt;
u16 ioplh;
u16 ioplt;
u32 iidc;
u32 ictl;
u32 ifcpp;
u8 pad5[0x4];
u16 mfac0;
u16 mfac1;
u16 mfac2;
u16 mfac3;
u16 mfac4;
u16 mfac5;
u16 mfac6;
u16 mfac7;
u16 ifcfh;
u16 ifcht;
u8 pad6[0x4];
u32 iifmc;
u32 iodb;
u32 iodbc;
u32 ifbal;
u32 ifbah;
u32 ifsiz;
u32 ispd0;
u32 ispd1;
u32 ispd2;
u32 ispd3;
u32 ihipl;
u32 ihiph;
u32 ihopl;
u32 ihoph;
u32 iiipl;
u32 iiiph;
u32 iiopl;
u32 iioph;
u32 ifcpl;
u32 ifcph;
u8 pad7[0x8];
u32 iopt;
};
#endif /* _PPC440SPE_DMA_H */

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drivers/dma/ppc4xx/xor.h Normal file
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/*
* 440SPe's XOR engines support header file
*
* 2006-2009 (C) DENX Software Engineering.
*
* Author: Yuri Tikhonov <yur@emcraft.com>
*
* This file is licensed under the term of the GNU General Public License
* version 2. The program licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef _PPC440SPE_XOR_H
#define _PPC440SPE_XOR_H
#include <linux/types.h>
/* Number of XOR engines available on the contoller */
#define XOR_ENGINES_NUM 1
/* Number of operands supported in the h/w */
#define XOR_MAX_OPS 16
/*
* XOR Command Block Control Register bits
*/
#define XOR_CBCR_LNK_BIT (1<<31) /* link present */
#define XOR_CBCR_TGT_BIT (1<<30) /* target present */
#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */
#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */
/*
* XORCore Status Register bits
*/
#define XOR_SR_XCP_BIT (1<<31) /* core processing */
#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */
#define XOR_SR_IC_BIT (1<<16) /* invalid command */
#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */
#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */
#define XOR_SR_CBC_BIT (1<<1) /* CB complete */
#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */
/*
* XORCore Control Set and Reset Register bits
*/
#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
#define XOR_CRSR_XAE_BIT (1<<30) /* enable */
#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */
#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */
#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */
/*
* XORCore Interrupt Enable Register
*/
#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
/*
* XOR Accelerator engine Command Block Type
*/
struct xor_cb {
/*
* Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
*/
u32 cbc; /* control */
u32 cbbc; /* byte count */
u32 cbs; /* status */
u8 pad0[4]; /* reserved */
u32 cbtah; /* target address high */
u32 cbtal; /* target address low */
u32 cblah; /* link address high */
u32 cblal; /* link address low */
struct {
u32 h;
u32 l;
} __attribute__ ((packed)) ops[16];
} __attribute__ ((packed));
/*
* XOR hardware registers Table 19-3, UM 1.22
*/
struct xor_regs {
u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
u8 pad0[352]; /* reserved */
u32 cbcr; /* CB control register */
u32 cbbcr; /* CB byte count register */
u32 cbsr; /* CB status register */
u8 pad1[4]; /* reserved */
u32 cbtahr; /* operand target address high register */
u32 cbtalr; /* operand target address low register */
u32 cblahr; /* CB link address high register */
u32 cblalr; /* CB link address low register */
u32 crsr; /* control set register */
u32 crrr; /* control reset register */
u32 ccbahr; /* current CB address high register */
u32 ccbalr; /* current CB address low register */
u32 plbr; /* PLB configuration register */
u32 ier; /* interrupt enable register */
u32 pecr; /* parity error count register */
u32 sr; /* status register */
u32 revidr; /* revision ID register */
};
#endif /* _PPC440SPE_XOR_H */