dt-bindings: gpio: gpio-mvebu: convert txt binding to DT schema format
Convert the existing device tree binding to DT schema format. The old binding listed the interrupt-controller and related properties as required but there are sufficiently many existing usages without it that the YAML binding does not make the interrupt properties required. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
Chris Packham
Bartosz Golaszewski
parent
2b038e786f
commit
1282157a6c
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@ -72,7 +72,7 @@ mpp19 19 gpio, uart0(rxd), sdio(pw_off)
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GPIO:
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-----
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For common binding part and usage, refer to
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Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
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Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
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Required properties:
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@ -156,7 +156,7 @@ GPIO:
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-----
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For common binding part and usage, refer to
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Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
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Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
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Required properties:
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@ -1,93 +0,0 @@
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* Marvell EBU GPIO controller
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Required properties:
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- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
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"marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
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"marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
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Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
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should be used for the Discovery MV78200.
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"marvel,armadaxp-gpio" should be used for all Armada XP SoCs
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(MV78230, MV78260, MV78460).
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"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
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SoCs (either from AP or CP), see
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Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
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for specific details about the offset property.
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- reg: Address and length of the register set for the device. Only one
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entry is expected, except for the "marvell,armadaxp-gpio" variant
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for which two entries are expected: one for the general registers,
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one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
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- interrupts: The list of interrupts that are used for all the pins
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managed by this GPIO bank. There can be more than one interrupt
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(example: 1 interrupt per 8 pins on Armada XP, which means 4
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interrupts per bank of 32 GPIOs).
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. Should be two.
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The first cell is the GPIO number.
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The second cell is used to specify flags:
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bits[3:0] trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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- gpio-controller: marks the device node as a gpio controller
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- ngpios: number of GPIOs this controller has
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- #gpio-cells: Should be two. The first cell is the pin number. The
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second cell is reserved for flags, unused at the moment.
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Optional properties:
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In order to use the GPIO lines in PWM mode, some additional optional
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properties are required.
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- compatible: Must contain "marvell,armada-370-gpio"
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- reg: an additional register set is needed, for the GPIO Blink
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Counter on/off registers.
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- reg-names: Must contain an entry "pwm" corresponding to the
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additional register range needed for PWM operation.
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- #pwm-cells: Should be two. The first cell is the GPIO line number. The
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second cell is the period in nanoseconds.
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- clocks: Must be a phandle to the clock for the GPIO controller.
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Example:
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gpio0: gpio@d0018100 {
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compatible = "marvell,armadaxp-gpio";
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reg = <0xd0018100 0x40>,
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<0xd0018800 0x30>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <16>, <17>, <18>, <19>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,armada-370-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <17>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>;
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clocks = <&coreclk 0>;
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};
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@ -0,0 +1,146 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell EBU GPIO controller
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maintainers:
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- Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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- Andrew Lunn <andrew@lunn.ch>
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properties:
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compatible:
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oneOf:
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- enum:
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- marvell,armada-8k-gpio
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- marvell,orion-gpio
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- items:
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- enum:
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- marvell,mv78200-gpio
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- marvell,armada-370-gpio
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- marvell,armadaxp-gpio
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- const: marvell,orion-gpio
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reg:
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description: |
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Address and length of the register set for the device. Not used for
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marvell,armada-8k-gpio.
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For the "marvell,armadaxp-gpio" variant a second entry is expected for
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the per-cpu registers. For other variants second entry can be provided,
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for the PWM function using the GPIO Blink Counter on/off registers.
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minItems: 1
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maxItems: 2
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reg-names:
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items:
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- const: gpio
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- const: pwm
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minItems: 1
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interrupts:
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description: |
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The list of interrupts that are used for all the pins managed by this
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GPIO bank. There can be more than one interrupt (example: 1 interrupt
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per 8 pins on Armada XP, which means 4 interrupts per bank of 32
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GPIOs).
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minItems: 1
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maxItems: 4
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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gpio-controller: true
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ngpios:
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minimum: 1
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maximum: 32
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"#gpio-cells":
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const: 2
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"#pwm-cells":
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description:
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The first cell is the GPIO line number. The second cell is the period
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in nanoseconds.
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const: 2
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clocks:
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description:
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Clock(s) used for PWM function.
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items:
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- description: Core clock
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- description: AXI bus clock
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minItems: 1
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clock-names:
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items:
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- const: core
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- const: axi
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minItems: 1
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required:
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- compatible
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- gpio-controller
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- ngpios
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- "#gpio-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: marvell,armada-8k-gpio
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then:
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required:
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- offset
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else:
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required:
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- reg
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- if:
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properties:
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compatible:
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contains:
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const: marvell,armadaxp-gpio
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then:
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properties:
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reg:
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minItems: 2
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reg-names:
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minItems: 2
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unevaluatedProperties: true
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examples:
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- |
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gpio@d0018100 {
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compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
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reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <16>, <17>, <18>, <19>;
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};
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- |
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gpio@18140 {
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compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <17>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>;
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clocks = <&coreclk 0>;
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};
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@ -16330,7 +16330,7 @@ L: linux-pwm@vger.kernel.org
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S: Maintained
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Q: https://patchwork.ozlabs.org/project/linux-pwm/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git
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F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
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F: Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
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F: Documentation/devicetree/bindings/pwm/
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F: Documentation/driver-api/pwm.rst
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F: drivers/gpio/gpio-mvebu.c
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