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perf c2c: Update documentation for store metric 'N/A'
The 'N/A' metric is added for store operations, update documentation to reflect changes in the report table. Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Jiri Olsa <jolsa@kernel.org> Cc: Adam Li <adamli@amperemail.onmicrosoft.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ali Saidi <alisaidi@amazon.com> Cc: Alyssa Ross <hi@alyssa.is> Cc: German Gomez <german.gomez@arm.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Joe Mario <jmario@redhat.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Li Huafei <lihuafei1@huawei.com> Cc: Like Xu <likexu@tencent.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20220518055729.1869566-4-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -189,9 +189,10 @@ For each cacheline in the 1) list we display following data:
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Total stores
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- sum of all store accesses
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Store Reference - L1Hit, L1Miss
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Store Reference - L1Hit, L1Miss, N/A
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L1Hit - store accesses that hit L1
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L1Miss - store accesses that missed L1
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N/A - store accesses with memory level is not available
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Core Load Hit - FB, L1, L2
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- count of load hits in FB (Fill Buffer), L1 and L2 cache
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@ -210,8 +211,9 @@ For each offset in the 2) list we display following data:
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HITM - Rmt, Lcl
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- % of Remote/Local HITM accesses for given offset within cacheline
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Store Refs - L1 Hit, L1 Miss
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- % of store accesses that hit/missed L1 for given offset within cacheline
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Store Refs - L1 Hit, L1 Miss, N/A
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- % of store accesses that hit L1, missed L1 and N/A (no available) memory
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level for given offset within cacheline
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Data address - Offset
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- offset address
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