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tty: serial: msm: Add mask value for UART_DM registers
The bit masks for RFR_LEVEL1 and STALE_TIMEOUT_MSB values in MR1 and IPR registers respectively are different for UART and UART_DM hardware cores. We have been using UART core mask values for these. Add the same for UART_DM core. There is no bit setting as UART_IPR_RXSTALE_LAST for UART_DM core so do it only for UART core. Signed-off-by: Pramod Gurav <gpramod@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 22 additions and 6 deletions
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@ -421,7 +421,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int baud)
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static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
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{
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unsigned int rxstale, watermark;
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unsigned int rxstale, watermark, mask;
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struct msm_port *msm_port = UART_TO_MSM(port);
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const struct msm_baud_map *entry;
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@ -432,8 +432,15 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
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/* RX stale watermark */
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rxstale = entry->rxstale;
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watermark = UART_IPR_STALE_LSB & rxstale;
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watermark |= UART_IPR_RXSTALE_LAST;
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watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
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if (msm_port->is_uartdm) {
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mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
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} else {
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watermark |= UART_IPR_RXSTALE_LAST;
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mask = UART_IPR_STALE_TIMEOUT_MSB;
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}
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watermark |= mask & (rxstale << 2);
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msm_write(port, watermark, UART_IPR);
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/* set RX watermark */
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@ -476,7 +483,7 @@ static void msm_init_clock(struct uart_port *port)
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static int msm_startup(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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unsigned int data, rfr_level;
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unsigned int data, rfr_level, mask;
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int ret;
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snprintf(msm_port->name, sizeof(msm_port->name),
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@ -496,11 +503,18 @@ static int msm_startup(struct uart_port *port)
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/* set automatic RFR level */
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data = msm_read(port, UART_MR1);
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data &= ~UART_MR1_AUTO_RFR_LEVEL1;
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if (msm_port->is_uartdm)
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mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
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else
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mask = UART_MR1_AUTO_RFR_LEVEL1;
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data &= ~mask;
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data &= ~UART_MR1_AUTO_RFR_LEVEL0;
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data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
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data |= mask & (rfr_level << 2);
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data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
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msm_write(port, data, UART_MR1);
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return 0;
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}
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@ -20,6 +20,7 @@
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#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
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#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
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#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
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#define UART_MR1_RX_RDY_CTL (1 << 7)
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#define UART_MR1_CTS_CTL (1 << 6)
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@ -78,6 +79,7 @@
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#define UART_IPR_RXSTALE_LAST 0x20
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#define UART_IPR_STALE_LSB 0x1F
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#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
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#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
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#define UART_IPR 0x0018
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#define UART_TFWR 0x001C
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