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clk: rockchip: fix rk3188 USB HSIC PHY clock divider
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11). Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
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RK2928_CLKGATE_CON(3), 6, GFLAGS),
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DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
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RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
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RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
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MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
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RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
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