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drm/radeon/kms: adjust evergreen display watermark setup
This patch fixes two issues: - A disabled crtc does not use any lb, so return 0 for lb size. This makes the display priority calculation more exact. - Only use 1/2 and whole lb partitions. Using smaller partitions can cause underflow to one of the displays if you have multiple large displays on the same lb. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=34534 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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1 changed files with 44 additions and 45 deletions
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@ -353,7 +353,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
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struct drm_display_mode *mode,
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struct drm_display_mode *mode,
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struct drm_display_mode *other_mode)
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struct drm_display_mode *other_mode)
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{
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{
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u32 tmp = 0;
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u32 tmp;
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/*
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/*
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* Line Buffer Setup
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* Line Buffer Setup
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* There are 3 line buffers, each one shared by 2 display controllers.
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* There are 3 line buffers, each one shared by 2 display controllers.
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@ -363,64 +363,63 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
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* first display controller
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* first display controller
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* 0 - first half of lb (3840 * 2)
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* 0 - first half of lb (3840 * 2)
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* 1 - first 3/4 of lb (5760 * 2)
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* 1 - first 3/4 of lb (5760 * 2)
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* 2 - whole lb (7680 * 2)
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* 2 - whole lb (7680 * 2), other crtc must be disabled
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* 3 - first 1/4 of lb (1920 * 2)
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* 3 - first 1/4 of lb (1920 * 2)
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* second display controller
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* second display controller
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* 4 - second half of lb (3840 * 2)
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* 4 - second half of lb (3840 * 2)
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* 5 - second 3/4 of lb (5760 * 2)
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* 5 - second 3/4 of lb (5760 * 2)
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* 6 - whole lb (7680 * 2)
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* 6 - whole lb (7680 * 2), other crtc must be disabled
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* 7 - last 1/4 of lb (1920 * 2)
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* 7 - last 1/4 of lb (1920 * 2)
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*/
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*/
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if (mode && other_mode) {
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/* this can get tricky if we have two large displays on a paired group
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if (mode->hdisplay > other_mode->hdisplay) {
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* of crtcs. Ideally for multiple large displays we'd assign them to
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if (mode->hdisplay > 2560)
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* non-linked crtcs for maximum line buffer allocation.
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tmp = 1; /* 3/4 */
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*/
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else
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if (radeon_crtc->base.enabled && mode) {
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tmp = 0; /* 1/2 */
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if (other_mode)
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} else if (other_mode->hdisplay > mode->hdisplay) {
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if (other_mode->hdisplay > 2560)
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tmp = 3; /* 1/4 */
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else
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tmp = 0; /* 1/2 */
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} else
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tmp = 0; /* 1/2 */
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tmp = 0; /* 1/2 */
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} else if (mode)
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else
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tmp = 2; /* whole */
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tmp = 2; /* whole */
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else if (other_mode)
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} else
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tmp = 3; /* 1/4 */
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tmp = 0;
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/* second controller of the pair uses second half of the lb */
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/* second controller of the pair uses second half of the lb */
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if (radeon_crtc->crtc_id % 2)
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if (radeon_crtc->crtc_id % 2)
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tmp += 4;
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tmp += 4;
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WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
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WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
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switch (tmp) {
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if (radeon_crtc->base.enabled && mode) {
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case 0:
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switch (tmp) {
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case 4:
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case 0:
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default:
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case 4:
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if (ASIC_IS_DCE5(rdev))
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default:
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return 4096 * 2;
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if (ASIC_IS_DCE5(rdev))
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else
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return 4096 * 2;
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return 3840 * 2;
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else
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case 1:
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return 3840 * 2;
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case 5:
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case 1:
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if (ASIC_IS_DCE5(rdev))
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case 5:
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return 6144 * 2;
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if (ASIC_IS_DCE5(rdev))
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else
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return 6144 * 2;
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return 5760 * 2;
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else
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case 2:
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return 5760 * 2;
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case 6:
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case 2:
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if (ASIC_IS_DCE5(rdev))
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case 6:
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return 8192 * 2;
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if (ASIC_IS_DCE5(rdev))
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else
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return 8192 * 2;
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return 7680 * 2;
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else
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case 3:
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return 7680 * 2;
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case 7:
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case 3:
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if (ASIC_IS_DCE5(rdev))
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case 7:
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return 2048 * 2;
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if (ASIC_IS_DCE5(rdev))
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else
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return 2048 * 2;
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return 1920 * 2;
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else
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return 1920 * 2;
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}
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}
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}
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/* controller not enabled, so no lb used */
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return 0;
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}
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}
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static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
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static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
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