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drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV
Workaround for dual port PS dispatch on GT1. v2: pull in register definition & offset handling v3: use IVB GT1 macro to get the right regs (Ben) v4: add for VLV too (Ben) v5: don't read the reg, it's masked so we'll only enable the one extra bit (Chris) v6: use a _GT2 suffix for the second reg (Chris) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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3 changed files with 17 additions and 0 deletions
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@ -1134,6 +1134,7 @@ static bool IS_DISPLAYREG(u32 reg)
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switch (reg) {
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case GEN7_ROW_CHICKEN2:
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case GEN7_HALF_SLICE_CHICKEN1:
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return false;
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default:
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break;
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@ -4305,6 +4305,11 @@
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#define GEN7_L3LOG_BASE 0xB070
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#define GEN7_L3LOG_SIZE 0x80
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#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
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#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
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#define GEN7_MAX_PS_THREAD_DEP (8<<12)
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#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
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#define GEN7_ROW_CHICKEN2 0xe4f4
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#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
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#define DOP_CLOCK_GATING_DISABLE (1<<0)
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@ -3592,6 +3592,14 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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/* WaDisablePSDDualDispatchEnable */
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if (IS_IVB_GT1(dev))
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
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_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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else
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
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_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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@ -3679,6 +3687,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
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_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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