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drm/amdgpu: Fix bugs in amdgpu_device_gpu_recover in XGMI case.
Issue 1: In XGMI case amdgpu_device_lock_adev for other devices in hive was called to late, after access to their repsective schedulers. So relocate the lock to the begining of accessing the other devs. Issue 2: Using amdgpu_device_ip_need_full_reset to switch the device list from all devices in hive to the single 'master' device who owns this reset call is wrong because when stopping schedulers we iterate all the devices in hive but when restarting we will only reactivate the 'master' device. Also, in case amdgpu_device_pre_asic_reset conlcudes that full reset IS needed we then have to stop schedulers for all devices in hive and not only the 'master' but with amdgpu_device_ip_need_full_reset we already missed the opprotunity do to so. So just remove this logic and always stop and start all schedulers for all devices in hive. Also minor cleanup and print fix. v4: Minor coding style fix. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 10 additions and 13 deletions
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@ -3823,15 +3823,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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device_list_handle = &device_list;
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}
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/*
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* Mark these ASICs to be reseted as untracked first
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* And add them back after reset completed
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*/
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head)
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amdgpu_unregister_gpu_instance(tmp_adev);
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/* block all schedulers and reset given job's ring */
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
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if (tmp_adev != adev)
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amdgpu_device_lock_adev(tmp_adev, false);
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/*
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* Mark these ASICs to be reseted as untracked first
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* And add them back after reset completed
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*/
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amdgpu_unregister_gpu_instance(tmp_adev);
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/* disable ras on ALL IPs */
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if (amdgpu_device_ip_need_full_reset(tmp_adev))
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amdgpu_ras_suspend(tmp_adev);
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@ -3857,9 +3858,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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dma_fence_is_signaled(job->base.s_fence->parent))
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job_signaled = true;
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if (!amdgpu_device_ip_need_full_reset(adev))
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device_list_handle = &device_list;
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if (job_signaled) {
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dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
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goto skip_hw_reset;
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@ -3881,7 +3879,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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if (tmp_adev == adev)
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continue;
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amdgpu_device_lock_adev(tmp_adev, false);
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r = amdgpu_device_pre_asic_reset(tmp_adev,
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NULL,
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&need_full_reset);
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@ -3930,10 +3927,10 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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if (r) {
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/* bad news, how to tell it to userspace ? */
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dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
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dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
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amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
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} else {
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dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
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dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
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}
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amdgpu_device_unlock_adev(tmp_adev);
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