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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
Split up crtc_state->base to hw where appropriate. This is done using the following patch: @@ struct intel_crtc_state *T; identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$"; @@ -T->base.x +T->hw.x @@ struct drm_crtc_state *T; identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$"; @@ -to_intel_crtc_state(T)->base.x +to_intel_crtc_state(T)->hw.x Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031112610.27608-4-maarten.lankhorst@linux.intel.com
This commit is contained in:
parent
aa42a50add
commit
1326a92c34
24 changed files with 316 additions and 313 deletions
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@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
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if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
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const struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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&pipe_config->hw.adjusted_mode;
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u32 dss_ctl2;
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u16 hactive = adjusted_mode->crtc_hdisplay;
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u16 dl_buffer_depth;
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@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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const struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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&pipe_config->hw.adjusted_mode;
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enum port port;
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enum transcoder dsi_trans;
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/* horizontal timings */
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@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
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{
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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&pipe_config->hw.adjusted_mode;
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if (intel_dsi->dual_link) {
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adjusted_mode->crtc_hdisplay *= 2;
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@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
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pipe_config->port_clock =
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cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
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pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
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pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
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if (intel_dsi->dual_link)
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pipe_config->base.adjusted_mode.crtc_clock *= 2;
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pipe_config->hw.adjusted_mode.crtc_clock *= 2;
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gen11_dsi_get_timings(encoder, pipe_config);
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pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
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@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
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const struct drm_display_mode *fixed_mode =
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intel_connector->panel.fixed_mode;
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struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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&pipe_config->hw.adjusted_mode;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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intel_fixed_panel_mode(fixed_mode, adjusted_mode);
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@ -234,7 +234,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
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static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
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{
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->base.adjusted_mode;
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&crtc_state->hw.adjusted_mode;
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int i;
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for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
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@ -695,7 +695,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_connector *connector = conn_state->connector;
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->base.adjusted_mode;
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&crtc_state->hw.adjusted_mode;
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enum port port = encoder->port;
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enum pipe pipe = crtc->pipe;
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@ -1937,7 +1937,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
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to_i915(crtc_state->base.crtc->dev);
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int min_cdclk;
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if (!crtc_state->base.enable)
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if (!crtc_state->hw.enable)
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return 0;
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min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
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@ -2074,7 +2074,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
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for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
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int ret;
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if (crtc_state->base.enable)
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if (crtc_state->hw.enable)
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min_voltage_level = crtc_state->min_voltage_level;
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else
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min_voltage_level = 0;
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@ -2168,7 +2168,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
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vco = dev_priv->skl_preferred_vco_freq;
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for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
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if (!crtc_state->base.enable)
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if (!crtc_state->hw.enable)
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continue;
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if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
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@ -2281,7 +2281,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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if (!crtc_state->base.active ||
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if (!crtc_state->hw.active ||
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drm_atomic_crtc_needs_modeset(&crtc_state->base))
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continue;
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@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut)
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static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
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{
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return !crtc_state->base.degamma_lut &&
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!crtc_state->base.ctm &&
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crtc_state->base.gamma_lut &&
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lut_is_legacy(crtc_state->base.gamma_lut);
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return !crtc_state->hw.degamma_lut &&
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!crtc_state->hw.ctm &&
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crtc_state->hw.gamma_lut &&
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lut_is_legacy(crtc_state->hw.gamma_lut);
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}
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/*
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@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
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static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
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u16 coeffs[9])
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{
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const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
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const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
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const u64 *input;
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u64 temp[9];
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int i;
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@ -274,7 +274,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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bool limited_color_range = ilk_csc_limited_range(crtc_state);
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if (crtc_state->base.ctm) {
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if (crtc_state->hw.ctm) {
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u16 coeff[9];
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ilk_csc_convert_ctm(crtc_state, coeff);
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@ -312,7 +312,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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if (crtc_state->base.ctm) {
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if (crtc_state->hw.ctm) {
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u16 coeff[9];
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ilk_csc_convert_ctm(crtc_state, coeff);
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@ -342,8 +342,8 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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if (crtc_state->base.ctm) {
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const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
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if (crtc_state->hw.ctm) {
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const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
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u16 coeffs[9] = {};
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int i;
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@ -435,7 +435,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
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static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
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{
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i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
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i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
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}
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static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
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@ -525,7 +525,7 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
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static void i965_load_luts(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
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i9xx_load_luts(crtc_state);
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@ -548,7 +548,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
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static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
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i9xx_load_luts(crtc_state);
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@ -655,8 +655,8 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
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static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
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if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
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i9xx_load_luts(crtc_state);
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@ -678,8 +678,8 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
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static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
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if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
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i9xx_load_luts(crtc_state);
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@ -704,7 +704,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
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const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
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const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
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u32 i;
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/*
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@ -766,7 +766,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
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static void glk_load_luts(const struct intel_crtc_state *crtc_state)
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{
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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/*
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@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
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* the degama LUT so that we don't have to reload
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* it every time the pipe CSC is being enabled.
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*/
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if (crtc_state->base.degamma_lut)
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if (crtc_state->hw.degamma_lut)
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glk_load_degamma_lut(crtc_state);
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else
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glk_load_degamma_lut_linear(crtc_state);
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@ -823,7 +823,7 @@ static void
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icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
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const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
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const struct drm_color_lut *lut = blob->data;
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struct intel_dsb *dsb = intel_dsb_get(crtc);
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enum pipe pipe = crtc->pipe;
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@ -855,7 +855,7 @@ static void
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icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
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const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
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const struct drm_color_lut *lut = blob->data;
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const struct drm_color_lut *entry;
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struct intel_dsb *dsb = intel_dsb_get(crtc);
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@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
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static void icl_load_luts(const struct intel_crtc_state *crtc_state)
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{
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct intel_dsb *dsb = intel_dsb_get(crtc);
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if (crtc_state->base.degamma_lut)
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if (crtc_state->hw.degamma_lut)
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glk_load_degamma_lut(crtc_state);
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switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
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@ -991,8 +991,8 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
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static void chv_load_luts(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
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cherryview_load_csc_matrix(crtc_state);
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@ -1063,7 +1063,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
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intel_atomic_get_old_crtc_state(state, crtc);
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struct intel_plane *plane;
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if (!new_crtc_state->base.active ||
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if (!new_crtc_state->hw.active ||
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drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
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return 0;
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@ -1107,8 +1107,8 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
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static int check_luts(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
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const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
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const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
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const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
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int gamma_length, degamma_length;
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u32 gamma_tests, degamma_tests;
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@ -1156,7 +1156,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
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return ret;
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crtc_state->gamma_enable =
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crtc_state->base.gamma_lut &&
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crtc_state->hw.gamma_lut &&
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!crtc_state->c8_planes;
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crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
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@ -1175,11 +1175,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
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if (crtc_state_is_legacy_gamma(crtc_state))
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return 0;
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if (crtc_state->base.degamma_lut)
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if (crtc_state->hw.degamma_lut)
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cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
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if (crtc_state->base.ctm)
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if (crtc_state->hw.ctm)
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cgm_mode |= CGM_PIPE_MODE_CSC;
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if (crtc_state->base.gamma_lut)
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if (crtc_state->hw.gamma_lut)
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cgm_mode |= CGM_PIPE_MODE_GAMMA;
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return cgm_mode;
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@ -1253,7 +1253,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
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return ret;
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crtc_state->gamma_enable =
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crtc_state->base.gamma_lut &&
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crtc_state->hw.gamma_lut &&
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!crtc_state->c8_planes;
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/*
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@ -1279,8 +1279,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
|
|||
if (!crtc_state->gamma_enable ||
|
||||
crtc_state_is_legacy_gamma(crtc_state))
|
||||
return GAMMA_MODE_MODE_8BIT;
|
||||
else if (crtc_state->base.gamma_lut &&
|
||||
crtc_state->base.degamma_lut)
|
||||
else if (crtc_state->hw.gamma_lut &&
|
||||
crtc_state->hw.degamma_lut)
|
||||
return GAMMA_MODE_MODE_SPLIT;
|
||||
else
|
||||
return GAMMA_MODE_MODE_10BIT;
|
||||
|
@ -1294,7 +1294,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
|
|||
* CSC comes after the LUT in degamma, RGB->YCbCr,
|
||||
* and RGB full->limited range mode.
|
||||
*/
|
||||
if (crtc_state->base.degamma_lut ||
|
||||
if (crtc_state->hw.degamma_lut ||
|
||||
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
|
||||
limited_color_range)
|
||||
return 0;
|
||||
|
@ -1312,13 +1312,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
|
|||
return ret;
|
||||
|
||||
crtc_state->gamma_enable =
|
||||
(crtc_state->base.gamma_lut ||
|
||||
crtc_state->base.degamma_lut) &&
|
||||
(crtc_state->hw.gamma_lut ||
|
||||
crtc_state->hw.degamma_lut) &&
|
||||
!crtc_state->c8_planes;
|
||||
|
||||
crtc_state->csc_enable =
|
||||
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
|
||||
crtc_state->base.ctm || limited_color_range;
|
||||
crtc_state->hw.ctm || limited_color_range;
|
||||
|
||||
crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
|
||||
|
||||
|
@ -1349,14 +1349,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
|
|||
return ret;
|
||||
|
||||
crtc_state->gamma_enable =
|
||||
crtc_state->base.gamma_lut &&
|
||||
crtc_state->hw.gamma_lut &&
|
||||
!crtc_state->c8_planes;
|
||||
|
||||
/* On GLK+ degamma LUT is controlled by csc_enable */
|
||||
crtc_state->csc_enable =
|
||||
crtc_state->base.degamma_lut ||
|
||||
crtc_state->hw.degamma_lut ||
|
||||
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
|
||||
crtc_state->base.ctm || crtc_state->limited_color_range;
|
||||
crtc_state->hw.ctm || crtc_state->limited_color_range;
|
||||
|
||||
crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
|
||||
|
||||
|
@ -1373,14 +1373,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
|
|||
{
|
||||
u32 gamma_mode = 0;
|
||||
|
||||
if (crtc_state->base.degamma_lut)
|
||||
if (crtc_state->hw.degamma_lut)
|
||||
gamma_mode |= PRE_CSC_GAMMA_ENABLE;
|
||||
|
||||
if (crtc_state->base.gamma_lut &&
|
||||
if (crtc_state->hw.gamma_lut &&
|
||||
!crtc_state->c8_planes)
|
||||
gamma_mode |= POST_CSC_GAMMA_ENABLE;
|
||||
|
||||
if (!crtc_state->base.gamma_lut ||
|
||||
if (!crtc_state->hw.gamma_lut ||
|
||||
crtc_state_is_legacy_gamma(crtc_state))
|
||||
gamma_mode |= GAMMA_MODE_MODE_8BIT;
|
||||
else
|
||||
|
@ -1393,7 +1393,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
|
|||
{
|
||||
u32 csc_mode = 0;
|
||||
|
||||
if (crtc_state->base.ctm)
|
||||
if (crtc_state->hw.ctm)
|
||||
csc_mode |= ICL_CSC_ENABLE;
|
||||
|
||||
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
|
||||
|
@ -1622,7 +1622,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
|
|||
if (!crtc_state->gamma_enable)
|
||||
return;
|
||||
|
||||
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
}
|
||||
|
||||
static struct drm_property_blob *
|
||||
|
@ -1672,9 +1672,9 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
|
|||
return;
|
||||
|
||||
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
|
||||
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
else
|
||||
crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
|
||||
crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
|
||||
}
|
||||
|
||||
static struct drm_property_blob *
|
||||
|
@ -1714,7 +1714,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
|
|||
static void chv_read_luts(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
|
||||
crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
|
||||
crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
|
||||
else
|
||||
i965_read_luts(crtc_state);
|
||||
}
|
||||
|
@ -1761,9 +1761,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
|
|||
return;
|
||||
|
||||
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
|
||||
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
else
|
||||
crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
|
||||
crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
|
||||
}
|
||||
|
||||
static struct drm_property_blob *
|
||||
|
@ -1810,9 +1810,9 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
|
|||
return;
|
||||
|
||||
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
|
||||
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
|
||||
else
|
||||
crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
|
||||
crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
|
||||
}
|
||||
|
||||
void intel_color_init(struct intel_crtc *crtc)
|
||||
|
|
|
@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
|
|||
{
|
||||
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
|
||||
pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||
}
|
||||
|
||||
static void hsw_crt_get_config(struct intel_encoder *encoder,
|
||||
|
@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
|
|||
|
||||
intel_ddi_get_config(encoder, pipe_config);
|
||||
|
||||
pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
|
||||
pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
|
||||
DRM_MODE_FLAG_NHSYNC |
|
||||
DRM_MODE_FLAG_PVSYNC |
|
||||
DRM_MODE_FLAG_NVSYNC);
|
||||
pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
|
||||
pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
|
||||
}
|
||||
|
||||
/* Note: The caller is required to filter out dpms modes not supported by the
|
||||
|
@ -162,7 +162,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
|
|||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_crt *crt = intel_encoder_to_crt(encoder);
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
|
||||
u32 adpa;
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 5)
|
||||
|
@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
|
|||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return -EINVAL;
|
||||
|
@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
|
|||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return -EINVAL;
|
||||
|
@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return -EINVAL;
|
||||
|
|
|
@ -1528,7 +1528,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
|
|||
if (pipe_config->pixel_multiplier)
|
||||
dotclock /= pipe_config->pixel_multiplier;
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
|
||||
}
|
||||
|
||||
static void icl_ddi_clock_get(struct intel_encoder *encoder,
|
||||
|
@ -1860,9 +1860,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
|
|||
BUG();
|
||||
}
|
||||
|
||||
if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
|
||||
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
|
||||
temp |= TRANS_DDI_PVSYNC;
|
||||
if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
|
||||
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
|
||||
temp |= TRANS_DDI_PHSYNC;
|
||||
|
||||
if (cpu_transcoder == TRANSCODER_EDP) {
|
||||
|
@ -3376,7 +3376,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
|
|||
{
|
||||
u32 exit_scanlines;
|
||||
struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
|
||||
u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
|
||||
u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
|
||||
|
||||
cstate->dc3co_exitline = 0;
|
||||
|
||||
|
@ -3388,7 +3388,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
|
|||
encoder->port != PORT_A)
|
||||
return;
|
||||
|
||||
if (!cstate->has_psr2 || !cstate->base.active)
|
||||
if (!cstate->has_psr2 || !cstate->hw.active)
|
||||
return;
|
||||
|
||||
/*
|
||||
|
@ -3396,7 +3396,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
|
|||
* PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
|
||||
*/
|
||||
exit_scanlines =
|
||||
intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1;
|
||||
intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
|
||||
|
||||
if (WARN_ON(exit_scanlines > crtc_vdisplay))
|
||||
return;
|
||||
|
@ -4083,7 +4083,7 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
|
|||
WARN_ON(crtc && crtc->active);
|
||||
|
||||
intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
|
||||
if (crtc_state && crtc_state->base.active)
|
||||
if (crtc_state && crtc_state->hw.active)
|
||||
intel_update_active_dpll(state, crtc, encoder);
|
||||
}
|
||||
|
||||
|
@ -4231,7 +4231,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
|
|||
else
|
||||
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= flags;
|
||||
pipe_config->hw.adjusted_mode.flags |= flags;
|
||||
|
||||
switch (temp & TRANS_DDI_BPC_MASK) {
|
||||
case TRANS_DDI_BPC_6:
|
||||
|
@ -4514,7 +4514,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder,
|
|||
|
||||
WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
|
||||
|
||||
if (!crtc_state->base.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return 0;
|
||||
|
||||
if (!crtc_state->hdmi_high_tmds_clock_ratio &&
|
||||
|
|
|
@ -1040,7 +1040,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
|
|||
* for atomic.
|
||||
*/
|
||||
return crtc->active && crtc->base.primary->state->fb &&
|
||||
crtc->config->base.adjusted_mode.crtc_clock;
|
||||
crtc->config->hw.adjusted_mode.crtc_clock;
|
||||
}
|
||||
|
||||
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
|
||||
|
@ -5086,7 +5086,7 @@ static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
|
|||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
int clock = crtc_state->base.adjusted_mode.crtc_clock;
|
||||
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
|
||||
u32 divsel, phaseinc, auxdiv, phasedir = 0;
|
||||
u32 temp;
|
||||
|
||||
|
@ -5359,7 +5359,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
|
|||
if (HAS_PCH_CPT(dev_priv) &&
|
||||
intel_crtc_has_dp_encoder(crtc_state)) {
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
|
||||
i915_reg_t reg = TRANS_DP_CTL(pipe);
|
||||
enum port port;
|
||||
|
@ -5509,7 +5509,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
|
|||
to_intel_crtc(crtc_state->base.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
/*
|
||||
* Src coordinates are already rotated by 270 degrees for
|
||||
|
@ -5525,7 +5525,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
|
|||
* Once NV12 is enabled, handle it here while allocating scaler
|
||||
* for NV12.
|
||||
*/
|
||||
if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
|
||||
if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
|
||||
need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
||||
DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
|
||||
return -EINVAL;
|
||||
|
@ -5597,13 +5597,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
|
|||
*/
|
||||
int skl_update_scaler_crtc(struct intel_crtc_state *state)
|
||||
{
|
||||
const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
|
||||
bool need_scaler = false;
|
||||
|
||||
if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
|
||||
need_scaler = true;
|
||||
|
||||
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
|
||||
return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
|
||||
&state->scaler_state.scaler_id,
|
||||
state->pipe_src_w, state->pipe_src_h,
|
||||
adjusted_mode->crtc_hdisplay,
|
||||
|
@ -5958,7 +5958,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
|
|||
* forcibly enable IPS on the first fastset.
|
||||
*/
|
||||
if (new_crtc_state->update_pipe &&
|
||||
old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
|
||||
old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
|
||||
return true;
|
||||
|
||||
return !old_crtc_state->ips_enabled;
|
||||
|
@ -6002,7 +6002,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
|
|||
|
||||
intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
|
||||
|
||||
if (pipe_config->update_wm_post && pipe_config->base.active)
|
||||
if (pipe_config->update_wm_post && pipe_config->hw.active)
|
||||
intel_update_watermarks(crtc);
|
||||
|
||||
if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
|
||||
|
@ -6080,7 +6080,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
|
|||
* event which is after the vblank start event, so we need to have a
|
||||
* wait-for-vblank between disabling the plane and the pipe.
|
||||
*/
|
||||
if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
|
||||
if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
|
||||
pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
|
||||
|
@ -6092,7 +6092,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
|
|||
* WaCxSRDisabledForSpriteScaling:ivb
|
||||
*/
|
||||
if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
|
||||
old_crtc_state->base.active)
|
||||
old_crtc_state->hw.active)
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
|
||||
/*
|
||||
|
@ -6896,7 +6896,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
|
|||
u64 mask;
|
||||
enum transcoder transcoder = crtc_state->cpu_transcoder;
|
||||
|
||||
if (!crtc_state->base.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return 0;
|
||||
|
||||
mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
|
||||
|
@ -7253,8 +7253,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
|
|||
if (!crtc_state)
|
||||
return;
|
||||
|
||||
I915_STATE_WARN(!crtc_state->base.active,
|
||||
"connector is active, but attached crtc isn't\n");
|
||||
I915_STATE_WARN(!crtc_state->hw.active,
|
||||
"connector is active, but attached crtc isn't\n");
|
||||
|
||||
if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
|
||||
return;
|
||||
|
@ -7265,8 +7265,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
|
|||
I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
|
||||
"attached encoder crtc differs from connector crtc\n");
|
||||
} else {
|
||||
I915_STATE_WARN(crtc_state && crtc_state->base.active,
|
||||
"attached crtc is active, but connector isn't\n");
|
||||
I915_STATE_WARN(crtc_state && crtc_state->hw.active,
|
||||
"attached crtc is active, but connector isn't\n");
|
||||
I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
|
||||
"best encoder set without crtc!\n");
|
||||
}
|
||||
|
@ -7274,7 +7274,7 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
|
|||
|
||||
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (crtc_state->base.enable && crtc_state->has_pch_encoder)
|
||||
if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
|
||||
return crtc_state->fdi_lanes;
|
||||
|
||||
return 0;
|
||||
|
@ -7357,7 +7357,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
|
|||
struct intel_crtc_state *pipe_config)
|
||||
{
|
||||
struct drm_device *dev = intel_crtc->base.dev;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
int lane, link_bw, fdi_dotclock, ret;
|
||||
bool needs_recompute = false;
|
||||
|
||||
|
@ -7474,7 +7474,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
|
|||
{
|
||||
u32 pixel_rate;
|
||||
|
||||
pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
|
||||
pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
|
||||
|
||||
/*
|
||||
* We only use IF-ID interlacing. If we ever use
|
||||
|
@ -7512,7 +7512,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
|
|||
if (HAS_GMCH(dev_priv))
|
||||
/* FIXME calculate proper pipe pixel rate for GMCH pfit */
|
||||
crtc_state->pixel_rate =
|
||||
crtc_state->base.adjusted_mode.crtc_clock;
|
||||
crtc_state->hw.adjusted_mode.crtc_clock;
|
||||
else
|
||||
crtc_state->pixel_rate =
|
||||
ilk_pipe_pixel_rate(crtc_state);
|
||||
|
@ -7522,7 +7522,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
|
|||
struct intel_crtc_state *pipe_config)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
int clock_limit = dev_priv->max_dotclk_freq;
|
||||
|
||||
if (INTEL_GEN(dev_priv) < 4) {
|
||||
|
@ -7548,7 +7548,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
|
|||
|
||||
if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
|
||||
pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
|
||||
pipe_config->base.ctm) {
|
||||
pipe_config->hw.ctm) {
|
||||
/*
|
||||
* There is only one pipe CSC unit per pipe, and we need that
|
||||
* for output conversion from RGB->YCBCR. So if CTM is already
|
||||
|
@ -8246,7 +8246,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
|
|||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
|
||||
u32 crtc_vtotal, crtc_vblank_end;
|
||||
int vsyncshift = 0;
|
||||
|
||||
|
@ -8340,39 +8340,39 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
|
|||
u32 tmp;
|
||||
|
||||
tmp = I915_READ(HTOTAL(cpu_transcoder));
|
||||
pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
|
||||
pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
|
||||
|
||||
if (!transcoder_is_dsi(cpu_transcoder)) {
|
||||
tmp = I915_READ(HBLANK(cpu_transcoder));
|
||||
pipe_config->base.adjusted_mode.crtc_hblank_start =
|
||||
pipe_config->hw.adjusted_mode.crtc_hblank_start =
|
||||
(tmp & 0xffff) + 1;
|
||||
pipe_config->base.adjusted_mode.crtc_hblank_end =
|
||||
pipe_config->hw.adjusted_mode.crtc_hblank_end =
|
||||
((tmp >> 16) & 0xffff) + 1;
|
||||
}
|
||||
tmp = I915_READ(HSYNC(cpu_transcoder));
|
||||
pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
|
||||
pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
|
||||
|
||||
tmp = I915_READ(VTOTAL(cpu_transcoder));
|
||||
pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
|
||||
pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
|
||||
|
||||
if (!transcoder_is_dsi(cpu_transcoder)) {
|
||||
tmp = I915_READ(VBLANK(cpu_transcoder));
|
||||
pipe_config->base.adjusted_mode.crtc_vblank_start =
|
||||
pipe_config->hw.adjusted_mode.crtc_vblank_start =
|
||||
(tmp & 0xffff) + 1;
|
||||
pipe_config->base.adjusted_mode.crtc_vblank_end =
|
||||
pipe_config->hw.adjusted_mode.crtc_vblank_end =
|
||||
((tmp >> 16) & 0xffff) + 1;
|
||||
}
|
||||
tmp = I915_READ(VSYNC(cpu_transcoder));
|
||||
pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
|
||||
pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
|
||||
|
||||
if (intel_pipe_is_interlaced(pipe_config)) {
|
||||
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
|
||||
pipe_config->base.adjusted_mode.crtc_vtotal += 1;
|
||||
pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
|
||||
pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
|
||||
pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
|
||||
pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -8387,27 +8387,27 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
|
|||
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
|
||||
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
|
||||
|
||||
pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
|
||||
pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
|
||||
pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
|
||||
pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
|
||||
}
|
||||
|
||||
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
||||
struct intel_crtc_state *pipe_config)
|
||||
{
|
||||
mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
|
||||
mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
|
||||
mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
|
||||
mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
|
||||
mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
|
||||
mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
|
||||
mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
|
||||
mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
|
||||
|
||||
mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
|
||||
mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
|
||||
mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
|
||||
mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
|
||||
mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
|
||||
mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
|
||||
mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
|
||||
mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
|
||||
|
||||
mode->flags = pipe_config->base.adjusted_mode.flags;
|
||||
mode->flags = pipe_config->hw.adjusted_mode.flags;
|
||||
mode->type = DRM_MODE_TYPE_DRIVER;
|
||||
|
||||
mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
|
||||
mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
|
||||
|
||||
mode->hsync = drm_mode_hsync(mode);
|
||||
mode->vrefresh = drm_mode_vrefresh(mode);
|
||||
|
@ -8453,7 +8453,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
|
|||
}
|
||||
}
|
||||
|
||||
if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
||||
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
||||
if (INTEL_GEN(dev_priv) < 4 ||
|
||||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
|
||||
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
|
||||
|
@ -8986,7 +8986,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
|
|||
* but in case the pipe is enabled w/o any ports we need a sane
|
||||
* default.
|
||||
*/
|
||||
pipe_config->base.adjusted_mode.crtc_clock =
|
||||
pipe_config->hw.adjusted_mode.crtc_clock =
|
||||
pipe_config->port_clock / pipe_config->pixel_multiplier;
|
||||
|
||||
ret = true;
|
||||
|
@ -9530,7 +9530,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
|
|||
if (crtc_state->dither)
|
||||
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
|
||||
|
||||
if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
val |= PIPECONF_INTERLACED_ILK;
|
||||
else
|
||||
val |= PIPECONF_PROGRESSIVE;
|
||||
|
@ -9564,7 +9564,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
|
|||
if (IS_HASWELL(dev_priv) && crtc_state->dither)
|
||||
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
|
||||
|
||||
if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
val |= PIPECONF_INTERLACED_ILK;
|
||||
else
|
||||
val |= PIPECONF_PROGRESSIVE;
|
||||
|
@ -11643,7 +11643,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
|
|||
* we may need some idea for the dotclock anyway.
|
||||
* Calculate one based on the FDI configuration.
|
||||
*/
|
||||
pipe_config->base.adjusted_mode.crtc_clock =
|
||||
pipe_config->hw.adjusted_mode.crtc_clock =
|
||||
intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
|
||||
&pipe_config->fdi_m_n);
|
||||
}
|
||||
|
@ -11748,8 +11748,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
|
|||
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
bool mode_changed = needs_modeset(crtc_state);
|
||||
bool was_crtc_enabled = old_crtc_state->base.active;
|
||||
bool is_crtc_enabled = crtc_state->base.active;
|
||||
bool was_crtc_enabled = old_crtc_state->hw.active;
|
||||
bool is_crtc_enabled = crtc_state->hw.active;
|
||||
bool turn_off, turn_on, visible, was_visible;
|
||||
int ret;
|
||||
|
||||
|
@ -12026,8 +12026,8 @@ static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
|
|||
continue;
|
||||
if (!connector->has_tile)
|
||||
continue;
|
||||
if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
|
||||
crtc_state->base.mode.vdisplay != connector->tile_v_size)
|
||||
if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
|
||||
crtc_state->hw.mode.vdisplay != connector->tile_v_size)
|
||||
return 0;
|
||||
if (connector->tile_h_loc == connector->num_h_tile - 1 &&
|
||||
connector->tile_v_loc == connector->num_v_tile - 1)
|
||||
|
@ -12093,10 +12093,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
|
|||
int ret;
|
||||
|
||||
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
|
||||
mode_changed && !crtc_state->base.active)
|
||||
mode_changed && !crtc_state->hw.active)
|
||||
crtc_state->update_wm_post = true;
|
||||
|
||||
if (mode_changed && crtc_state->base.enable &&
|
||||
if (mode_changed && crtc_state->hw.enable &&
|
||||
dev_priv->display.crtc_compute_clock &&
|
||||
!WARN_ON(crtc_state->shared_dpll)) {
|
||||
ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
|
||||
|
@ -12387,14 +12387,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
|
|||
|
||||
DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
|
||||
crtc->base.base.id, crtc->base.name,
|
||||
yesno(pipe_config->base.enable), context);
|
||||
yesno(pipe_config->hw.enable), context);
|
||||
|
||||
if (!pipe_config->base.enable)
|
||||
if (!pipe_config->hw.enable)
|
||||
goto dump_planes;
|
||||
|
||||
snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
|
||||
DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
|
||||
yesno(pipe_config->base.active),
|
||||
yesno(pipe_config->hw.active),
|
||||
buf, pipe_config->output_types,
|
||||
output_formats(pipe_config->output_format));
|
||||
|
||||
|
@ -12434,10 +12434,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
|
|||
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
|
||||
|
||||
DRM_DEBUG_KMS("requested mode:\n");
|
||||
drm_mode_debug_printmodeline(&pipe_config->base.mode);
|
||||
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
|
||||
DRM_DEBUG_KMS("adjusted mode:\n");
|
||||
drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
|
||||
intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
|
||||
drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
|
||||
intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
|
||||
DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
|
||||
pipe_config->port_clock,
|
||||
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
|
||||
|
@ -12625,13 +12625,13 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
|
|||
* positive or negative polarity is requested, treat this as meaning
|
||||
* negative polarity.
|
||||
*/
|
||||
if (!(pipe_config->base.adjusted_mode.flags &
|
||||
if (!(pipe_config->hw.adjusted_mode.flags &
|
||||
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
|
||||
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
|
||||
pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
|
||||
|
||||
if (!(pipe_config->base.adjusted_mode.flags &
|
||||
if (!(pipe_config->hw.adjusted_mode.flags &
|
||||
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
|
||||
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
|
||||
pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
|
||||
|
||||
ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
|
||||
pipe_config);
|
||||
|
@ -12648,7 +12648,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
|
|||
* computation to clearly distinguish it from the adjusted mode, which
|
||||
* can be changed by the connectors in the below retry loop.
|
||||
*/
|
||||
drm_mode_get_hv_timing(&pipe_config->base.mode,
|
||||
drm_mode_get_hv_timing(&pipe_config->hw.mode,
|
||||
&pipe_config->pipe_src_w,
|
||||
&pipe_config->pipe_src_h);
|
||||
|
||||
|
@ -12681,7 +12681,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
|
|||
pipe_config->pixel_multiplier = 1;
|
||||
|
||||
/* Fill in default crtc timings, allow encoders to overwrite them. */
|
||||
drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
|
||||
drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
|
||||
CRTC_STEREO_DOUBLE);
|
||||
|
||||
/* Set the crtc_state defaults for trans_port_sync */
|
||||
|
@ -12715,7 +12715,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
|
|||
/* Set default port clock if not overwritten by the encoder. Needs to be
|
||||
* done afterwards in case the encoder adjusts the mode. */
|
||||
if (!pipe_config->port_clock)
|
||||
pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
|
||||
pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
|
||||
* pipe_config->pixel_multiplier;
|
||||
|
||||
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
|
||||
|
@ -12887,8 +12887,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
|||
bool ret = true;
|
||||
u32 bp_gamma = 0;
|
||||
bool fixup_inherited = fastset &&
|
||||
(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
|
||||
!(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
|
||||
(current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
|
||||
!(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
|
||||
|
||||
if (fixup_inherited && !fastboot_enabled(dev_priv)) {
|
||||
DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
|
||||
|
@ -13234,7 +13234,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
|
|||
if (pipe_config->has_pch_encoder) {
|
||||
int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
|
||||
&pipe_config->fdi_m_n);
|
||||
int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
|
||||
int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
|
||||
|
||||
/*
|
||||
* FDI already provided one idea for the dotclock.
|
||||
|
@ -13262,7 +13262,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
|
|||
const enum pipe pipe = crtc->pipe;
|
||||
int plane, level, max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
|
||||
if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
|
||||
return;
|
||||
|
||||
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
|
||||
|
@ -13484,23 +13484,26 @@ verify_crtc_state(struct intel_crtc *crtc,
|
|||
|
||||
/* we keep both pipes enabled on 830 */
|
||||
if (IS_I830(dev_priv))
|
||||
active = new_crtc_state->base.active;
|
||||
active = new_crtc_state->hw.active;
|
||||
|
||||
I915_STATE_WARN(new_crtc_state->base.active != active,
|
||||
"crtc active state doesn't match with hw state "
|
||||
"(expected %i, found %i)\n", new_crtc_state->base.active, active);
|
||||
I915_STATE_WARN(new_crtc_state->hw.active != active,
|
||||
"crtc active state doesn't match with hw state "
|
||||
"(expected %i, found %i)\n",
|
||||
new_crtc_state->hw.active, active);
|
||||
|
||||
I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
|
||||
"transitional active state does not match atomic hw state "
|
||||
"(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
|
||||
I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
|
||||
"transitional active state does not match atomic hw state "
|
||||
"(expected %i, found %i)\n",
|
||||
new_crtc_state->hw.active, crtc->active);
|
||||
|
||||
for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
|
||||
enum pipe pipe;
|
||||
|
||||
active = encoder->get_hw_state(encoder, &pipe);
|
||||
I915_STATE_WARN(active != new_crtc_state->base.active,
|
||||
"[ENCODER:%i] active %i with crtc active %i\n",
|
||||
encoder->base.base.id, active, new_crtc_state->base.active);
|
||||
I915_STATE_WARN(active != new_crtc_state->hw.active,
|
||||
"[ENCODER:%i] active %i with crtc active %i\n",
|
||||
encoder->base.base.id, active,
|
||||
new_crtc_state->hw.active);
|
||||
|
||||
I915_STATE_WARN(active && crtc->pipe != pipe,
|
||||
"Encoder connected to wrong pipe %c\n",
|
||||
|
@ -13512,7 +13515,7 @@ verify_crtc_state(struct intel_crtc *crtc,
|
|||
|
||||
intel_crtc_compute_pixel_rate(pipe_config);
|
||||
|
||||
if (!new_crtc_state->base.active)
|
||||
if (!new_crtc_state->hw.active)
|
||||
return;
|
||||
|
||||
intel_pipe_config_sanity_check(dev_priv, pipe_config);
|
||||
|
@ -13574,7 +13577,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
|
|||
|
||||
crtc_mask = drm_crtc_mask(&crtc->base);
|
||||
|
||||
if (new_crtc_state->base.active)
|
||||
if (new_crtc_state->hw.active)
|
||||
I915_STATE_WARN(!(pll->active_mask & crtc_mask),
|
||||
"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
|
||||
pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
|
||||
|
@ -13656,7 +13659,7 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
|
|||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
|
||||
|
||||
|
@ -13738,7 +13741,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
|
|||
|
||||
/* look at all crtc's that are going to be enabled in during modeset */
|
||||
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
if (!crtc_state->base.active ||
|
||||
if (!crtc_state->hw.active ||
|
||||
!needs_modeset(crtc_state))
|
||||
continue;
|
||||
|
||||
|
@ -13763,7 +13766,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
|
|||
|
||||
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
|
||||
|
||||
if (!crtc_state->base.active ||
|
||||
if (!crtc_state->hw.active ||
|
||||
needs_modeset(crtc_state))
|
||||
continue;
|
||||
|
||||
|
@ -13800,12 +13803,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
|
|||
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
|
||||
new_crtc_state, i) {
|
||||
if (new_crtc_state->base.active)
|
||||
if (new_crtc_state->hw.active)
|
||||
state->active_pipes |= BIT(crtc->pipe);
|
||||
else
|
||||
state->active_pipes &= ~BIT(crtc->pipe);
|
||||
|
||||
if (old_crtc_state->base.active != new_crtc_state->base.active)
|
||||
if (old_crtc_state->hw.active != new_crtc_state->hw.active)
|
||||
state->active_pipe_changes |= BIT(crtc->pipe);
|
||||
}
|
||||
|
||||
|
@ -13993,8 +13996,8 @@ static int intel_atomic_check(struct drm_device *dev,
|
|||
/* Catch I915_MODE_FLAG_INHERITED */
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
|
||||
new_crtc_state, i) {
|
||||
if (new_crtc_state->base.mode.private_flags !=
|
||||
old_crtc_state->base.mode.private_flags)
|
||||
if (new_crtc_state->hw.mode.private_flags !=
|
||||
old_crtc_state->hw.mode.private_flags)
|
||||
new_crtc_state->base.mode_changed = true;
|
||||
}
|
||||
|
||||
|
@ -14233,7 +14236,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
|
|||
* of enabling them on the CRTC's first fastset.
|
||||
*/
|
||||
if (new_crtc_state->update_pipe && !modeset &&
|
||||
old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
|
||||
old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
|
||||
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
|
||||
}
|
||||
|
||||
|
@ -14277,7 +14280,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
|
|||
intel_check_pch_fifo_underruns(dev_priv);
|
||||
|
||||
/* FIXME unify this for all platforms */
|
||||
if (!new_crtc_state->base.active &&
|
||||
if (!new_crtc_state->hw.active &&
|
||||
!HAS_GMCH(dev_priv) &&
|
||||
dev_priv->display.initial_watermarks)
|
||||
dev_priv->display.initial_watermarks(state,
|
||||
|
@ -14300,7 +14303,7 @@ static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
|
|||
|
||||
/* Disable Slave first */
|
||||
intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
|
||||
if (old_slave_crtc_state->base.active)
|
||||
if (old_slave_crtc_state->hw.active)
|
||||
intel_old_crtc_state_disables(state,
|
||||
old_slave_crtc_state,
|
||||
new_slave_crtc_state,
|
||||
|
@ -14308,7 +14311,7 @@ static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *st
|
|||
|
||||
/* Disable Master */
|
||||
intel_pre_plane_update(old_crtc_state, new_crtc_state);
|
||||
if (old_crtc_state->base.active)
|
||||
if (old_crtc_state->hw.active)
|
||||
intel_old_crtc_state_disables(state,
|
||||
old_crtc_state,
|
||||
new_crtc_state,
|
||||
|
@ -14349,7 +14352,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
|
|||
} else {
|
||||
intel_pre_plane_update(old_crtc_state, new_crtc_state);
|
||||
|
||||
if (old_crtc_state->base.active)
|
||||
if (old_crtc_state->hw.active)
|
||||
intel_old_crtc_state_disables(state,
|
||||
old_crtc_state,
|
||||
new_crtc_state,
|
||||
|
@ -14365,7 +14368,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
|
|||
int i;
|
||||
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
|
||||
if (!new_crtc_state->base.active)
|
||||
if (!new_crtc_state->hw.active)
|
||||
continue;
|
||||
|
||||
intel_update_crtc(crtc, state, old_crtc_state,
|
||||
|
@ -14430,7 +14433,7 @@ static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
|
|||
* of enabling them on the CRTC's first fastset.
|
||||
*/
|
||||
if (new_crtc_state->update_pipe && !modeset &&
|
||||
old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
|
||||
old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
|
||||
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
|
||||
}
|
||||
|
||||
|
@ -14494,7 +14497,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
|
|||
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
|
||||
/* ignore allocations for crtc's that have been turned off. */
|
||||
if (new_crtc_state->base.active)
|
||||
if (new_crtc_state->hw.active)
|
||||
entries[i] = old_crtc_state->wm.skl.ddb;
|
||||
|
||||
/* If 2nd DBuf slice required, enable it here */
|
||||
|
@ -14515,7 +14518,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
|
|||
bool vbl_wait = false;
|
||||
bool modeset = needs_modeset(new_crtc_state);
|
||||
|
||||
if (updated & BIT(crtc->pipe) || !new_crtc_state->base.active)
|
||||
if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
|
||||
continue;
|
||||
|
||||
if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
|
||||
|
@ -14677,7 +14680,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
|
|||
bool modeset = needs_modeset(new_crtc_state);
|
||||
|
||||
/* Complete events for now disable pipes here. */
|
||||
if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
|
||||
if (modeset && !new_crtc_state->hw.active && new_crtc_state->base.event) {
|
||||
spin_lock_irq(&dev->event_lock);
|
||||
drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
|
||||
spin_unlock_irq(&dev->event_lock);
|
||||
|
@ -14713,7 +14716,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
|
|||
drm_atomic_helper_wait_for_flip_done(dev, &state->base);
|
||||
|
||||
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
|
||||
if (new_crtc_state->base.active &&
|
||||
if (new_crtc_state->hw.active &&
|
||||
!needs_modeset(new_crtc_state) &&
|
||||
(new_crtc_state->base.color_mgmt_changed ||
|
||||
new_crtc_state->update_pipe))
|
||||
|
@ -15280,7 +15283,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
|
|||
* When crtc is inactive or there is a modeset pending,
|
||||
* wait for it to complete in the slowpath
|
||||
*/
|
||||
if (!crtc_state->base.active || needs_modeset(crtc_state) ||
|
||||
if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
|
||||
crtc_state->update_pipe)
|
||||
goto slow;
|
||||
|
||||
|
@ -16737,7 +16740,7 @@ static int intel_initial_commit(struct drm_device *dev)
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (crtc_state->base.active) {
|
||||
if (crtc_state->hw.active) {
|
||||
ret = drm_atomic_add_affected_planes(state, &crtc->base);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
@ -17087,7 +17090,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
|
|||
I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
|
||||
}
|
||||
|
||||
if (crtc_state->base.active) {
|
||||
if (crtc_state->hw.active) {
|
||||
struct intel_plane *plane;
|
||||
|
||||
/* Disable everything but the primary plane */
|
||||
|
@ -17112,10 +17115,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
|
|||
|
||||
/* Adjust the state of the output pipe according to whether we
|
||||
* have active connectors/encoders. */
|
||||
if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
|
||||
if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
|
||||
intel_crtc_disable_noatomic(&crtc->base, ctx);
|
||||
|
||||
if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
|
||||
if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
|
||||
/*
|
||||
* We start out with underrun reporting disabled to avoid races.
|
||||
* For correct bookkeeping mark this on active crtcs.
|
||||
|
@ -17159,7 +17162,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
|
|||
* road.
|
||||
*/
|
||||
return IS_GEN(dev_priv, 6) &&
|
||||
crtc_state->base.active &&
|
||||
crtc_state->hw.active &&
|
||||
crtc_state->shared_dpll &&
|
||||
crtc_state->port_clock == 0;
|
||||
}
|
||||
|
@ -17176,7 +17179,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
|
|||
* encoder is active and trying to read from a pipe) and the
|
||||
* pipe itself being active. */
|
||||
bool has_active_crtc = crtc_state &&
|
||||
crtc_state->base.active;
|
||||
crtc_state->hw.active;
|
||||
|
||||
if (crtc_state && has_bogus_dpll_config(crtc_state)) {
|
||||
DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
|
||||
|
@ -17284,18 +17287,18 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
memset(crtc_state, 0, sizeof(*crtc_state));
|
||||
__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
|
||||
|
||||
crtc_state->base.active = crtc_state->base.enable =
|
||||
crtc_state->hw.active = crtc_state->hw.enable =
|
||||
dev_priv->display.get_pipe_config(crtc, crtc_state);
|
||||
|
||||
crtc->base.enabled = crtc_state->base.enable;
|
||||
crtc->active = crtc_state->base.active;
|
||||
crtc->base.enabled = crtc_state->hw.enable;
|
||||
crtc->active = crtc_state->hw.active;
|
||||
|
||||
if (crtc_state->base.active)
|
||||
if (crtc_state->hw.active)
|
||||
dev_priv->active_pipes |= BIT(crtc->pipe);
|
||||
|
||||
DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
|
||||
crtc->base.base.id, crtc->base.name,
|
||||
enableddisabled(crtc_state->base.active));
|
||||
enableddisabled(crtc_state->hw.active));
|
||||
}
|
||||
|
||||
readout_plane_state(dev_priv);
|
||||
|
@ -17317,7 +17320,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
struct intel_crtc_state *crtc_state =
|
||||
to_intel_crtc_state(crtc->base.state);
|
||||
|
||||
if (crtc_state->base.active &&
|
||||
if (crtc_state->hw.active &&
|
||||
crtc_state->shared_dpll == pll)
|
||||
pll->state.crtc_mask |= 1 << crtc->pipe;
|
||||
}
|
||||
|
@ -17362,7 +17365,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
crtc = to_intel_crtc(encoder->base.crtc);
|
||||
crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
|
||||
|
||||
if (crtc_state && crtc_state->base.active) {
|
||||
if (crtc_state && crtc_state->hw.active) {
|
||||
/*
|
||||
* This has to be done during hardware readout
|
||||
* because anything calling .crtc_disable may
|
||||
|
@ -17391,13 +17394,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
struct intel_plane *plane;
|
||||
int min_cdclk = 0;
|
||||
|
||||
if (crtc_state->base.active) {
|
||||
if (crtc_state->hw.active) {
|
||||
struct drm_display_mode mode;
|
||||
|
||||
intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode,
|
||||
intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
|
||||
crtc_state);
|
||||
|
||||
mode = crtc_state->base.adjusted_mode;
|
||||
mode = crtc_state->hw.adjusted_mode;
|
||||
mode.hdisplay = crtc_state->pipe_src_w;
|
||||
mode.vdisplay = crtc_state->pipe_src_h;
|
||||
WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->base, &mode));
|
||||
|
@ -17411,7 +17414,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
* set a flag to indicate that a full recalculation is
|
||||
* needed on the next commit.
|
||||
*/
|
||||
crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
|
||||
crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
|
||||
|
||||
intel_crtc_compute_pixel_rate(crtc_state);
|
||||
|
||||
|
@ -17447,7 +17450,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
crtc_state->min_cdclk[plane->id]);
|
||||
}
|
||||
|
||||
if (crtc_state->base.active) {
|
||||
if (crtc_state->hw.active) {
|
||||
min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
|
||||
if (WARN_ON(min_cdclk < 0))
|
||||
min_cdclk = 0;
|
||||
|
@ -17607,7 +17610,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
|
|||
|
||||
drm_crtc_vblank_reset(&crtc->base);
|
||||
|
||||
if (crtc_state->base.active)
|
||||
if (crtc_state->hw.active)
|
||||
intel_crtc_vblank_on(crtc_state);
|
||||
}
|
||||
|
||||
|
|
|
@ -1999,7 +1999,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
|
|||
struct intel_crtc_state *pipe_config,
|
||||
const struct link_config_limits *limits)
|
||||
{
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
int bpp, clock, lane_count;
|
||||
int mode_rate, link_clock, link_avail;
|
||||
|
||||
|
@ -2053,7 +2053,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
|
|||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
u8 dsc_max_bpc;
|
||||
int pipe_bpp;
|
||||
int ret;
|
||||
|
@ -2164,7 +2164,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
|
|||
struct intel_crtc_state *pipe_config,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||
struct link_config_limits limits;
|
||||
int common_len;
|
||||
|
@ -2252,7 +2252,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
|
|||
{
|
||||
const struct drm_display_info *info = &connector->display_info;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
||||
int ret;
|
||||
|
||||
|
@ -2281,7 +2281,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
|
|||
const struct intel_digital_connector_state *intel_conn_state =
|
||||
to_intel_digital_connector_state(conn_state);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
/*
|
||||
* Our YCbCr output is always limited range.
|
||||
|
@ -2314,7 +2314,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
|
|||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||
struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
|
||||
enum port port = encoder->port;
|
||||
|
@ -2437,7 +2437,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
|
|||
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
||||
enum port port = encoder->port;
|
||||
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
|
||||
intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
|
||||
pipe_config->lane_count,
|
||||
|
@ -3269,7 +3269,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
|
|||
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||
}
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= flags;
|
||||
pipe_config->hw.adjusted_mode.flags |= flags;
|
||||
|
||||
if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
|
||||
pipe_config->limited_color_range = true;
|
||||
|
@ -3286,7 +3286,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
|
|||
pipe_config->port_clock = 270000;
|
||||
}
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock =
|
||||
pipe_config->hw.adjusted_mode.crtc_clock =
|
||||
intel_dotclock_calculate(pipe_config->port_clock,
|
||||
&pipe_config->dp_m_n);
|
||||
|
||||
|
@ -5079,7 +5079,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
|
|||
|
||||
WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
|
||||
|
||||
if (!crtc_state->base.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return 0;
|
||||
|
||||
if (conn_state->commit &&
|
||||
|
@ -6947,7 +6947,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
|
|||
return;
|
||||
}
|
||||
|
||||
if (!crtc_state->base.active) {
|
||||
if (!crtc_state->hw.active) {
|
||||
DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -48,7 +48,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
|
|||
struct intel_connector *connector =
|
||||
to_intel_connector(conn_state->connector);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
void *port = connector->port;
|
||||
bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
|
||||
DP_DPCD_QUIRK_CONSTANT_N);
|
||||
|
@ -99,7 +99,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
|
|||
struct intel_digital_connector_state *intel_conn_state =
|
||||
to_intel_digital_connector_state(conn_state);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
void *port = connector->port;
|
||||
struct link_config_limits limits;
|
||||
int ret;
|
||||
|
@ -191,7 +191,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
|
|||
|
||||
if (!crtc_state ||
|
||||
!drm_atomic_crtc_needs_modeset(&crtc_state->base) ||
|
||||
crtc_state->base.enable)
|
||||
crtc_state->hw.enable)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -178,9 +178,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
|
|||
else
|
||||
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= flags;
|
||||
pipe_config->hw.adjusted_mode.flags |= flags;
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||
}
|
||||
|
||||
static void intel_disable_dvo(struct intel_encoder *encoder,
|
||||
|
@ -207,8 +207,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder,
|
|||
u32 temp = I915_READ(dvo_reg);
|
||||
|
||||
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
|
||||
&pipe_config->base.mode,
|
||||
&pipe_config->base.adjusted_mode);
|
||||
&pipe_config->hw.mode,
|
||||
&pipe_config->hw.adjusted_mode);
|
||||
|
||||
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
|
||||
I915_READ(dvo_reg);
|
||||
|
@ -253,7 +253,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
|
|||
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
|
||||
const struct drm_display_mode *fixed_mode =
|
||||
intel_dvo->attached_connector->panel.fixed_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
|
||||
/*
|
||||
* If we have timings from the BIOS for the panel, put them in
|
||||
|
@ -278,7 +278,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
u32 dvo_val;
|
||||
|
|
|
@ -667,7 +667,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
|
|||
cache->vma = NULL;
|
||||
cache->flags = 0;
|
||||
|
||||
cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
|
||||
cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
|
||||
|
||||
|
|
|
@ -708,7 +708,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
|
|||
{
|
||||
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
struct drm_connector *connector = conn_state->connector;
|
||||
int ret;
|
||||
|
||||
|
@ -804,7 +804,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
|
|||
|
||||
ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
|
||||
conn_state->connector,
|
||||
&crtc_state->base.adjusted_mode);
|
||||
&crtc_state->hw.adjusted_mode);
|
||||
if (WARN_ON(ret))
|
||||
return false;
|
||||
|
||||
|
@ -1027,7 +1027,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
|
|||
|
||||
/* Enable default_phase whenever the display mode is suitably aligned */
|
||||
if (gcp_default_phase_possible(crtc_state->pipe_bpp,
|
||||
&crtc_state->base.adjusted_mode))
|
||||
&crtc_state->hw.adjusted_mode))
|
||||
crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
|
||||
}
|
||||
|
||||
|
@ -1738,7 +1738,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
|
|||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
||||
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
|
||||
u32 hdmi_val;
|
||||
|
||||
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
|
||||
|
@ -1829,7 +1829,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
|
|||
tmp & HDMI_COLOR_RANGE_16_235)
|
||||
pipe_config->limited_color_range = true;
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= flags;
|
||||
pipe_config->hw.adjusted_mode.flags |= flags;
|
||||
|
||||
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
|
||||
dotclock = pipe_config->port_clock * 2 / 3;
|
||||
|
@ -1839,7 +1839,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
|
|||
if (pipe_config->pixel_multiplier)
|
||||
dotclock /= pipe_config->pixel_multiplier;
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
|
||||
|
||||
pipe_config->lane_count = 4;
|
||||
|
||||
|
@ -2215,7 +2215,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
|
|||
struct drm_connector_state *connector_state;
|
||||
struct drm_connector *connector;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
int i;
|
||||
|
||||
if (HAS_GMCH(dev_priv))
|
||||
|
@ -2336,7 +2336,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
|
|||
{
|
||||
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
int bpc, clock = adjusted_mode->crtc_clock;
|
||||
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
|
||||
|
@ -2378,7 +2378,7 @@ static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_s
|
|||
const struct intel_digital_connector_state *intel_conn_state =
|
||||
to_intel_digital_connector_state(conn_state);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
/*
|
||||
* Our YCbCr output is always limited range.
|
||||
|
@ -2406,7 +2406,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
|
|||
{
|
||||
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
struct drm_connector *connector = conn_state->connector;
|
||||
struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
|
||||
struct intel_digital_connector_state *intel_conn_state =
|
||||
|
|
|
@ -189,7 +189,7 @@ void lspcon_ycbcr420_config(struct drm_connector *connector,
|
|||
{
|
||||
const struct drm_display_info *info = &connector->display_info;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
if (drm_mode_is_420_only(info, adjusted_mode) &&
|
||||
connector->ycbcr_420_allowed) {
|
||||
|
@ -475,7 +475,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
|
|||
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
|
||||
struct intel_lspcon *lspcon = &dig_port->lspcon;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
if (!lspcon->active) {
|
||||
DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
|
||||
|
|
|
@ -135,7 +135,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
|
|||
else
|
||||
flags |= DRM_MODE_FLAG_PVSYNC;
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= flags;
|
||||
pipe_config->hw.adjusted_mode.flags |= flags;
|
||||
|
||||
if (INTEL_GEN(dev_priv) < 5)
|
||||
pipe_config->gmch_pfit.lvds_border_bits =
|
||||
|
@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
|
|||
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
|
||||
}
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
|
||||
}
|
||||
|
||||
static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
|
@ -231,7 +231,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
|
|||
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
enum pipe pipe = crtc->pipe;
|
||||
u32 temp;
|
||||
|
||||
|
@ -392,7 +392,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
|
|||
to_lvds_encoder(&intel_encoder->base);
|
||||
struct intel_connector *intel_connector =
|
||||
lvds_encoder->attached_connector;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
unsigned int lvds_bpp;
|
||||
|
||||
|
|
|
@ -178,7 +178,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
|
|||
struct intel_crtc_state *pipe_config,
|
||||
int fitting_mode)
|
||||
{
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
int x = 0, y = 0, width = 0, height = 0;
|
||||
|
||||
/* Native modes don't need fitting */
|
||||
|
@ -300,7 +300,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
|
|||
static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
|
||||
u32 *pfit_control)
|
||||
{
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
u32 scaled_width = adjusted_mode->crtc_hdisplay *
|
||||
pipe_config->pipe_src_h;
|
||||
u32 scaled_height = pipe_config->pipe_src_w *
|
||||
|
@ -321,7 +321,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
|
|||
u32 *pfit_control, u32 *pfit_pgm_ratios,
|
||||
u32 *border)
|
||||
{
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
u32 scaled_width = adjusted_mode->crtc_hdisplay *
|
||||
pipe_config->pipe_src_h;
|
||||
u32 scaled_height = pipe_config->pipe_src_w *
|
||||
|
@ -380,7 +380,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
|
||||
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
|
||||
/* Native modes don't need fitting */
|
||||
if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
|
||||
|
|
|
@ -313,7 +313,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
|
|||
pipe_config->crc_enabled = enable;
|
||||
|
||||
if (IS_HASWELL(dev_priv) &&
|
||||
pipe_config->base.active && crtc->pipe == PIPE_A &&
|
||||
pipe_config->hw.active && crtc->pipe == PIPE_A &&
|
||||
pipe_config->cpu_transcoder == TRANSCODER_EDP)
|
||||
pipe_config->base.mode_changed = true;
|
||||
|
||||
|
|
|
@ -537,11 +537,11 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
|
|||
|
||||
static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
|
||||
{
|
||||
if (!cstate || !cstate->base.active)
|
||||
if (!cstate || !cstate->hw.active)
|
||||
return 0;
|
||||
|
||||
return DIV_ROUND_UP(1000 * 1000,
|
||||
drm_mode_vrefresh(&cstate->base.adjusted_mode));
|
||||
drm_mode_vrefresh(&cstate->hw.adjusted_mode));
|
||||
}
|
||||
|
||||
static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
|
||||
|
@ -606,8 +606,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
|
|||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
|
||||
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
|
||||
int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
|
||||
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
|
||||
int psr_max_h = 0, psr_max_v = 0;
|
||||
|
||||
if (!dev_priv->psr.sink_psr2_support)
|
||||
|
@ -673,7 +673,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
|
|||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
int psr_setup_time;
|
||||
|
||||
if (!CAN_PSR(dev_priv))
|
||||
|
@ -1117,7 +1117,7 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
|
|||
goto error;
|
||||
}
|
||||
|
||||
if (crtc_state->base.active && crtc_state->has_psr) {
|
||||
if (crtc_state->hw.active && crtc_state->has_psr) {
|
||||
/* Mark mode as changed to trigger a pipe->update() */
|
||||
crtc_state->base.mode_changed = true;
|
||||
break;
|
||||
|
|
|
@ -1087,7 +1087,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
|
|||
{
|
||||
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
int ret;
|
||||
|
||||
if (!crtc_state->has_hdmi_sink)
|
||||
|
@ -1276,8 +1276,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
|
|||
to_intel_sdvo_connector_state(conn_state);
|
||||
struct intel_sdvo_connector *intel_sdvo_connector =
|
||||
to_intel_sdvo_connector(conn_state->connector);
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *mode = &pipe_config->base.mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
struct drm_display_mode *mode = &pipe_config->hw.mode;
|
||||
|
||||
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
|
||||
pipe_config->pipe_bpp = 8*3;
|
||||
|
@ -1430,12 +1430,12 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
|
||||
const struct intel_sdvo_connector_state *sdvo_state =
|
||||
to_intel_sdvo_connector_state(conn_state);
|
||||
const struct intel_sdvo_connector *intel_sdvo_connector =
|
||||
to_intel_sdvo_connector(conn_state->connector);
|
||||
const struct drm_display_mode *mode = &crtc_state->base.mode;
|
||||
const struct drm_display_mode *mode = &crtc_state->hw.mode;
|
||||
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
|
||||
u32 sdvox;
|
||||
struct intel_sdvo_in_out_map in_out;
|
||||
|
@ -1629,7 +1629,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
|
|||
flags |= DRM_MODE_FLAG_NVSYNC;
|
||||
}
|
||||
|
||||
pipe_config->base.adjusted_mode.flags |= flags;
|
||||
pipe_config->hw.adjusted_mode.flags |= flags;
|
||||
|
||||
/*
|
||||
* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
|
||||
|
@ -1649,7 +1649,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
|
|||
if (pipe_config->pixel_multiplier)
|
||||
dotclock /= pipe_config->pixel_multiplier;
|
||||
|
||||
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
|
||||
|
||||
/* Cross check the port pixel multiplier with the sdvo encoder state. */
|
||||
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
|
||||
|
@ -1701,7 +1701,7 @@ static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
|
|||
const struct drm_connector_state *conn_state)
|
||||
{
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
struct drm_connector *connector = conn_state->connector;
|
||||
u8 *eld = connector->eld;
|
||||
|
||||
|
|
|
@ -83,7 +83,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
|
|||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
|
||||
long timeout = msecs_to_jiffies_timeout(1);
|
||||
int scanline, min, max, vblank_start;
|
||||
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
|
||||
|
@ -1891,7 +1891,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
|
|||
const struct drm_rect *dst = &plane_state->base.dst;
|
||||
int src_x, src_w, src_h, crtc_w, crtc_h;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
unsigned int stride = plane_state->color_plane[0].stride;
|
||||
unsigned int cpp = fb->format->cpp[0];
|
||||
unsigned int width_bytes;
|
||||
|
@ -2105,8 +2105,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
|
|||
}
|
||||
|
||||
/* Y-tiling is not supported in IF-ID Interlace mode */
|
||||
if (crtc_state->base.enable &&
|
||||
crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
|
||||
if (crtc_state->hw.enable &&
|
||||
crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
|
||||
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
|
||||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
|
||||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
|
||||
|
|
|
@ -1085,7 +1085,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
struct drm_display_mode mode = {};
|
||||
u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
|
||||
struct tv_mode tv_mode = {};
|
||||
|
@ -1188,7 +1188,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
|
|||
to_intel_tv_connector_state(conn_state);
|
||||
const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
|
||||
struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
int hdisplay = adjusted_mode->crtc_hdisplay;
|
||||
int vdisplay = adjusted_mode->crtc_vdisplay;
|
||||
|
||||
|
|
|
@ -329,8 +329,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
|
|||
int column_index = 0;
|
||||
u8 line_buf_depth = 0;
|
||||
|
||||
vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
|
||||
vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
|
||||
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
|
||||
vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
|
||||
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
|
||||
pipe_config->dsc.slice_count);
|
||||
/*
|
||||
|
|
|
@ -263,7 +263,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
|
|||
struct intel_connector *intel_connector = intel_dsi->attached_connector;
|
||||
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
@ -1032,7 +1032,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
|
|||
struct drm_device *dev = encoder->base.dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct drm_display_mode *adjusted_mode =
|
||||
&pipe_config->base.adjusted_mode;
|
||||
&pipe_config->hw.adjusted_mode;
|
||||
struct drm_display_mode *adjusted_mode_sw;
|
||||
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
||||
|
@ -1045,7 +1045,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
|
|||
crtc_hblank_start_sw, crtc_hblank_end_sw;
|
||||
|
||||
/* FIXME: hw readout should not depend on SW state */
|
||||
adjusted_mode_sw = &crtc->config->base.adjusted_mode;
|
||||
adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
|
||||
|
||||
/*
|
||||
* Atleast one port is active as encoder->get_config called only if
|
||||
|
@ -1204,7 +1204,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
|
|||
}
|
||||
|
||||
if (pclk) {
|
||||
pipe_config->base.adjusted_mode.crtc_clock = pclk;
|
||||
pipe_config->hw.adjusted_mode.crtc_clock = pclk;
|
||||
pipe_config->port_clock = pclk;
|
||||
}
|
||||
}
|
||||
|
@ -1317,7 +1317,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
|
|||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
|
||||
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
||||
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
|
||||
enum port port;
|
||||
unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
|
||||
u32 val, tmp;
|
||||
|
|
|
@ -2684,11 +2684,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
|
|||
|
||||
seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
|
||||
crtc->base.base.id, pipe_name(crtc->pipe),
|
||||
yesno(pipe_config->base.active),
|
||||
yesno(pipe_config->hw.active),
|
||||
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
|
||||
yesno(pipe_config->dither), pipe_config->pipe_bpp);
|
||||
|
||||
if (pipe_config->base.active) {
|
||||
if (pipe_config->hw.active) {
|
||||
struct intel_plane *cursor =
|
||||
to_intel_plane(crtc->base.cursor);
|
||||
|
||||
|
@ -4161,7 +4161,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
|
|||
|
||||
crtc_state = to_intel_crtc_state(crtc->base.state);
|
||||
|
||||
if (!crtc_state->base.active ||
|
||||
if (!crtc_state->hw.active ||
|
||||
!crtc_state->has_drrs)
|
||||
goto out;
|
||||
|
||||
|
@ -4243,7 +4243,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
|
|||
ret = wait_for_completion_interruptible(&commit->flip_done);
|
||||
}
|
||||
|
||||
if (!ret && crtc_state->base.active) {
|
||||
if (!ret && crtc_state->hw.active) {
|
||||
DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
|
||||
pipe_name(intel_crtc->pipe));
|
||||
|
||||
|
|
|
@ -789,7 +789,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
|
|||
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
|
||||
|
||||
/* FIXME check the 'enable' instead */
|
||||
if (!crtc_state->base.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return false;
|
||||
|
||||
/*
|
||||
|
@ -842,7 +842,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
|
|||
crtc = single_enabled_crtc(dev_priv);
|
||||
if (crtc) {
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc->config->base.adjusted_mode;
|
||||
&crtc->config->hw.adjusted_mode;
|
||||
const struct drm_framebuffer *fb =
|
||||
crtc->base.primary->state->fb;
|
||||
int cpp = fb->format->cpp[0];
|
||||
|
@ -1078,7 +1078,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
|
|||
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
|
||||
unsigned int clock, htotal, cpp, width, wm;
|
||||
|
||||
|
@ -1390,7 +1390,7 @@ static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
|
|||
const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
|
||||
enum plane_id plane_id;
|
||||
|
||||
if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
|
||||
if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
|
||||
*intermediate = *optimal;
|
||||
|
||||
intermediate->cxsr = false;
|
||||
|
@ -1584,7 +1584,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
|
|||
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
unsigned int clock, htotal, cpp, width, wm;
|
||||
|
||||
if (dev_priv->wm.pri_latency[level] == 0)
|
||||
|
@ -2023,7 +2023,7 @@ static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
|
|||
const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
|
||||
int level;
|
||||
|
||||
if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
|
||||
if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
|
||||
*intermediate = *optimal;
|
||||
|
||||
intermediate->cxsr = false;
|
||||
|
@ -2179,7 +2179,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
|
|||
/* self-refresh has much higher latency */
|
||||
static const int sr_latency_ns = 12000;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc->config->base.adjusted_mode;
|
||||
&crtc->config->hw.adjusted_mode;
|
||||
const struct drm_framebuffer *fb =
|
||||
crtc->base.primary->state->fb;
|
||||
int clock = adjusted_mode->crtc_clock;
|
||||
|
@ -2260,7 +2260,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
|
|||
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
|
||||
if (intel_crtc_active(crtc)) {
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc->config->base.adjusted_mode;
|
||||
&crtc->config->hw.adjusted_mode;
|
||||
const struct drm_framebuffer *fb =
|
||||
crtc->base.primary->state->fb;
|
||||
int cpp;
|
||||
|
@ -2287,7 +2287,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
|
|||
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
|
||||
if (intel_crtc_active(crtc)) {
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc->config->base.adjusted_mode;
|
||||
&crtc->config->hw.adjusted_mode;
|
||||
const struct drm_framebuffer *fb =
|
||||
crtc->base.primary->state->fb;
|
||||
int cpp;
|
||||
|
@ -2335,7 +2335,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
|
|||
/* self-refresh has much higher latency */
|
||||
static const int sr_latency_ns = 6000;
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&enabled->config->base.adjusted_mode;
|
||||
&enabled->config->hw.adjusted_mode;
|
||||
const struct drm_framebuffer *fb =
|
||||
enabled->base.primary->state->fb;
|
||||
int clock = adjusted_mode->crtc_clock;
|
||||
|
@ -2393,7 +2393,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
|
|||
if (crtc == NULL)
|
||||
return;
|
||||
|
||||
adjusted_mode = &crtc->config->base.adjusted_mode;
|
||||
adjusted_mode = &crtc->config->hw.adjusted_mode;
|
||||
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
||||
&i845_wm_info,
|
||||
dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
|
||||
|
@ -2483,7 +2483,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
|
|||
return method1;
|
||||
|
||||
method2 = ilk_wm_method2(crtc_state->pixel_rate,
|
||||
crtc_state->base.adjusted_mode.crtc_htotal,
|
||||
crtc_state->hw.adjusted_mode.crtc_htotal,
|
||||
drm_rect_width(&plane_state->base.dst),
|
||||
cpp, mem_value);
|
||||
|
||||
|
@ -2511,7 +2511,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
|
|||
|
||||
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
|
||||
method2 = ilk_wm_method2(crtc_state->pixel_rate,
|
||||
crtc_state->base.adjusted_mode.crtc_htotal,
|
||||
crtc_state->hw.adjusted_mode.crtc_htotal,
|
||||
drm_rect_width(&plane_state->base.dst),
|
||||
cpp, mem_value);
|
||||
return min(method1, method2);
|
||||
|
@ -2536,7 +2536,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
|
|||
cpp = plane_state->base.fb->format->cpp[0];
|
||||
|
||||
return ilk_wm_method2(crtc_state->pixel_rate,
|
||||
crtc_state->base.adjusted_mode.crtc_htotal,
|
||||
crtc_state->hw.adjusted_mode.crtc_htotal,
|
||||
drm_rect_width(&plane_state->base.dst),
|
||||
cpp, mem_value);
|
||||
}
|
||||
|
@ -2760,10 +2760,10 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
|
|||
const struct intel_atomic_state *intel_state =
|
||||
to_intel_atomic_state(crtc_state->base.state);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
u32 linetime, ips_linetime;
|
||||
|
||||
if (!crtc_state->base.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return 0;
|
||||
if (WARN_ON(adjusted_mode->crtc_clock == 0))
|
||||
return 0;
|
||||
|
@ -3095,7 +3095,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
|
|||
curstate = plane_state;
|
||||
}
|
||||
|
||||
pipe_wm->pipe_enabled = crtc_state->base.active;
|
||||
pipe_wm->pipe_enabled = crtc_state->hw.active;
|
||||
if (sprstate) {
|
||||
pipe_wm->sprites_enabled = sprstate->base.visible;
|
||||
pipe_wm->sprites_scaled = sprstate->base.visible &&
|
||||
|
@ -3168,7 +3168,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
|
|||
* and after the vblank.
|
||||
*/
|
||||
*a = newstate->wm.ilk.optimal;
|
||||
if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
|
||||
if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
|
||||
intel_state->skip_intermediate_wm)
|
||||
return 0;
|
||||
|
||||
|
@ -3770,7 +3770,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
|
|||
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
||||
crtc_state = to_intel_crtc_state(crtc->base.state);
|
||||
|
||||
if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
return false;
|
||||
|
||||
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
||||
|
@ -3820,7 +3820,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
|
|||
if (INTEL_GEN(dev_priv) < 11)
|
||||
return ddb_size - 4; /* 4 blocks for bypass path allocation */
|
||||
|
||||
adjusted_mode = &crtc_state->base.adjusted_mode;
|
||||
adjusted_mode = &crtc_state->hw.adjusted_mode;
|
||||
total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
|
||||
|
||||
/*
|
||||
|
@ -3858,7 +3858,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
|
|||
u16 ddb_size;
|
||||
u32 i;
|
||||
|
||||
if (WARN_ON(!state) || !crtc_state->base.active) {
|
||||
if (WARN_ON(!state) || !crtc_state->hw.active) {
|
||||
alloc->start = 0;
|
||||
alloc->end = 0;
|
||||
*num_active = hweight8(dev_priv->active_pipes);
|
||||
|
@ -3897,11 +3897,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
|
|||
*/
|
||||
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->base.adjusted_mode;
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
enum pipe pipe = crtc->pipe;
|
||||
int hdisplay, vdisplay;
|
||||
|
||||
if (!crtc_state->base.enable)
|
||||
if (!crtc_state->hw.enable)
|
||||
continue;
|
||||
|
||||
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
|
||||
|
@ -4238,7 +4238,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
|
|||
if (WARN_ON(!state))
|
||||
return 0;
|
||||
|
||||
if (!crtc_state->base.active) {
|
||||
if (!crtc_state->hw.active) {
|
||||
alloc->start = alloc->end = 0;
|
||||
return 0;
|
||||
}
|
||||
|
@ -4480,7 +4480,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
|
|||
u32 crtc_htotal;
|
||||
uint_fixed_16_16_t linetime_us;
|
||||
|
||||
if (!crtc_state->base.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return u32_to_fixed16(0);
|
||||
|
||||
pixel_rate = crtc_state->pixel_rate;
|
||||
|
@ -4488,7 +4488,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
|
|||
if (WARN_ON(pixel_rate == 0))
|
||||
return u32_to_fixed16(0);
|
||||
|
||||
crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
|
||||
crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
|
||||
linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
|
||||
|
||||
return linetime_us;
|
||||
|
@ -4670,14 +4670,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
|
|||
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
|
||||
wp->cpp, latency, wp->dbuf_block_size);
|
||||
method2 = skl_wm_method2(wp->plane_pixel_rate,
|
||||
crtc_state->base.adjusted_mode.crtc_htotal,
|
||||
crtc_state->hw.adjusted_mode.crtc_htotal,
|
||||
latency,
|
||||
wp->plane_blocks_per_line);
|
||||
|
||||
if (wp->y_tiled) {
|
||||
selected_result = max_fixed16(method2, wp->y_tile_minimum);
|
||||
} else {
|
||||
if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
|
||||
if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
|
||||
wp->dbuf_block_size < 1) &&
|
||||
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
|
||||
selected_result = method2;
|
||||
|
|
Loading…
Reference in a new issue