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ARM: AT91: update clock source registration
In d7e81c2
(clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants. Switch over to using this new interface.
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
40cc524400
commit
132b16325f
2 changed files with 2 additions and 6 deletions
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@ -101,7 +101,6 @@ static struct clocksource clk32k = {
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.rating = 150,
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.rating = 150,
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.read = read_clk32k,
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.read = read_clk32k,
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.mask = CLOCKSOURCE_MASK(20),
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.mask = CLOCKSOURCE_MASK(20),
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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};
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@ -201,8 +200,7 @@ void __init at91rm9200_timer_init(void)
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clockevents_register_device(&clkevt);
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clockevents_register_device(&clkevt);
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/* register clocksource */
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/* register clocksource */
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clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
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clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
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clocksource_register(&clk32k);
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}
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}
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struct sys_timer at91rm9200_timer = {
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struct sys_timer at91rm9200_timer = {
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@ -51,7 +51,6 @@ static struct clocksource pit_clk = {
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.name = "pit",
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.name = "pit",
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.rating = 175,
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.rating = 175,
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.read = read_pit_clk,
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.read = read_pit_clk,
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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};
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@ -163,10 +162,9 @@ static void __init at91sam926x_pit_init(void)
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* Register clocksource. The high order bits of PIV are unused,
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* Register clocksource. The high order bits of PIV are unused,
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* so this isn't a 32-bit counter unless we get clockevent irqs.
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* so this isn't a 32-bit counter unless we get clockevent irqs.
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*/
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*/
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pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
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bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
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bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
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pit_clk.mask = CLOCKSOURCE_MASK(bits);
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pit_clk.mask = CLOCKSOURCE_MASK(bits);
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clocksource_register(&pit_clk);
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clocksource_register_hz(&pit_clk, pit_rate);
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/* Set up irq handler */
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/* Set up irq handler */
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setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
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setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
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