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Code Issues Releases Wiki Activity

Staging driver fixes and removal for 6.3-rc2 

Here are 4 small staging driver fixes, and one big staging driver
 deletion for 6.3-rc2.
 
 The fixes are:
   - rtl8192e driver fixes for where the driver was attempting to execute
     various programs directly from the disk for unknown reasons
   - rtl8723bs driver fixes for issues found by Hans in testing
 
 The deleted driver is the removal of the r8188eu wireless driver as now
 in 6.3-rc1 we have a "real" wifi driver for one that includes support
 for many many more devices than this old driver did.  So it's time to
 remove it as it is no longer needed.  The maintainers of this driver all
 have acked its removal.  Many thanks to them over the years for working
 to clean it up and keep it working while the real driver was being
 developed.
 
 All of these have been in linux-next this week with no reported
 problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-6.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging driver fixes and removal from Greg KH:
 "Here are four small staging driver fixes, and one big staging driver
  deletion for 6.3-rc2.

  The fixes are:

   - rtl8192e driver fixes for where the driver was attempting to
     execute various programs directly from the disk for unknown reasons

   - rtl8723bs driver fixes for issues found by Hans in testing

  The deleted driver is the removal of the r8188eu wireless driver as
  now in 6.3-rc1 we have a "real" wifi driver for one that includes
  support for many many more devices than this old driver did. So it's
  time to remove it as it is no longer needed. The maintainers of this
  driver all have acked its removal. Many thanks to them over the years
  for working to clean it up and keep it working while the real driver
  was being developed.

  All of these have been in linux-next this week with no reported
  problems"

* tag 'staging-6.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
  staging: r8188eu: delete driver
  staging: rtl8723bs: Pass correct parameters to cfg80211_get_bss()
  staging: rtl8723bs: Fix key-store index handling
  staging: rtl8192e: Remove call_usermodehelper starting RadioPower.sh
  staging: rtl8192e: Remove function ..dm_check_ac_dc_power calling a script
This commit is contained in:
Linus Torvalds 2023-03-12 09:17:30 -07:00
parent d3d0cac69f fdf6c2309f
commit 1342316648
106 changed files with 39 additions and 51308 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MAINTAINERS
View File

@ -19864,13 +19864,6 @@ S: Maintained
W: http://wiki.laptop.org/go/DCON W: http://wiki.laptop.org/go/DCON
F: drivers/staging/olpc_dcon/ F: drivers/staging/olpc_dcon/
STAGING - REALTEK RTL8188EU DRIVERS
M: Larry Finger <Larry.Finger@lwfinger.net>
M: Phillip Potter <phil@philpotter.co.uk>
R: Pavel Skripkin <paskripkin@gmail.com>
S: Supported
F: drivers/staging/r8188eu/
STAGING - REALTEK RTL8712U DRIVERS STAGING - REALTEK RTL8712U DRIVERS
M: Larry Finger <Larry.Finger@lwfinger.net> M: Larry Finger <Larry.Finger@lwfinger.net>
M: Florian Schilhabel <florian.c.schilhabel@googlemail.com>. M: Florian Schilhabel <florian.c.schilhabel@googlemail.com>.

2
drivers/staging/Kconfig
View File

@ -36,8 +36,6 @@ source "drivers/staging/rtl8723bs/Kconfig"
source "drivers/staging/rtl8712/Kconfig" source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/r8188eu/Kconfig"
source "drivers/staging/rts5208/Kconfig" source "drivers/staging/rts5208/Kconfig"
source "drivers/staging/octeon/Kconfig" source "drivers/staging/octeon/Kconfig"

1
drivers/staging/Makefile
View File

@ -8,7 +8,6 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/ obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_RTL8723BS) += rtl8723bs/ obj-$(CONFIG_RTL8723BS) += rtl8723bs/
obj-$(CONFIG_R8712U) += rtl8712/ obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_R8188EU) += r8188eu/
obj-$(CONFIG_RTS5208) += rts5208/ obj-$(CONFIG_RTS5208) += rts5208/
obj-$(CONFIG_OCTEON_ETHERNET) += octeon/ obj-$(CONFIG_OCTEON_ETHERNET) += octeon/
obj-$(CONFIG_VT6655) += vt6655/ obj-$(CONFIG_VT6655) += vt6655/

16
drivers/staging/r8188eu/Kconfig
View File

@ -1,16 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config R8188EU
tristate "Realtek RTL8188EU Wireless LAN NIC driver"
depends on WLAN && USB && CFG80211
depends on m
select WIRELESS_EXT
select WEXT_PRIV
select LIB80211
select LIB80211_CRYPT_WEP
select LIB80211_CRYPT_CCMP
help
This option adds support for the Realtek RTL8188EU chipset, used in USB
devices such as the ASUS USB-N10 Nano. This newer driver is based on GitHub
sources for version v4.1.4_6773.20130222, and contains modifications for
newer kernel features. If built as a module, it will be called r8188eu.

48
drivers/staging/r8188eu/Makefile
View File

@ -1,48 +0,0 @@
r8188eu-y = \
hal/HalHWImg8188E_MAC.o \
hal/HalHWImg8188E_BB.o \
hal/HalHWImg8188E_RF.o \
hal/HalPhyRf_8188e.o \
hal/HalPwrSeqCmd.o \
hal/Hal8188ERateAdaptive.o \
hal/hal_intf.o \
hal/hal_com.o \
hal/odm.o \
hal/odm_HWConfig.o \
hal/odm_RTL8188E.o \
hal/rtl8188e_cmd.o \
hal/rtl8188e_dm.o \
hal/rtl8188e_hal_init.o \
hal/rtl8188e_phycfg.o \
hal/rtl8188e_rf6052.o \
hal/rtl8188e_rxdesc.o \
hal/rtl8188eu_xmit.o \
hal/usb_halinit.o \
hal/usb_ops_linux.o \
os_dep/ioctl_linux.o \
os_dep/os_intfs.o \
os_dep/osdep_service.o \
os_dep/usb_intf.o \
os_dep/usb_ops_linux.o \
core/rtw_ap.o \
core/rtw_br_ext.o \
core/rtw_cmd.o \
core/rtw_efuse.o \
core/rtw_fw.o \
core/rtw_ieee80211.o \
core/rtw_ioctl_set.o \
core/rtw_iol.o \
core/rtw_led.o \
core/rtw_mlme.o \
core/rtw_mlme_ext.o \
core/rtw_pwrctrl.o \
core/rtw_p2p.o \
core/rtw_recv.o \
core/rtw_rf.o \
core/rtw_security.o \
core/rtw_sta_mgt.o \
core/rtw_wlan_util.o \
core/rtw_xmit.o
obj-$(CONFIG_R8188EU) := r8188eu.o

16
drivers/staging/r8188eu/TODO
View File

@ -1,16 +0,0 @@
To-do list:
* Correct the coding style according to Linux guidelines; please read the document
at https://www.kernel.org/doc/html/latest/process/coding-style.html.
* Remove unnecessary debugging/printing macros; for those that are still needed
use the proper kernel API (pr_debug(), dev_dbg(), netdev_dbg()).
* Remove dead code such as unusued functions, variables, fields, etc..
* Use in-kernel API and remove unnecessary wrappers where possible.
* Fix bugs due to code that sleeps in atomic context.
* Remove the HAL layer and migrate its functionality into the relevant parts of
the driver.
* Switch to use LIB80211.
* Switch to use MAC80211.
* Switch to use CFG80211.
* Improve the error handling of various functions, particularly those that use
existing kernel APIs.

1181
drivers/staging/r8188eu/core/rtw_ap.c
View File

File diff suppressed because it is too large Load Diff

658
drivers/staging/r8188eu/core/rtw_br_ext.c
View File

@ -1,658 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. i*/
#define _RTW_BR_EXT_C_
#include "../include/linux/if_arp.h"
#include "../include/net/ip.h"
#include "../include/linux/atalk.h"
#include "../include/linux/udp.h"
#include "../include/linux/if_pppox.h"
#include "../include/drv_types.h"
#include "../include/rtw_br_ext.h"
#include "../include/usb_osintf.h"
#ifndef csum_ipv6_magic
#include "../include/net/ip6_checksum.h"
#endif
#include "../include/linux/ipv6.h"
#include "../include/linux/icmpv6.h"
#include "../include/net/ndisc.h"
#include "../include/net/checksum.h"
#define NAT25_IPV4 01
#define NAT25_IPV6 02
#define NAT25_IPX 03
#define NAT25_APPLE 04
#define NAT25_PPPOE 05
#define RTL_RELAY_TAG_LEN (ETH_ALEN)
#define TAG_HDR_LEN 4
#define MAGIC_CODE 0x8186
#define MAGIC_CODE_LEN 2
#define WAIT_TIME_PPPOE 5 /* waiting time for pppoe server in sec */
/*-----------------------------------------------------------------
How database records network address:
0 1 2 3 4 5 6 7 8 9 10
|----|----|----|----|----|----|----|----|----|----|----|
IPv4 |type| | IP addr |
IPX |type| Net addr | Node addr |
IPX |type| Net addr |Sckt addr|
Apple |type| Network |node|
PPPoE |type| SID | AC MAC |
-----------------------------------------------------------------*/
/* Find a tag in pppoe frame and return the pointer */
static unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type)
{
unsigned char *cur_ptr, *start_ptr;
unsigned short tag_len, tag_type;
start_ptr = (unsigned char *)ph->tag;
cur_ptr = (unsigned char *)ph->tag;
while ((cur_ptr - start_ptr) < ntohs(ph->length)) {
/* prevent un-alignment access */
tag_type = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]);
tag_len = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]);
if (tag_type == type)
return cur_ptr;
cur_ptr = cur_ptr + TAG_HDR_LEN + tag_len;
}
return NULL;
}
static int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag)
{
struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
int data_len;
data_len = be16_to_cpu(tag->tag_len) + TAG_HDR_LEN;
if (skb_tailroom(skb) < data_len)
return -1;
skb_put(skb, data_len);
/* have a room for new tag */
memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length));
ph->length = htons(ntohs(ph->length) + data_len);
memcpy((unsigned char *)ph->tag, tag, data_len);
return data_len;
}
static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len)
{
int tail_len;
unsigned long end, tail;
if ((src + len) > skb_tail_pointer(skb) || skb->len < len)
return -1;
tail = (unsigned long)skb_tail_pointer(skb);
end = (unsigned long)src + len;
if (tail < end)
return -1;
tail_len = (int)(tail - end);
if (tail_len > 0)
memmove(src, src + len, tail_len);
skb_trim(skb, skb->len - len);
return 0;
}
static int __nat25_has_expired(struct nat25_network_db_entry *fdb)
{
if (time_before_eq(fdb->ageing_timer, jiffies - NAT25_AGEING_TIME * HZ))
return 1;
return 0;
}
static void __nat25_generate_ipv4_network_addr(unsigned char *addr,
unsigned int *ip_addr)
{
memset(addr, 0, MAX_NETWORK_ADDR_LEN);
addr[0] = NAT25_IPV4;
memcpy(addr + 7, (unsigned char *)ip_addr, 4);
}
static void __nat25_generate_pppoe_network_addr(unsigned char *addr,
unsigned char *ac_mac, __be16 *sid)
{
memset(addr, 0, MAX_NETWORK_ADDR_LEN);
addr[0] = NAT25_PPPOE;
memcpy(addr + 1, (unsigned char *)sid, 2);
memcpy(addr + 3, (unsigned char *)ac_mac, 6);
}
static void __nat25_generate_ipv6_network_addr(unsigned char *addr,
unsigned int *ip_addr)
{
memset(addr, 0, MAX_NETWORK_ADDR_LEN);
addr[0] = NAT25_IPV6;
memcpy(addr + 1, (unsigned char *)ip_addr, 16);
}
static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b)
{
while (len > 0) {
if (*data == tag && *(data + 1) == len8b && len >= len8b * 8)
return data + 2;
len -= (*(data + 1)) * 8;
data += (*(data + 1)) * 8;
}
return NULL;
}
static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac)
{
struct icmp6hdr *icmphdr = (struct icmp6hdr *)data;
unsigned char *mac;
if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) {
if (len >= 8) {
mac = scan_tlv(&data[8], len - 8, 1, 1);
if (mac) {
memcpy(mac, replace_mac, 6);
return 1;
}
}
} else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) {
if (len >= 16) {
mac = scan_tlv(&data[16], len - 16, 1, 1);
if (mac) {
memcpy(mac, replace_mac, 6);
return 1;
}
}
} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) {
if (len >= 24) {
mac = scan_tlv(&data[24], len - 24, 1, 1);
if (mac) {
memcpy(mac, replace_mac, 6);
return 1;
}
}
} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) {
if (len >= 24) {
mac = scan_tlv(&data[24], len - 24, 2, 1);
if (mac) {
memcpy(mac, replace_mac, 6);
return 1;
}
}
} else if (icmphdr->icmp6_type == NDISC_REDIRECT) {
if (len >= 40) {
mac = scan_tlv(&data[40], len - 40, 2, 1);
if (mac) {
memcpy(mac, replace_mac, 6);
return 1;
}
}
}
return 0;
}
static int __nat25_network_hash(unsigned char *addr)
{
if (addr[0] == NAT25_IPV4) {
unsigned long x;
x = addr[7] ^ addr[8] ^ addr[9] ^ addr[10];
return x & (NAT25_HASH_SIZE - 1);
} else if (addr[0] == NAT25_IPX) {
unsigned long x;
x = addr[1] ^ addr[2] ^ addr[3] ^ addr[4] ^ addr[5] ^
addr[6] ^ addr[7] ^ addr[8] ^ addr[9] ^ addr[10];
return x & (NAT25_HASH_SIZE - 1);
} else if (addr[0] == NAT25_APPLE) {
unsigned long x;
x = addr[1] ^ addr[2] ^ addr[3];
return x & (NAT25_HASH_SIZE - 1);
} else if (addr[0] == NAT25_PPPOE) {
unsigned long x;
x = addr[0] ^ addr[1] ^ addr[2] ^ addr[3] ^ addr[4] ^
addr[5] ^ addr[6] ^ addr[7] ^ addr[8];
return x & (NAT25_HASH_SIZE - 1);
} else if (addr[0] == NAT25_IPV6) {
unsigned long x;
x = addr[1] ^ addr[2] ^ addr[3] ^ addr[4] ^ addr[5] ^ addr[6] ^
addr[7] ^ addr[8] ^ addr[9] ^ addr[10] ^ addr[11] ^ addr[12] ^
addr[13] ^ addr[14] ^ addr[15] ^ addr[16];
return x & (NAT25_HASH_SIZE - 1);
} else {
unsigned long x = 0;
int i;
for (i = 0; i < MAX_NETWORK_ADDR_LEN; i++)
x ^= addr[i];
return x & (NAT25_HASH_SIZE - 1);
}
}
static void __network_hash_link(struct adapter *priv,
struct nat25_network_db_entry *ent, int hash)
{
/* Caller must spin_lock already! */
ent->next_hash = priv->nethash[hash];
if (ent->next_hash)
ent->next_hash->pprev_hash = &ent->next_hash;
priv->nethash[hash] = ent;
ent->pprev_hash = &priv->nethash[hash];
}
static void __network_hash_unlink(struct nat25_network_db_entry *ent)
{
/* Caller must spin_lock already! */
*ent->pprev_hash = ent->next_hash;
if (ent->next_hash)
ent->next_hash->pprev_hash = ent->pprev_hash;
ent->next_hash = NULL;
ent->pprev_hash = NULL;
}
static void __nat25_db_network_insert(struct adapter *priv,
unsigned char *mac_addr, unsigned char *addr)
{
struct nat25_network_db_entry *db;
int hash;
spin_lock_bh(&priv->br_ext_lock);
hash = __nat25_network_hash(addr);
db = priv->nethash[hash];
while (db) {
if (!memcmp(db->networkAddr, addr, MAX_NETWORK_ADDR_LEN)) {
memcpy(db->macAddr, mac_addr, ETH_ALEN);
db->ageing_timer = jiffies;
spin_unlock_bh(&priv->br_ext_lock);
return;
}
db = db->next_hash;
}
db = kmalloc(sizeof(*db), GFP_ATOMIC);
if (!db) {
spin_unlock_bh(&priv->br_ext_lock);
return;
}
memcpy(db->networkAddr, addr, MAX_NETWORK_ADDR_LEN);
memcpy(db->macAddr, mac_addr, ETH_ALEN);
atomic_set(&db->use_count, 1);
db->ageing_timer = jiffies;
__network_hash_link(priv, db, hash);
spin_unlock_bh(&priv->br_ext_lock);
}
/*
* NAT2.5 interface
*/
void nat25_db_cleanup(struct adapter *priv)
{
int i;
spin_lock_bh(&priv->br_ext_lock);
for (i = 0; i < NAT25_HASH_SIZE; i++) {
struct nat25_network_db_entry *f;
f = priv->nethash[i];
while (f) {
struct nat25_network_db_entry *g;
g = f->next_hash;
if (priv->scdb_entry == f) {
memset(priv->scdb_mac, 0, ETH_ALEN);
memset(priv->scdb_ip, 0, 4);
priv->scdb_entry = NULL;
}
__network_hash_unlink(f);
kfree(f);
f = g;
}
}
spin_unlock_bh(&priv->br_ext_lock);
}
void nat25_db_expire(struct adapter *priv)
{
int i;
spin_lock_bh(&priv->br_ext_lock);
for (i = 0; i < NAT25_HASH_SIZE; i++) {
struct nat25_network_db_entry *f;
f = priv->nethash[i];
while (f) {
struct nat25_network_db_entry *g;
g = f->next_hash;
if (__nat25_has_expired(f)) {
if (atomic_dec_and_test(&f->use_count)) {
if (priv->scdb_entry == f) {
memset(priv->scdb_mac, 0, ETH_ALEN);
memset(priv->scdb_ip, 0, 4);
priv->scdb_entry = NULL;
}
__network_hash_unlink(f);
kfree(f);
}
}
f = g;
}
}
spin_unlock_bh(&priv->br_ext_lock);
}
int nat25_db_handle(struct adapter *priv, struct sk_buff *skb, int method)
{
unsigned short protocol;
unsigned char addr[MAX_NETWORK_ADDR_LEN];
unsigned int tmp;
if (!skb)
return -1;
if ((method <= NAT25_MIN) || (method >= NAT25_MAX))
return -1;
protocol = be16_to_cpu(*((__be16 *)(skb->data + 2 * ETH_ALEN)));
/*---------------------------------------------------*/
/* Handle IP frame */
/*---------------------------------------------------*/
if (protocol == ETH_P_IP) {
struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
if (((unsigned char *)(iph) + (iph->ihl << 2)) >= (skb->data + ETH_HLEN + skb->len))
return -1;
switch (method) {
case NAT25_CHECK:
return -1;
case NAT25_INSERT:
/* some multicast with source IP is all zero, maybe other case is illegal */
/* in class A, B, C, host address is all zero or all one is illegal */
if (iph->saddr == 0)
return 0;
tmp = be32_to_cpu(iph->saddr);
__nat25_generate_ipv4_network_addr(addr, &tmp);
/* record source IP address and , source mac address into db */
__nat25_db_network_insert(priv, skb->data + ETH_ALEN, addr);
return 0;
default:
return -1;
}
} else if (protocol == ETH_P_ARP) {
/*---------------------------------------------------*/
/* Handle ARP frame */
/*---------------------------------------------------*/
struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN);
unsigned char *arp_ptr = (unsigned char *)(arp + 1);
unsigned int *sender;
if (arp->ar_pro != htons(ETH_P_IP))
return -1;
switch (method) {
case NAT25_CHECK:
return 0; /* skb_copy for all ARP frame */
case NAT25_INSERT:
/* change to ARP sender mac address to wlan STA address */
memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN);
arp_ptr += arp->ar_hln;
sender = (unsigned int *)arp_ptr;
__nat25_generate_ipv4_network_addr(addr, sender);
__nat25_db_network_insert(priv, skb->data + ETH_ALEN, addr);
return 0;
default:
return -1;
}
} else if ((protocol == ETH_P_PPP_DISC) ||
(protocol == ETH_P_PPP_SES)) {
/*---------------------------------------------------*/
/* Handle PPPoE frame */
/*---------------------------------------------------*/
struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
__be16 *pMagic;
switch (method) {
case NAT25_CHECK:
if (ph->sid == 0)
return 0;
return 1;
case NAT25_INSERT:
if (ph->sid == 0) { /* Discovery phase according to tag */
if (ph->code == PADI_CODE || ph->code == PADR_CODE) {
if (priv->ethBrExtInfo.addPPPoETag) {
struct pppoe_tag *tag, *pOldTag;
unsigned char tag_buf[40];
int old_tag_len = 0;
tag = (struct pppoe_tag *)tag_buf;
pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
if (pOldTag) { /* if SID existed, copy old value and delete it */
old_tag_len = ntohs(pOldTag->tag_len);
if (old_tag_len +
TAG_HDR_LEN +
MAGIC_CODE_LEN +
RTL_RELAY_TAG_LEN >
sizeof(tag_buf))
return -1;
memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN,
pOldTag->tag_data, old_tag_len);
if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0)
return -1;
ph->length = htons(ntohs(ph->length) - TAG_HDR_LEN - old_tag_len);
}
tag->tag_type = PTT_RELAY_SID;
tag->tag_len = htons(MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN + old_tag_len);
/* insert the magic_code+client mac in relay tag */
pMagic = (__be16 *)tag->tag_data;
*pMagic = htons(MAGIC_CODE);
memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN);
/* Add relay tag */
if (__nat25_add_pppoe_tag(skb, tag) < 0)
return -1;
} else { /* not add relay tag */
if (priv->pppoe_connection_in_progress &&
memcmp(skb->data + ETH_ALEN,
priv->pppoe_addr,
ETH_ALEN))
return -2;
if (priv->pppoe_connection_in_progress == 0)
memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN);
priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
}
} else {
return -1;
}
} else { /* session phase */
__nat25_generate_pppoe_network_addr(addr, skb->data, &ph->sid);
__nat25_db_network_insert(priv, skb->data + ETH_ALEN, addr);
if (!priv->ethBrExtInfo.addPPPoETag &&
priv->pppoe_connection_in_progress &&
!memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))
priv->pppoe_connection_in_progress = 0;
}
return 0;
default:
return -1;
}
} else if (protocol == 0x888e) {
/*---------------------------------------------------*/
/* Handle EAP frame */
/*---------------------------------------------------*/
switch (method) {
case NAT25_CHECK:
return -1;
case NAT25_INSERT:
return 0;
default:
return -1;
}
} else if ((protocol == 0xe2ae) || (protocol == 0xe2af)) {
/*---------------------------------------------------*/
/* Handle C-Media proprietary frame */
/*---------------------------------------------------*/
switch (method) {
case NAT25_CHECK:
return -1;
case NAT25_INSERT:
return 0;
default:
return -1;
}
} else if (protocol == ETH_P_IPV6) {
/*------------------------------------------------*/
/* Handle IPV6 frame */
/*------------------------------------------------*/
struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
if (sizeof(*iph) >= (skb->len - ETH_HLEN))
return -1;
switch (method) {
case NAT25_CHECK:
if (skb->data[0] & 1)
return 0;
return -1;
case NAT25_INSERT:
if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) {
__nat25_generate_ipv6_network_addr(addr, (unsigned int *)&iph->saddr);
__nat25_db_network_insert(priv, skb->data + ETH_ALEN, addr);
if (iph->nexthdr == IPPROTO_ICMPV6 &&
skb->len > (ETH_HLEN + sizeof(*iph) + 4)) {
if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph),
skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) {
struct icmp6hdr *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph));
hdr->icmp6_cksum = 0;
hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr,
be16_to_cpu(iph->payload_len),
IPPROTO_ICMPV6,
csum_partial((__u8 *)hdr,
be16_to_cpu(iph->payload_len),
0));
}
}
}
return 0;
default:
return -1;
}
}
return -1;
}
#define SERVER_PORT 67
#define CLIENT_PORT 68
#define DHCP_MAGIC 0x63825363
#define BROADCAST_FLAG 0x8000
struct dhcpMessage {
u_int8_t op;
u_int8_t htype;
u_int8_t hlen;
u_int8_t hops;
u_int32_t xid;
__be16 secs;
__be16 flags;
__be32 ciaddr;
__be32 yiaddr;
__be32 siaddr;
__be32 giaddr;
u_int8_t chaddr[16];
u_int8_t sname[64];
u_int8_t file[128];
__be32 cookie;
u_int8_t options[308]; /* 312 - cookie */
};
void dhcp_flag_bcast(struct adapter *priv, struct sk_buff *skb)
{
if (!skb)
return;
if (!priv->ethBrExtInfo.dhcp_bcst_disable) {
__be16 protocol = *((__be16 *)(skb->data + 2 * ETH_ALEN));
if (protocol == htons(ETH_P_IP)) { /* IP */
struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
if (iph->protocol == IPPROTO_UDP) { /* UDP */
struct udphdr *udph = (void *)iph + (iph->ihl << 2);
if ((udph->source == htons(CLIENT_PORT)) &&
(udph->dest == htons(SERVER_PORT))) { /* DHCP request */
struct dhcpMessage *dhcph = (void *)udph + sizeof(struct udphdr);
u32 cookie = be32_to_cpu(dhcph->cookie);
if (cookie == DHCP_MAGIC) { /* match magic word */
if (!(dhcph->flags & htons(BROADCAST_FLAG))) {
/* if not broadcast */
register int sum = 0;
/* or BROADCAST flag */
dhcph->flags |= htons(BROADCAST_FLAG);
/* recalculate checksum */
sum = ~(udph->check) & 0xffff;
sum += be16_to_cpu(dhcph->flags);
while (sum >> 16)
sum = (sum & 0xffff) + (sum >> 16);
udph->check = ~sum;
}
}
}
}
}
}
}
void *scdb_findEntry(struct adapter *priv, unsigned char *ip_addr)
{
unsigned char addr[MAX_NETWORK_ADDR_LEN];
struct nat25_network_db_entry *db;
int hash;
__nat25_generate_ipv4_network_addr(addr, (unsigned int *)ip_addr);
hash = __nat25_network_hash(addr);
db = priv->nethash[hash];
while (db) {
if (!memcmp(db->networkAddr, addr, MAX_NETWORK_ADDR_LEN))
return (void *)db;
db = db->next_hash;
}
return NULL;
}

1529
drivers/staging/r8188eu/core/rtw_cmd.c
View File

File diff suppressed because it is too large Load Diff

74
drivers/staging/r8188eu/core/rtw_efuse.c
View File

@ -1,74 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _RTW_EFUSE_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtw_efuse.h"
#include "../include/rtl8188e_hal.h"
/* */
/* Description: */
/* Execute E-Fuse read byte operation. */
/* Referred from SD1 Richard. */
/* */
/* Assumption: */
/* 1. Boot from E-Fuse and successfully auto-load. */
/* 2. PASSIVE_LEVEL (USB interface) */
/* */
/* Created by Roger, 2008.10.21. */
/* */
void
ReadEFuseByte(
struct adapter *Adapter,
u16 _offset,
u8 *pbuf)
{
u32 value32;
u8 readbyte;
u16 retry;
int res;
/* Write Address */
rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
res = rtw_read8(Adapter, EFUSE_CTRL + 2, &readbyte);
if (res)
return;
rtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
/* Write bit 32 0 */
res = rtw_read8(Adapter, EFUSE_CTRL + 3, &readbyte);
if (res)
return;
rtw_write8(Adapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
/* Check bit 32 read-ready */
res = rtw_read32(Adapter, EFUSE_CTRL, &value32);
if (res)
return;
for (retry = 0; retry < 10000; retry++) {
res = rtw_read32(Adapter, EFUSE_CTRL, &value32);
if (res)
continue;
if (((value32 >> 24) & 0xff) & 0x80)
break;
}
/* 20100205 Joseph: Add delay suggested by SD1 Victor. */
/* This fix the problem that Efuse read error in high temperature condition. */
/* Designer says that there shall be some delay after ready bit is set, or the */
/* result will always stay on last data we read. */
udelay(50);
res = rtw_read32(Adapter, EFUSE_CTRL, &value32);
if (res)
return;
*pbuf = (u8)(value32 & 0xff);
/* FIXME: return an error to caller */
}

335
drivers/staging/r8188eu/core/rtw_fw.c
View File

@ -1,335 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include <linux/firmware.h>
#include "../include/rtw_fw.h"
#define MAX_REG_BLOCK_SIZE 196
#define FW_8188E_START_ADDRESS 0x1000
#define MAX_PAGE_SIZE 4096
#define IS_FW_HEADER_EXIST(_fwhdr) \
((le16_to_cpu(_fwhdr->signature) & 0xFFF0) == 0x92C0 || \
(le16_to_cpu(_fwhdr->signature) & 0xFFF0) == 0x88C0 || \
(le16_to_cpu(_fwhdr->signature) & 0xFFF0) == 0x2300 || \
(le16_to_cpu(_fwhdr->signature) & 0xFFF0) == 0x88E0)
struct rt_firmware_hdr {
__le16 signature; /* 92C0: test chip; 92C,
* 88C0: test chip; 88C1: MP A-cut;
* 92C1: MP A-cut */
u8 category; /* AP/NIC and USB/PCI */
u8 function; /* Reserved for different FW function
* indcation, for further use when
* driver needs to download different
* FW for different conditions */
__le16 version; /* FW Version */
u8 subversion; /* FW Subversion, default 0x00 */
u8 rsvd1;
u8 month; /* Release time Month field */
u8 date; /* Release time Date field */
u8 hour; /* Release time Hour field */
u8 minute; /* Release time Minute field */
__le16 ramcodesize; /* The size of RAM code */
u8 foundry;
u8 rsvd2;
__le32 svnidx; /* The SVN entry index */
__le32 rsvd3;
__le32 rsvd4;
__le32 rsvd5;
};
static_assert(sizeof(struct rt_firmware_hdr) == 32);
static void fw_download_enable(struct adapter *padapter, bool enable)
{
u8 tmp;
int res;
if (enable) {
/* MCU firmware download enable. */
res = rtw_read8(padapter, REG_MCUFWDL, &tmp);
if (res)
return;
rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
/* 8051 reset */
res = rtw_read8(padapter, REG_MCUFWDL + 2, &tmp);
if (res)
return;
rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
} else {
/* MCU firmware download disable. */
res = rtw_read8(padapter, REG_MCUFWDL, &tmp);
if (res)
return;
rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
/* Reserved for fw extension. */
rtw_write8(padapter, REG_MCUFWDL + 1, 0x00);
}
}
static int block_write(struct adapter *padapter, u8 *buffer, u32 size)
{
int ret = _SUCCESS;
u32 blocks, block_size, remain;
u32 i, offset, addr;
u8 *data;
block_size = MAX_REG_BLOCK_SIZE;
blocks = size / block_size;
remain = size % block_size;
for (i = 0; i < blocks; i++) {
addr = FW_8188E_START_ADDRESS + i * block_size;
data = buffer + i * block_size;
if (rtw_writeN(padapter, addr, block_size, data))
return _FAIL;
}
if (remain) {
offset = blocks * block_size;
block_size = 8;
blocks = remain / block_size;
remain = remain % block_size;
for (i = 0; i < blocks; i++) {
addr = FW_8188E_START_ADDRESS + offset + i * block_size;
data = buffer + offset + i * block_size;
if (rtw_writeN(padapter, addr, block_size, data))
return _FAIL;
}
}
if (remain) {
offset += blocks * block_size;
/* block size 1 */
blocks = remain;
for (i = 0; i < blocks; i++) {
addr = FW_8188E_START_ADDRESS + offset + i;
data = buffer + offset + i;
ret = rtw_write8(padapter, addr, *data);
if (ret == _FAIL)
goto exit;
}
}
exit:
return ret;
}
static int page_write(struct adapter *padapter, u32 page, u8 *buffer, u32 size)
{
u8 value8;
u8 u8Page = (u8)(page & 0x07);
int res;
res = rtw_read8(padapter, REG_MCUFWDL + 2, &value8);
if (res)
return _FAIL;
value8 = (value8 & 0xF8) | u8Page;
rtw_write8(padapter, REG_MCUFWDL + 2, value8);
return block_write(padapter, buffer, size);
}
static int write_fw(struct adapter *padapter, u8 *buffer, u32 size)
{
/* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
/* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
int ret = _SUCCESS;
u32 pageNums, remainSize;
u32 page, offset;
pageNums = size / MAX_PAGE_SIZE;
remainSize = size % MAX_PAGE_SIZE;
for (page = 0; page < pageNums; page++) {
offset = page * MAX_PAGE_SIZE;
ret = page_write(padapter, page, buffer + offset, MAX_PAGE_SIZE);
if (ret == _FAIL)
goto exit;
}
if (remainSize) {
offset = pageNums * MAX_PAGE_SIZE;
page = pageNums;
ret = page_write(padapter, page, buffer + offset, remainSize);
if (ret == _FAIL)
goto exit;
}
exit:
return ret;
}
void rtw_reset_8051(struct adapter *padapter)
{
u8 val8;
int res;
res = rtw_read8(padapter, REG_SYS_FUNC_EN + 1, &val8);
if (res)
return;
rtw_write8(padapter, REG_SYS_FUNC_EN + 1, val8 & (~BIT(2)));
rtw_write8(padapter, REG_SYS_FUNC_EN + 1, val8 | (BIT(2)));
}
static int fw_free_to_go(struct adapter *padapter)
{
u32 counter = 0;
u32 value32;
int res;
/* polling CheckSum report */
do {
res = rtw_read32(padapter, REG_MCUFWDL, &value32);
if (res)
continue;
if (value32 & FWDL_CHKSUM_RPT)
break;
} while (counter++ < POLLING_READY_TIMEOUT_COUNT);
if (counter >= POLLING_READY_TIMEOUT_COUNT)
return _FAIL;
res = rtw_read32(padapter, REG_MCUFWDL, &value32);
if (res)
return _FAIL;
value32 |= MCUFWDL_RDY;
value32 &= ~WINTINI_RDY;
rtw_write32(padapter, REG_MCUFWDL, value32);
rtw_reset_8051(padapter);
/* polling for FW ready */
counter = 0;
do {
res = rtw_read32(padapter, REG_MCUFWDL, &value32);
if (!res && value32 & WINTINI_RDY)
return _SUCCESS;
udelay(5);
} while (counter++ < POLLING_READY_TIMEOUT_COUNT);
return _FAIL;
}
static int load_firmware(struct rt_firmware *rtfw, struct device *device)
{
int ret = _SUCCESS;
const struct firmware *fw;
const char *fw_name = FW_RTL8188EU;
int err = request_firmware(&fw, fw_name, device);
if (err) {
pr_err("Request firmware failed with error 0x%x\n", err);
ret = _FAIL;
goto exit;
}
if (!fw) {
pr_err("Firmware %s not available\n", fw_name);
ret = _FAIL;
goto exit;
}
rtfw->data = kmemdup(fw->data, fw->size, GFP_KERNEL);
if (!rtfw->data) {
pr_err("Failed to allocate rtfw->data\n");
ret = _FAIL;
goto exit;
}
rtfw->size = fw->size;
exit:
release_firmware(fw);
return ret;
}
int rtl8188e_firmware_download(struct adapter *padapter)
{
int ret = _SUCCESS;
u8 reg;
unsigned long fwdl_timeout;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct device *device = dvobj_to_dev(dvobj);
struct rt_firmware_hdr *fwhdr = NULL;
u8 *fw_data;
u32 fw_size;
if (!dvobj->firmware.data)
ret = load_firmware(&dvobj->firmware, device);
if (ret == _FAIL) {
dvobj->firmware.data = NULL;
goto exit;
}
fw_data = dvobj->firmware.data;
fw_size = dvobj->firmware.size;
fwhdr = (struct rt_firmware_hdr *)dvobj->firmware.data;
if (IS_FW_HEADER_EXIST(fwhdr)) {
dev_info_once(device, "Firmware Version %d, SubVersion %d, Signature 0x%x\n",
le16_to_cpu(fwhdr->version), fwhdr->subversion,
le16_to_cpu(fwhdr->signature));
fw_data = fw_data + sizeof(struct rt_firmware_hdr);
fw_size = fw_size - sizeof(struct rt_firmware_hdr);
}
/* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */
/* or it will cause download Fw fail. 2010.02.01. by tynli. */
ret = rtw_read8(padapter, REG_MCUFWDL, &reg);
if (ret) {
ret = _FAIL;
goto exit;
}
if (reg & RAM_DL_SEL) { /* 8051 RAM code */
rtw_write8(padapter, REG_MCUFWDL, 0x00);
rtw_reset_8051(padapter);
}
fw_download_enable(padapter, true);
fwdl_timeout = jiffies + msecs_to_jiffies(500);
do {
/* reset the FWDL chksum */
ret = rtw_read8(padapter, REG_MCUFWDL, &reg);
if (ret) {
ret = _FAIL;
continue;
}
rtw_write8(padapter, REG_MCUFWDL, reg | FWDL_CHKSUM_RPT);
ret = write_fw(padapter, fw_data, fw_size);
if (ret == _SUCCESS)
break;
} while (!time_after(jiffies, fwdl_timeout));
fw_download_enable(padapter, false);
if (ret != _SUCCESS)
goto exit;
ret = fw_free_to_go(padapter);
if (ret != _SUCCESS)
goto exit;
exit:
return ret;
}

1150
drivers/staging/r8188eu/core/rtw_ieee80211.c
View File

File diff suppressed because it is too large Load Diff

479
drivers/staging/r8188eu/core/rtw_ioctl_set.c
View File

@ -1,479 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#define _RTW_IOCTL_SET_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtw_ioctl_set.h"
#include "../include/hal_intf.h"
#include "../include/usb_osintf.h"
#include "../include/usb_ops.h"
u8 rtw_do_join(struct adapter *padapter)
{
struct list_head *plist, *phead;
u8 *pibss = NULL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct __queue *queue = &pmlmepriv->scanned_queue;
u8 ret = _SUCCESS;
spin_lock_bh(&pmlmepriv->scanned_queue.lock);
phead = get_list_head(queue);
plist = phead->next;
pmlmepriv->cur_network.join_res = -2;
set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
pmlmepriv->pscanned = plist;
pmlmepriv->to_join = true;
if (list_empty(&queue->queue)) {
spin_unlock_bh(&pmlmepriv->scanned_queue.lock);
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */
/* we try to issue sitesurvey firstly */
if (!pmlmepriv->LinkDetectInfo.bBusyTraffic ||
pmlmepriv->to_roaming > 0) {
/* submit site_survey_cmd */
ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1);
if (ret != _SUCCESS)
pmlmepriv->to_join = false;
} else {
pmlmepriv->to_join = false;
ret = _FAIL;
}
return ret;
} else {
int select_ret;
spin_unlock_bh(&pmlmepriv->scanned_queue.lock);
select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
if (select_ret == _SUCCESS) {
pmlmepriv->to_join = false;
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
} else {
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
/* submit createbss_cmd to change to a ADHOC_MASTER */
/* pmlmepriv->lock has been acquired by caller... */
struct wlan_bssid_ex *pdev_network = &padapter->registrypriv.dev_network;
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
pibss = padapter->registrypriv.dev_network.MacAddress;
memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(struct ndis_802_11_ssid));
rtw_update_registrypriv_dev_network(padapter);
rtw_generate_random_ibss(pibss);
if (rtw_createbss_cmd(padapter) != _SUCCESS)
return false;
pmlmepriv->to_join = false;
} else {
/* can't associate ; reset under-linking */
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */
/* we try to issue sitesurvey firstly */
if (!pmlmepriv->LinkDetectInfo.bBusyTraffic ||
pmlmepriv->to_roaming > 0) {
ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1);
if (ret != _SUCCESS)
pmlmepriv->to_join = false;
} else {
ret = _FAIL;
pmlmepriv->to_join = false;
}
}
}
}
return ret;
}
u8 rtw_set_802_11_bssid(struct adapter *padapter, u8 *bssid)
{
u8 status = _SUCCESS;
u32 cur_time = 0;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 &&
bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) ||
(bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF &&
bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) {
status = _FAIL;
goto exit;
}
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
goto handle_tkip_countermeasure;
else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
goto release_mlme_lock;
if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE)) {
if (!memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN)) {
if (!check_fwstate(pmlmepriv, WIFI_STATION_STATE))
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
} else {
rtw_disassoc_cmd(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED))
rtw_indicate_disconnect(padapter);
rtw_free_assoc_resources(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
}
}
handle_tkip_countermeasure:
/* should we add something here...? */
if (padapter->securitypriv.btkip_countermeasure) {
cur_time = jiffies;
if ((cur_time - padapter->securitypriv.btkip_countermeasure_time) > 60 * HZ) {
padapter->securitypriv.btkip_countermeasure = false;
padapter->securitypriv.btkip_countermeasure_time = 0;
} else {
status = _FAIL;
goto release_mlme_lock;
}
}
memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
pmlmepriv->assoc_by_bssid = true;
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
pmlmepriv->to_join = true;
else
status = rtw_do_join(padapter);
release_mlme_lock:
spin_unlock_bh(&pmlmepriv->lock);
exit:
return status;
}
u8 rtw_set_802_11_ssid(struct adapter *padapter, struct ndis_802_11_ssid *ssid)
{
u8 status = _SUCCESS;
u32 cur_time = 0;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *pnetwork = &pmlmepriv->cur_network;
if (!padapter->hw_init_completed) {
status = _FAIL;
goto exit;
}
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
goto handle_tkip_countermeasure;
} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {
goto release_mlme_lock;
}
if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE)) {
if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
(!memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength))) {
if (!check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
if (!rtw_is_same_ibss(padapter, pnetwork)) {
/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
rtw_disassoc_cmd(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED))
rtw_indicate_disconnect(padapter);
rtw_free_assoc_resources(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
} else {
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
}
} else {
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1);
}
} else {
rtw_disassoc_cmd(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED))
rtw_indicate_disconnect(padapter);
rtw_free_assoc_resources(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
}
}
handle_tkip_countermeasure:
if (padapter->securitypriv.btkip_countermeasure) {
cur_time = jiffies;
if ((cur_time - padapter->securitypriv.btkip_countermeasure_time) > 60 * HZ) {
padapter->securitypriv.btkip_countermeasure = false;
padapter->securitypriv.btkip_countermeasure_time = 0;
} else {
status = _FAIL;
goto release_mlme_lock;
}
}
memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(struct ndis_802_11_ssid));
pmlmepriv->assoc_by_bssid = false;
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
pmlmepriv->to_join = true;
} else {
status = rtw_do_join(padapter);
}
release_mlme_lock:
spin_unlock_bh(&pmlmepriv->lock);
exit:
return status;
}
u8 rtw_set_802_11_infrastructure_mode(struct adapter *padapter,
enum ndis_802_11_network_infra networktype)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *cur_network = &pmlmepriv->cur_network;
enum ndis_802_11_network_infra *pold_state = &cur_network->network.InfrastructureMode;
if (*pold_state != networktype) {
spin_lock_bh(&pmlmepriv->lock);
if (*pold_state == Ndis802_11APMode) {
/* change to other mode from Ndis802_11APMode */
cur_network->join_res = -1;
stop_ap_mode(padapter);
}
if ((check_fwstate(pmlmepriv, _FW_LINKED)) ||
(*pold_state == Ndis802_11IBSS))
rtw_disassoc_cmd(padapter, 0, true);
if ((check_fwstate(pmlmepriv, _FW_LINKED)) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
rtw_free_assoc_resources(padapter, 1);
if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {
if (check_fwstate(pmlmepriv, _FW_LINKED))
rtw_indicate_disconnect(padapter); /* will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not */
}
*pold_state = networktype;
_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
switch (networktype) {
case Ndis802_11IBSS:
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
break;
case Ndis802_11Infrastructure:
set_fwstate(pmlmepriv, WIFI_STATION_STATE);
break;
case Ndis802_11APMode:
set_fwstate(pmlmepriv, WIFI_AP_STATE);
break;
case Ndis802_11AutoUnknown:
case Ndis802_11InfrastructureMax:
break;
}
spin_unlock_bh(&pmlmepriv->lock);
}
return true;
}
void rtw_set_802_11_disassociate(struct adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
rtw_disassoc_cmd(padapter, 0, true);
rtw_indicate_disconnect(padapter);
rtw_free_assoc_resources(padapter, 1);
rtw_pwr_wakeup(padapter);
}
spin_unlock_bh(&pmlmepriv->lock);
}
u8 rtw_set_802_11_bssid_list_scan(struct adapter *padapter, struct ndis_802_11_ssid *pssid, int ssid_max_num)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 res = true;
if (!padapter) {
res = false;
goto exit;
}
if (!padapter->hw_init_completed) {
res = false;
goto exit;
}
if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING)) ||
(pmlmepriv->LinkDetectInfo.bBusyTraffic)) {
/* Scan or linking is in progress, do nothing. */
res = true;
} else {
spin_lock_bh(&pmlmepriv->lock);
res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num);
spin_unlock_bh(&pmlmepriv->lock);
}
exit:
return res;
}
u8 rtw_set_802_11_authentication_mode(struct adapter *padapter, enum ndis_802_11_auth_mode authmode)
{
struct security_priv *psecuritypriv = &padapter->securitypriv;
int res;
u8 ret;
psecuritypriv->ndisauthtype = authmode;
if (psecuritypriv->ndisauthtype > 3)
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
res = rtw_set_auth(padapter, psecuritypriv);
if (res == _SUCCESS)
ret = true;
else
ret = false;
return ret;
}
u8 rtw_set_802_11_add_wep(struct adapter *padapter, struct ndis_802_11_wep *wep)
{
int keyid, res;
struct security_priv *psecuritypriv = &padapter->securitypriv;
u8 ret = _SUCCESS;
keyid = wep->KeyIndex & 0x3fffffff;
if (keyid >= 4) {
ret = false;
goto exit;
}
switch (wep->KeyLength) {
case 5:
psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
break;
case 13:
psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
break;
default:
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
break;
}
memcpy(&psecuritypriv->dot11DefKey[keyid].skey[0], &wep->KeyMaterial, wep->KeyLength);
psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;
psecuritypriv->dot11PrivacyKeyIndex = keyid;
res = rtw_set_key(padapter, psecuritypriv, keyid, 1);
if (res == _FAIL)
ret = false;
exit:
return ret;
}
/*
* rtw_get_cur_max_rate -
* @adapter: pointer to struct adapter structure
*
* Return 0 or 100Kbps
*/
u16 rtw_get_cur_max_rate(struct adapter *adapter)
{
int i = 0;
u8 *p;
u16 rate = 0, max_rate = 0;
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct registry_priv *pregistrypriv = &adapter->registrypriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network;
struct ieee80211_ht_cap *pht_capie;
u8 bw_40MHz = 0, short_GI_20 = 0, short_GI_40 = 0;
u16 mcs_rate = 0;
u32 ht_ielen = 0;
if ((!check_fwstate(pmlmepriv, _FW_LINKED)) &&
(!check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
return 0;
if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N)) {
p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12);
if (p && ht_ielen > 0) {
pht_capie = (struct ieee80211_ht_cap *)(p + 2);
memcpy(&mcs_rate, pht_capie->mcs.rx_mask, 2);
/* cur_bwmod is updated by beacon, pmlmeinfo is updated by association response */
bw_40MHz = (pmlmeext->cur_bwmode && (HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH & pmlmeinfo->HT_info.infos[0])) ? 1 : 0;
short_GI_20 = (le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info) & IEEE80211_HT_CAP_SGI_20) ? 1 : 0;
short_GI_40 = (le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info) & IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
max_rate = rtw_mcs_rate(bw_40MHz & (pregistrypriv->cbw40_enable),
short_GI_20,
short_GI_40,
pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate);
}
} else {
while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) {
rate = pcur_bss->SupportedRates[i] & 0x7F;
if (rate > max_rate)
max_rate = rate;
i++;
}
max_rate *= 5;
}
return max_rate;
}

160
drivers/staging/r8188eu/core/rtw_iol.c
View File

@ -1,160 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/rtw_iol.h"
struct xmit_frame *rtw_IOL_accquire_xmit_frame(struct adapter *adapter)
{
struct xmit_frame *xmit_frame;
struct xmit_buf *xmitbuf;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv = &adapter->xmitpriv;
xmit_frame = rtw_alloc_xmitframe(pxmitpriv);
if (!xmit_frame)
return NULL;
xmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (!xmitbuf) {
rtw_free_xmitframe(pxmitpriv, xmit_frame);
return NULL;
}
xmit_frame->frame_tag = MGNT_FRAMETAG;
xmit_frame->pxmitbuf = xmitbuf;
xmit_frame->buf_addr = xmitbuf->pbuf;
xmitbuf->priv_data = xmit_frame;
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = 0x10;/* Beacon */
pattrib->subtype = WIFI_BEACON;
pattrib->pktlen = 0;
pattrib->last_txcmdsz = 0;
return xmit_frame;
}
int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
{
struct pkt_attrib *pattrib = &xmit_frame->attrib;
u16 buf_offset;
u32 ori_len;
buf_offset = TXDESC_OFFSET;
ori_len = buf_offset + pattrib->pktlen;
/* check if the io_buf can accommodate new cmds */
if (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ)
return _FAIL;
memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
pattrib->pktlen += cmd_len;
pattrib->last_txcmdsz += cmd_len;
return _SUCCESS;
}
bool rtw_IOL_applied(struct adapter *adapter)
{
if (adapter->registrypriv.fw_iol == 1)
return true;
if ((adapter->registrypriv.fw_iol == 2) &&
(adapter_to_dvobj(adapter)->pusbdev->speed != USB_SPEED_HIGH))
return true;
return false;
}
int rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)
{
struct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0};
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if (mask != 0xFF) {
cmd.length = 12;
cmd.mask = cpu_to_le32(mask);
}
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
}
int rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)
{
struct ioreg_cfg cmd = {8, IOREG_CMD_WW_REG, 0x0, 0x0, 0x0};
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if (mask != 0xFFFF) {
cmd.length = 12;
cmd.mask = cpu_to_le32(mask);
}
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
}
int rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
{
struct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0};
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if (mask != 0xFFFFFFFF) {
cmd.length = 12;
cmd.mask = cpu_to_le32(mask);
}
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
}
int rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
{
struct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0};
cmd.address = cpu_to_le16((rf_path << 8) | ((addr) & 0xFF));
cmd.data = cpu_to_le32(value);
if (mask != 0x000FFFFF) {
cmd.length = 12;
cmd.mask = cpu_to_le32(mask);
}
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
}
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
{
struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
cmd.address = cpu_to_le16(us);
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
}
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
{
struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
cmd.address = cpu_to_le16(ms);
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
}
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
{
struct ioreg_cfg cmd = {4, IOREG_CMD_END, cpu_to_le16(0xFFFF), cpu_to_le32(0xFF), 0x0};
return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
}
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
{
u8 is_cmd_bndy = false;
if (((pxmit_frame->attrib.pktlen + 32) % 256) + 8 >= 256) {
rtw_IOL_append_END_cmd(pxmit_frame);
pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen + 32) / 256) + 1) * 256);
pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
is_cmd_bndy = true;
}
return is_cmd_bndy;
}

255
drivers/staging/r8188eu/core/rtw_led.c
View File

@ -1,255 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#include "../include/drv_types.h"
#include "../include/rtw_led.h"
#include "../include/rtl8188e_spec.h"
#define LED_BLINK_NO_LINK_INTVL msecs_to_jiffies(1000)
#define LED_BLINK_LINK_INTVL msecs_to_jiffies(500)
#define LED_BLINK_SCAN_INTVL msecs_to_jiffies(180)
#define LED_BLINK_FASTER_INTVL msecs_to_jiffies(50)
#define LED_BLINK_WPS_SUCESS_INTVL msecs_to_jiffies(5000)
#define IS_LED_WPS_BLINKING(l) \
((l)->CurrLedState == LED_BLINK_WPS || \
(l)->CurrLedState == LED_BLINK_WPS_STOP || \
(l)->bLedWPSBlinkInProgress)
static void ResetLedStatus(struct led_priv *pLed)
{
pLed->CurrLedState = RTW_LED_OFF; /* Current LED state. */
pLed->bLedOn = false; /* true if LED is ON, false if LED is OFF. */
pLed->bLedBlinkInProgress = false; /* true if it is blinking, false o.w.. */
pLed->bLedWPSBlinkInProgress = false;
pLed->BlinkTimes = 0; /* Number of times to toggle led state for blinking. */
pLed->bLedScanBlinkInProgress = false;
}
static void SwLedOn(struct led_priv *pLed)
{
struct adapter *padapter = container_of(pLed, struct adapter, ledpriv);
if (padapter->bDriverStopped)
return;
if (rtw_write8(padapter, REG_LEDCFG2, BIT(5)) != _SUCCESS)
return;
pLed->bLedOn = true;
}
static void SwLedOff(struct led_priv *pLed)
{
struct adapter *padapter = container_of(pLed, struct adapter, ledpriv);
if (padapter->bDriverStopped)
return;
if (rtw_write8(padapter, REG_LEDCFG2, BIT(5) | BIT(3)) != _SUCCESS)
return;
pLed->bLedOn = false;
}
static void blink_work(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct led_priv *pLed = container_of(dwork, struct led_priv, blink_work);
struct adapter *padapter = container_of(pLed, struct adapter, ledpriv);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if (padapter->pwrctrlpriv.rf_pwrstate != rf_on) {
SwLedOff(pLed);
ResetLedStatus(pLed);
return;
}
if (pLed->bLedOn)
SwLedOff(pLed);
else
SwLedOn(pLed);
switch (pLed->CurrLedState) {
case LED_BLINK_SLOWLY:
schedule_delayed_work(&pLed->blink_work, LED_BLINK_NO_LINK_INTVL);
break;
case LED_BLINK_NORMAL:
schedule_delayed_work(&pLed->blink_work, LED_BLINK_LINK_INTVL);
break;
case LED_BLINK_SCAN:
case LED_BLINK_TXRX:
pLed->BlinkTimes--;
if (pLed->BlinkTimes == 0) {
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
pLed->CurrLedState = LED_BLINK_NORMAL;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_LINK_INTVL);
} else {
pLed->CurrLedState = LED_BLINK_SLOWLY;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_NO_LINK_INTVL);
}
pLed->bLedBlinkInProgress = false;
pLed->bLedScanBlinkInProgress = false;
} else {
schedule_delayed_work(&pLed->blink_work,
pLed->CurrLedState == LED_BLINK_SCAN ?
LED_BLINK_SCAN_INTVL : LED_BLINK_FASTER_INTVL);
}
break;
case LED_BLINK_WPS:
schedule_delayed_work(&pLed->blink_work, LED_BLINK_SCAN_INTVL);
break;
case LED_BLINK_WPS_STOP: /* WPS success */
if (!pLed->bLedOn) {
pLed->CurrLedState = LED_BLINK_NORMAL;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_LINK_INTVL);
pLed->bLedWPSBlinkInProgress = false;
} else {
schedule_delayed_work(&pLed->blink_work, LED_BLINK_WPS_SUCESS_INTVL);
}
break;
default:
break;
}
}
void rtl8188eu_InitSwLeds(struct adapter *padapter)
{
struct led_priv *pledpriv = &padapter->ledpriv;
ResetLedStatus(pledpriv);
INIT_DELAYED_WORK(&pledpriv->blink_work, blink_work);
}
void rtl8188eu_DeInitSwLeds(struct adapter *padapter)
{
struct led_priv *ledpriv = &padapter->ledpriv;
cancel_delayed_work_sync(&ledpriv->blink_work);
ResetLedStatus(ledpriv);
SwLedOff(ledpriv);
}
void rtw_led_control(struct adapter *padapter, enum LED_CTL_MODE LedAction)
{
struct led_priv *pLed = &padapter->ledpriv;
struct registry_priv *registry_par;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if (!padapter->hw_init_completed)
return;
if (!pLed->bRegUseLed)
return;
registry_par = &padapter->registrypriv;
if (!registry_par->led_enable)
return;
switch (LedAction) {
case LED_CTL_START_TO_LINK:
case LED_CTL_NO_LINK:
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
return;
cancel_delayed_work(&pLed->blink_work);
pLed->bLedBlinkInProgress = false;
pLed->CurrLedState = LED_BLINK_SLOWLY;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_NO_LINK_INTVL);
break;
case LED_CTL_LINK:
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
return;
cancel_delayed_work(&pLed->blink_work);
pLed->bLedBlinkInProgress = false;
pLed->CurrLedState = LED_BLINK_NORMAL;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_LINK_INTVL);
break;
case LED_CTL_SITE_SURVEY:
if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)))
return;
if (pLed->bLedScanBlinkInProgress)
return;
if (IS_LED_WPS_BLINKING(pLed))
return;
cancel_delayed_work(&pLed->blink_work);
pLed->bLedBlinkInProgress = false;
pLed->bLedScanBlinkInProgress = true;
pLed->CurrLedState = LED_BLINK_SCAN;
pLed->BlinkTimes = 24;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_SCAN_INTVL);
break;
case LED_CTL_TX:
case LED_CTL_RX:
if (pLed->bLedBlinkInProgress)
return;
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
return;
cancel_delayed_work(&pLed->blink_work);
pLed->bLedBlinkInProgress = true;
pLed->CurrLedState = LED_BLINK_TXRX;
pLed->BlinkTimes = 2;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_FASTER_INTVL);
break;
case LED_CTL_START_WPS: /* wait until xinpin finish */
if (pLed->bLedWPSBlinkInProgress)
return;
cancel_delayed_work(&pLed->blink_work);
pLed->bLedBlinkInProgress = false;
pLed->bLedScanBlinkInProgress = false;
pLed->bLedWPSBlinkInProgress = true;
pLed->CurrLedState = LED_BLINK_WPS;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_SCAN_INTVL);
break;
case LED_CTL_STOP_WPS:
cancel_delayed_work(&pLed->blink_work);
pLed->bLedBlinkInProgress = false;
pLed->bLedScanBlinkInProgress = false;
pLed->bLedWPSBlinkInProgress = true;
pLed->CurrLedState = LED_BLINK_WPS_STOP;
if (pLed->bLedOn) {
schedule_delayed_work(&pLed->blink_work, LED_BLINK_WPS_SUCESS_INTVL);
} else {
schedule_delayed_work(&pLed->blink_work, 0);
}
break;
case LED_CTL_STOP_WPS_FAIL:
cancel_delayed_work(&pLed->blink_work);
pLed->bLedWPSBlinkInProgress = false;
pLed->CurrLedState = LED_BLINK_SLOWLY;
schedule_delayed_work(&pLed->blink_work, LED_BLINK_NO_LINK_INTVL);
break;
case LED_CTL_POWER_OFF:
pLed->CurrLedState = RTW_LED_OFF;
pLed->bLedBlinkInProgress = false;
pLed->bLedWPSBlinkInProgress = false;
pLed->bLedScanBlinkInProgress = false;
cancel_delayed_work(&pLed->blink_work);
SwLedOff(pLed);
break;
default:
break;
}
}

2067
drivers/staging/r8188eu/core/rtw_mlme.c
View File

File diff suppressed because it is too large Load Diff

7817
drivers/staging/r8188eu/core/rtw_mlme_ext.c
View File

File diff suppressed because it is too large Load Diff

1918
drivers/staging/r8188eu/core/rtw_p2p.c
View File

File diff suppressed because it is too large Load Diff

445
drivers/staging/r8188eu/core/rtw_pwrctrl.c
View File

@ -1,445 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#define _RTW_PWRCTRL_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/osdep_intf.h"
#include "../include/linux/usb.h"
static void ips_enter(struct adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct xmit_priv *pxmit_priv = &padapter->xmitpriv;
if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||
pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF)
return;
mutex_lock(&pwrpriv->lock);
pwrpriv->bips_processing = true;
/* syn ips_mode with request */
pwrpriv->ips_mode = pwrpriv->ips_mode_req;
pwrpriv->ips_enter_cnts++;
pwrpriv->bpower_saving = true;
if (pwrpriv->ips_mode == IPS_LEVEL_2)
pwrpriv->bkeepfwalive = true;
rtw_ips_pwr_down(padapter);
pwrpriv->rf_pwrstate = rf_off;
pwrpriv->bips_processing = false;
mutex_unlock(&pwrpriv->lock);
}
static int ips_leave(struct adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
int result = _SUCCESS;
int keyid;
mutex_lock(&pwrpriv->lock);
if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) {
pwrpriv->bips_processing = true;
pwrpriv->ips_leave_cnts++;
result = rtw_ips_pwr_up(padapter);
if (result == _SUCCESS) {
pwrpriv->rf_pwrstate = rf_on;
}
if ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_)) {
set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
for (keyid = 0; keyid < 4; keyid++) {
if (pmlmepriv->key_mask & BIT(keyid)) {
if (keyid == psecuritypriv->dot11PrivacyKeyIndex)
result = rtw_set_key(padapter, psecuritypriv, keyid, 1);
else
result = rtw_set_key(padapter, psecuritypriv, keyid, 0);
}
}
}
pwrpriv->bips_processing = false;
pwrpriv->bkeepfwalive = false;
pwrpriv->bpower_saving = false;
}
mutex_unlock(&pwrpriv->lock);
return result;
}
static bool rtw_pwr_unassociated_idle(struct adapter *adapter)
{
struct adapter *buddy = adapter->pbuddy_adapter;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct wifidirect_info *pwdinfo = &adapter->wdinfo;
bool ret = false;
if (time_after_eq(adapter->pwrctrlpriv.ips_deny_time, jiffies))
goto exit;
if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR) ||
check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) ||
check_fwstate(pmlmepriv, WIFI_UNDER_WPS) ||
check_fwstate(pmlmepriv, WIFI_AP_STATE) ||
check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) ||
!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
goto exit;
/* consider buddy, if exist */
if (buddy) {
struct mlme_priv *b_pmlmepriv = &buddy->mlmepriv;
struct wifidirect_info *b_pwdinfo = &buddy->wdinfo;
if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR) ||
check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) ||
check_fwstate(b_pmlmepriv, WIFI_AP_STATE) ||
check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) ||
!rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE))
goto exit;
}
ret = true;
exit:
return ret;
}
void rtw_ps_processor(struct adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
pwrpriv->ps_processing = true;
if (pwrpriv->bips_processing)
goto exit;
if (pwrpriv->ips_mode_req == IPS_NONE)
goto exit;
if (!rtw_pwr_unassociated_idle(padapter))
goto exit;
if (pwrpriv->rf_pwrstate == rf_on)
ips_enter(padapter);
exit:
rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
pwrpriv->ps_processing = false;
}
static void pwr_state_check_handler(struct timer_list *t)
{
struct adapter *padapter =
from_timer(padapter, t,
pwrctrlpriv.pwr_state_check_timer);
rtw_ps_cmd(padapter);
}
static bool PS_RDY_CHECK(struct adapter *padapter)
{
u32 curr_time, delta_time;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
curr_time = jiffies;
delta_time = curr_time - pwrpriv->DelayLPSLastTimeStamp;
if (delta_time < LPS_DELAY_TIME)
return false;
if (!check_fwstate(pmlmepriv, _FW_LINKED) ||
check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) ||
check_fwstate(pmlmepriv, WIFI_AP_STATE) ||
check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ||
check_fwstate(pmlmepriv, WIFI_ADHOC_STATE))
return false;
if (pwrpriv->bInSuspend)
return false;
if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X &&
!padapter->securitypriv.binstallGrpkey)
return false;
return true;
}
void rtw_set_firmware_ps_mode(struct adapter *adapter, u8 mode)
{
struct hal_data_8188e *haldata = &adapter->haldata;
struct odm_dm_struct *odmpriv = &haldata->odmpriv;
/* Force leave RF low power mode for 1T1R to prevent
* conflicting setting in firmware power saving sequence.
*/
if (mode != PS_MODE_ACTIVE)
ODM_RF_Saving(odmpriv, true);
rtl8188e_set_FwPwrMode_cmd(adapter, mode);
}
void rtw_set_ps_mode(struct adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
if (ps_mode > PM_Card_Disable)
return;
if (pwrpriv->pwr_mode == ps_mode) {
if (ps_mode == PS_MODE_ACTIVE)
return;
if ((pwrpriv->smart_ps == smart_ps) &&
(pwrpriv->bcn_ant_mode == bcn_ant_mode))
return;
}
if (ps_mode == PS_MODE_ACTIVE) {
if (pwdinfo->opp_ps == 0) {
pwrpriv->pwr_mode = ps_mode;
rtw_set_firmware_ps_mode(padapter, ps_mode);
pwrpriv->bFwCurrentInPSMode = false;
}
} else {
if (PS_RDY_CHECK(padapter)) {
pwrpriv->bFwCurrentInPSMode = true;
pwrpriv->pwr_mode = ps_mode;
pwrpriv->smart_ps = smart_ps;
pwrpriv->bcn_ant_mode = bcn_ant_mode;
rtw_set_firmware_ps_mode(padapter, ps_mode);
/* Set CTWindow after LPS */
if (pwdinfo->opp_ps == 1)
p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0);
}
}
}
static bool lps_rf_on(struct adapter *adapter)
{
int res;
u32 reg;
/* When we halt NIC, we should check if FW LPS is leave. */
if (adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
/* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
/* because Fw is unload. */
return true;
}
res = rtw_read32(adapter, REG_RCR, &reg);
if (res)
return false;
if (reg & 0x00070000)
return false;
return true;
}
/*
* Return:
* 0: Leave OK
* -1: Timeout
* -2: Other error
*/
static s32 LPS_RF_ON_check(struct adapter *padapter, u32 delay_ms)
{
unsigned long timeout = jiffies + msecs_to_jiffies(delay_ms);
s32 err = 0;
while (1) {
if (lps_rf_on(padapter))
break;
if (padapter->bSurpriseRemoved) {
err = -2;
break;
}
if (time_after(jiffies, timeout)) {
err = -1;
break;
}
mdelay(1);
}
return err;
}
/* */
/* Description: */
/* Enter the leisure power save mode. */
/* */
void LPS_Enter(struct adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
if (!PS_RDY_CHECK(padapter))
return;
if (pwrpriv->bLeisurePs) {
/* Idle for a while if we connect to AP a while ago. */
if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
pwrpriv->bpower_saving = true;
/* For Tenda W311R IOT issue */
rtw_set_ps_mode(padapter, pwrpriv->power_mgnt,
pwrpriv->smart_ps, 0x40);
}
} else {
pwrpriv->LpsIdleCount++;
}
}
}
#define LPS_LEAVE_TIMEOUT_MS 100
/* Description: */
/* Leave the leisure power save mode. */
void LPS_Leave(struct adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
if (pwrpriv->bLeisurePs) {
if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0x40);
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS);
}
}
pwrpriv->bpower_saving = false;
}
/* */
/* Description: Leave all power save mode: LPS, FwLPS, IPS if needed. */
/* Move code to function by tynli. 2010.03.26. */
/* */
void LeaveAllPowerSaveMode(struct adapter *Adapter)
{
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
u8 enqueue = 0;
if (check_fwstate(pmlmepriv, _FW_LINKED)) { /* connect */
p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue);
rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue);
}
}
void rtw_init_pwrctrl_priv(struct adapter *padapter)
{
struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
mutex_init(&pwrctrlpriv->lock);
pwrctrlpriv->rf_pwrstate = rf_on;
pwrctrlpriv->ips_enter_cnts = 0;
pwrctrlpriv->ips_leave_cnts = 0;
pwrctrlpriv->bips_processing = false;
pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
pwrctrlpriv->bInSuspend = false;
pwrctrlpriv->bkeepfwalive = false;
pwrctrlpriv->LpsIdleCount = 0;
pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt;/* PS_MODE_MIN; */
pwrctrlpriv->bLeisurePs = pwrctrlpriv->power_mgnt != PS_MODE_ACTIVE;
pwrctrlpriv->bFwCurrentInPSMode = false;
pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;
pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps;
pwrctrlpriv->bcn_ant_mode = 0;
timer_setup(&pwrctrlpriv->pwr_state_check_timer, pwr_state_check_handler, 0);
}
/* Wake the NIC up from: 1)IPS 2)USB autosuspend */
int rtw_pwr_wakeup(struct adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
unsigned long timeout = jiffies + msecs_to_jiffies(3000);
unsigned long deny_time;
int ret;
while (pwrpriv->ps_processing && time_before(jiffies, timeout))
msleep(10);
/* I think this should be check in IPS, LPS, autosuspend functions... */
/* Below goto is a success path taken for already linked devices */
ret = 0;
if (check_fwstate(pmlmepriv, _FW_LINKED))
goto exit;
if (pwrpriv->rf_pwrstate == rf_off && ips_leave(padapter) == _FAIL) {
ret = -ENOMEM;
goto exit;
}
if (padapter->bDriverStopped || !padapter->bup || !padapter->hw_init_completed) {
ret = -EBUSY;
goto exit;
}
exit:
deny_time = jiffies + msecs_to_jiffies(RTW_PWR_STATE_CHK_INTERVAL);
if (time_before(pwrpriv->ips_deny_time, deny_time))
pwrpriv->ips_deny_time = deny_time;
return ret;
}
int rtw_pm_set_lps(struct adapter *padapter, u8 mode)
{
int ret = 0;
struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
if (mode < PS_MODE_NUM) {
if (pwrctrlpriv->power_mgnt != mode) {
if (mode == PS_MODE_ACTIVE)
LeaveAllPowerSaveMode(padapter);
else
pwrctrlpriv->LpsIdleCount = 2;
pwrctrlpriv->power_mgnt = mode;
pwrctrlpriv->bLeisurePs = pwrctrlpriv->power_mgnt != PS_MODE_ACTIVE;
}
} else {
ret = -EINVAL;
}
return ret;
}
int rtw_pm_set_ips(struct adapter *padapter, u8 mode)
{
struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
if (mode == IPS_NORMAL || mode == IPS_LEVEL_2) {
rtw_ips_mode_req(pwrctrlpriv, mode);
return 0;
} else if (mode == IPS_NONE) {
rtw_ips_mode_req(pwrctrlpriv, mode);
if ((padapter->bSurpriseRemoved == 0) && rtw_pwr_wakeup(padapter))
return -EFAULT;
} else {
return -EINVAL;
}
return 0;
}

2010
drivers/staging/r8188eu/core/rtw_recv.c
View File

File diff suppressed because it is too large Load Diff

29
drivers/staging/r8188eu/core/rtw_rf.c
View File

@ -1,29 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/drv_types.h"
static const u32 ch_freq_map[] = {
2412,
2417,
2422,
2427,
2432,
2437,
2442,
2447,
2452,
2457,
2462,
2467,
2472,
2484
};
u32 rtw_ch2freq(u32 channel)
{
if (channel == 0 || channel > ARRAY_SIZE(ch_freq_map))
return 2412;
return ch_freq_map[channel - 1];
}

1374
drivers/staging/r8188eu/core/rtw_security.c
View File

File diff suppressed because it is too large Load Diff

490
drivers/staging/r8188eu/core/rtw_sta_mgt.c
View File

@ -1,490 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _RTW_STA_MGT_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/sta_info.h"
static void _rtw_init_stainfo(struct sta_info *psta)
{
memset((u8 *)psta, 0, sizeof(struct sta_info));
spin_lock_init(&psta->lock);
INIT_LIST_HEAD(&psta->list);
INIT_LIST_HEAD(&psta->hash_list);
rtw_init_queue(&psta->sleep_q);
psta->sleepq_len = 0;
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
INIT_LIST_HEAD(&psta->asoc_list);
INIT_LIST_HEAD(&psta->auth_list);
psta->expire_to = 0;
psta->flags = 0;
psta->capability = 0;
psta->bpairwise_key_installed = false;
psta->nonerp_set = 0;
psta->no_short_slot_time_set = 0;
psta->no_short_preamble_set = 0;
psta->no_ht_gf_set = 0;
psta->no_ht_set = 0;
psta->ht_20mhz_set = 0;
psta->under_exist_checking = 0;
psta->keep_alive_trycnt = 0;
}
int _rtw_init_sta_priv(struct sta_priv *pstapriv)
{
struct sta_info *psta;
s32 i;
pstapriv->pallocated_stainfo_buf = vzalloc(sizeof(struct sta_info) * NUM_STA + 4);
if (!pstapriv->pallocated_stainfo_buf)
return -ENOMEM;
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((size_t)(pstapriv->pallocated_stainfo_buf) & 3);
rtw_init_queue(&pstapriv->free_sta_queue);
spin_lock_init(&pstapriv->sta_hash_lock);
pstapriv->asoc_sta_count = 0;
rtw_init_queue(&pstapriv->sleep_q);
rtw_init_queue(&pstapriv->wakeup_q);
psta = (struct sta_info *)(pstapriv->pstainfo_buf);
for (i = 0; i < NUM_STA; i++) {
_rtw_init_stainfo(psta);
INIT_LIST_HEAD(&pstapriv->sta_hash[i]);
list_add_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
psta++;
}
pstapriv->sta_dz_bitmap = 0;
pstapriv->tim_bitmap = 0;
INIT_LIST_HEAD(&pstapriv->asoc_list);
INIT_LIST_HEAD(&pstapriv->auth_list);
spin_lock_init(&pstapriv->asoc_list_lock);
spin_lock_init(&pstapriv->auth_list_lock);
pstapriv->asoc_list_cnt = 0;
pstapriv->auth_list_cnt = 0;
pstapriv->auth_to = 3; /* 3*2 = 6 sec */
pstapriv->assoc_to = 3;
pstapriv->expire_to = 3; /* 3*2 = 6 sec */
pstapriv->max_num_sta = NUM_STA;
return 0;
}
inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
{
return (((u8 *)sta) - stapriv->pstainfo_buf) / sizeof(struct sta_info);
}
inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
{
return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
}
void _rtw_free_sta_priv(struct sta_priv *pstapriv)
{
struct list_head *phead, *plist;
struct sta_info *psta = NULL;
struct recv_reorder_ctrl *preorder_ctrl;
int index;
if (pstapriv) {
/* delete all reordering_ctrl_timer */
spin_lock_bh(&pstapriv->sta_hash_lock);
for (index = 0; index < NUM_STA; index++) {
phead = &pstapriv->sta_hash[index];
plist = phead->next;
while (phead != plist) {
int i;
psta = container_of(plist, struct sta_info, hash_list);
plist = plist->next;
for (i = 0; i < 16; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
}
}
}
spin_unlock_bh(&pstapriv->sta_hash_lock);
/*===============================*/
vfree(pstapriv->pallocated_stainfo_buf);
}
}
static void _rtw_reordering_ctrl_timeout_handler(struct timer_list *t)
{
struct recv_reorder_ctrl *preorder_ctrl;
preorder_ctrl = from_timer(preorder_ctrl, t, reordering_ctrl_timer);
rtw_reordering_ctrl_timeout_handler(preorder_ctrl);
}
static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
{
timer_setup(&preorder_ctrl->reordering_ctrl_timer, _rtw_reordering_ctrl_timeout_handler, 0);
}
static void _addba_timer_hdl(struct timer_list *t)
{
struct sta_info *psta = from_timer(psta, t, addba_retry_timer);
addba_timer_hdl(psta);
}
static void init_addba_retry_timer(struct adapter *padapter, struct sta_info *psta)
{
timer_setup(&psta->addba_retry_timer, _addba_timer_hdl, 0);
}
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
s32 index;
struct list_head *phash_list;
struct sta_info *psta;
struct __queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
int i = 0;
u16 wRxSeqInitialValue = 0xffff;
pfree_sta_queue = &pstapriv->free_sta_queue;
spin_lock_bh(&pfree_sta_queue->lock);
if (list_empty(&pfree_sta_queue->queue)) {
spin_unlock_bh(&pfree_sta_queue->lock);
psta = NULL;
} else {
psta = container_of((&pfree_sta_queue->queue)->next, struct sta_info, list);
list_del_init(&psta->list);
spin_unlock_bh(&pfree_sta_queue->lock);
_rtw_init_stainfo(psta);
memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
index = wifi_mac_hash(hwaddr);
if (index >= NUM_STA) {
psta = NULL;
goto exit;
}
phash_list = &pstapriv->sta_hash[index];
spin_lock_bh(&pstapriv->sta_hash_lock);
list_add_tail(&psta->hash_list, phash_list);
pstapriv->asoc_sta_count++;
spin_unlock_bh(&pstapriv->sta_hash_lock);
/* Commented by Albert 2009/08/13 */
/* For the SMC router, the sequence number of first packet of WPS handshake will be 0. */
/* In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. */
/* So, we initialize the tid_rxseq variable as the 0xffff. */
for (i = 0; i < 16; i++)
memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
init_addba_retry_timer(pstapriv->padapter, psta);
/* for A-MPDU Rx reordering buffer control */
for (i = 0; i < 16; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->padapter = pstapriv->padapter;
preorder_ctrl->enable = false;
preorder_ctrl->indicate_seq = 0xffff;
preorder_ctrl->wend_b = 0xffff;
preorder_ctrl->wsize_b = 64;/* 64; */
rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
rtw_init_recv_timer(preorder_ctrl);
}
/* init for DM */
psta->rssi_stat.UndecoratedSmoothedPWDB = (-1);
psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
/* init for the sequence number of received management frame */
psta->RxMgmtFrameSeqNum = 0xffff;
}
exit:
return psta;
}
/* using pstapriv->sta_hash_lock to protect */
void rtw_free_stainfo(struct adapter *padapter, struct sta_info *psta)
{
int i;
struct __queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
struct sta_xmit_priv *pstaxmitpriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct sta_priv *pstapriv = &padapter->stapriv;
if (!psta)
return;
pfree_sta_queue = &pstapriv->free_sta_queue;
pstaxmitpriv = &psta->sta_xmitpriv;
spin_lock_bh(&pxmitpriv->lock);
rtw_free_xmitframe_list(pxmitpriv, get_list_head(&psta->sleep_q));
psta->sleepq_len = 0;
rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
list_del_init(&pstaxmitpriv->vo_q.tx_pending);
rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
list_del_init(&pstaxmitpriv->vi_q.tx_pending);
rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
list_del_init(&pstaxmitpriv->bk_q.tx_pending);
rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
list_del_init(&pstaxmitpriv->be_q.tx_pending);
spin_unlock_bh(&pxmitpriv->lock);
list_del_init(&psta->hash_list);
pstapriv->asoc_sta_count--;
/* re-init sta_info; 20061114 */
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
_cancel_timer_ex(&psta->addba_retry_timer);
/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
for (i = 0; i < 16 ; i++) {
struct list_head *phead, *plist;
struct recv_frame *prframe;
struct __queue *ppending_recvframe_queue;
struct __queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
spin_lock_bh(&ppending_recvframe_queue->lock);
phead = get_list_head(ppending_recvframe_queue);
plist = phead->next;
while (!list_empty(phead)) {
prframe = container_of(plist, struct recv_frame, list);
plist = plist->next;
list_del_init(&prframe->list);
rtw_free_recvframe(prframe, pfree_recv_queue);
}
spin_unlock_bh(&ppending_recvframe_queue->lock);
}
if (!(psta->state & WIFI_AP_STATE))
rtl8188e_SetHalODMVar(padapter, psta, false);
spin_lock_bh(&pstapriv->auth_list_lock);
if (!list_empty(&psta->auth_list)) {
list_del_init(&psta->auth_list);
pstapriv->auth_list_cnt--;
}
spin_unlock_bh(&pstapriv->auth_list_lock);
psta->expire_to = 0;
psta->sleepq_ac_len = 0;
psta->qos_info = 0;
psta->max_sp_len = 0;
psta->uapsd_bk = 0;
psta->uapsd_be = 0;
psta->uapsd_vi = 0;
psta->uapsd_vo = 0;
psta->has_legacy_ac = 0;
pstapriv->sta_dz_bitmap &= ~BIT(psta->aid);
pstapriv->tim_bitmap &= ~BIT(psta->aid);
if ((psta->aid > 0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) {
pstapriv->sta_aid[psta->aid - 1] = NULL;
psta->aid = 0;
}
psta->under_exist_checking = 0;
spin_lock_bh(&pfree_sta_queue->lock);
list_add_tail(&psta->list, get_list_head(pfree_sta_queue));
spin_unlock_bh(&pfree_sta_queue->lock);
}
/* free all stainfo which in sta_hash[all] */
void rtw_free_all_stainfo(struct adapter *padapter)
{
struct list_head *plist, *phead;
s32 index;
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter);
if (pstapriv->asoc_sta_count == 1)
return;
spin_lock_bh(&pstapriv->sta_hash_lock);
for (index = 0; index < NUM_STA; index++) {
phead = &pstapriv->sta_hash[index];
plist = phead->next;
while (phead != plist) {
psta = container_of(plist, struct sta_info, hash_list);
plist = plist->next;
if (pbcmc_stainfo != psta)
rtw_free_stainfo(padapter, psta);
}
}
spin_unlock_bh(&pstapriv->sta_hash_lock);
}
/* any station allocated can be searched by hash list */
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
struct sta_info *ploop, *psta = NULL;
u32 index;
u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
if (!hwaddr)
return NULL;
if (is_multicast_ether_addr(hwaddr))
addr = bc_addr;
else
addr = hwaddr;
index = wifi_mac_hash(addr);
spin_lock_bh(&pstapriv->sta_hash_lock);
list_for_each_entry(ploop, &pstapriv->sta_hash[index], hash_list) {
if (!memcmp(ploop->hwaddr, addr, ETH_ALEN)) {
psta = ploop;
break;
}
}
spin_unlock_bh(&pstapriv->sta_hash_lock);
return psta;
}
u32 rtw_init_bcmc_stainfo(struct adapter *padapter)
{
struct sta_info *psta;
u32 res = _SUCCESS;
unsigned char bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
struct sta_priv *pstapriv = &padapter->stapriv;
psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
if (!psta) {
res = _FAIL;
goto exit;
}
/* default broadcast & multicast use macid 1 */
psta->mac_id = 1;
exit:
return res;
}
struct sta_info *rtw_get_bcmc_stainfo(struct adapter *padapter)
{
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
psta = rtw_get_stainfo(pstapriv, bc_addr);
return psta;
}
u8 rtw_access_ctrl(struct adapter *padapter, u8 *mac_addr)
{
u8 res = true;
struct list_head *plist, *phead;
struct rtw_wlan_acl_node *paclnode;
u8 match = false;
struct sta_priv *pstapriv = &padapter->stapriv;
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
struct __queue *pacl_node_q = &pacl_list->acl_node_q;
spin_lock_bh(&pacl_node_q->lock);
phead = get_list_head(pacl_node_q);
plist = phead->next;
while (phead != plist) {
paclnode = container_of(plist, struct rtw_wlan_acl_node, list);
plist = plist->next;
if (!memcmp(paclnode->addr, mac_addr, ETH_ALEN)) {
if (paclnode->valid) {
match = true;
break;
}
}
}
spin_unlock_bh(&pacl_node_q->lock);
if (pacl_list->mode == 1)/* accept unless in deny list */
res = !match;
else if (pacl_list->mode == 2)/* deny unless in accept list */
res = match;
else
res = true;
return res;
}

1551
drivers/staging/r8188eu/core/rtw_wlan_util.c
View File

File diff suppressed because it is too large Load Diff

2179
drivers/staging/r8188eu/core/rtw_xmit.c
View File

File diff suppressed because it is too large Load Diff

654
drivers/staging/r8188eu/hal/Hal8188ERateAdaptive.c
View File

@ -1,654 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) Realtek Semiconductor Corp. */
#include "../include/drv_types.h"
static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE + 1] = {
{5, 4, 3, 2, 0, 3}, /* 92 , idx = 0 */
{6, 5, 4, 3, 0, 4}, /* 86 , idx = 1 */
{6, 5, 4, 2, 0, 4}, /* 81 , idx = 2 */
{8, 7, 6, 4, 0, 6}, /* 75 , idx = 3 */
{10, 9, 8, 6, 0, 8}, /* 71 , idx = 4 */
{10, 9, 8, 4, 0, 8}, /* 66 , idx = 5 */
{10, 9, 8, 2, 0, 8}, /* 62 , idx = 6 */
{10, 9, 8, 0, 0, 8}, /* 59 , idx = 7 */
{18, 17, 16, 8, 0, 16}, /* 53 , idx = 8 */
{26, 25, 24, 16, 0, 24}, /* 50 , idx = 9 */
{34, 33, 32, 24, 0, 32}, /* 47 , idx = 0x0a */
{34, 31, 28, 20, 0, 32}, /* 43 , idx = 0x0b */
{34, 31, 27, 18, 0, 32}, /* 40 , idx = 0x0c */
{34, 31, 26, 16, 0, 32}, /* 37 , idx = 0x0d */
{34, 30, 22, 16, 0, 32}, /* 32 , idx = 0x0e */
{34, 30, 24, 16, 0, 32}, /* 26 , idx = 0x0f */
{49, 46, 40, 16, 0, 48}, /* 20 , idx = 0x10 */
{49, 45, 32, 0, 0, 48}, /* 17 , idx = 0x11 */
{49, 45, 22, 18, 0, 48}, /* 15 , idx = 0x12 */
{49, 40, 24, 16, 0, 48}, /* 12 , idx = 0x13 */
{49, 32, 18, 12, 0, 48}, /* 9 , idx = 0x14 */
{49, 22, 18, 14, 0, 48}, /* 6 , idx = 0x15 */
{49, 16, 16, 0, 0, 48}
}; /* 3, idx = 0x16 */
static u8 PT_PENALTY[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32};
/* wilson modify */
static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {
{4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */
4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,
5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f}, /* 0329 R01 */
{0x0a, 0x0a, 0x0b, 0x0c, 0x0a,
0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14, /* SS<TH */
0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x15,
9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13}
};
static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {
0x0c, 0x0d, 0x0d, 0x0f, 0x0d, 0x0e,
0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, /* SS>TH */
0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15,
0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15};
static u8 RSSI_THRESHOLD[RATESIZE] = {
0, 0, 0, 0,
0, 0, 0, 0, 0, 0x24, 0x26, 0x2a,
0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a,
0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c};
static u16 N_THRESHOLD_HIGH[RATESIZE] = {
4, 4, 8, 16,
24, 36, 48, 72, 96, 144, 192, 216,
60, 80, 100, 160, 240, 400, 560, 640,
300, 320, 480, 720, 1000, 1200, 1600, 2000};
static u16 N_THRESHOLD_LOW[RATESIZE] = {
2, 2, 4, 8,
12, 18, 24, 36, 48, 72, 96, 108,
30, 40, 50, 80, 120, 200, 280, 320,
150, 160, 240, 360, 500, 600, 800, 1000};
static u8 DROPING_NECESSARY[RATESIZE] = {
1, 1, 1, 1,
1, 2, 3, 4, 5, 6, 7, 8,
1, 2, 3, 4, 5, 6, 7, 8,
5, 6, 7, 8, 9, 10, 11, 12};
static u8 PendingForRateUpFail[5] = {2, 10, 24, 40, 60};
static u16 DynamicTxRPTTiming[6] = {
0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /* 200ms-1200ms */
/* End Rate adaptive parameters */
static void odm_SetTxRPTTiming_8188E(
struct odm_dm_struct *dm_odm,
struct odm_ra_info *pRaInfo,
u8 extend
)
{
u8 idx = 0;
for (idx = 0; idx < 5; idx++)
if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
break;
if (extend == 0) { /* back to default timing */
idx = 0; /* 200ms */
} else if (extend == 1) {/* increase the timing */
idx += 1;
if (idx > 5)
idx = 5;
} else if (extend == 2) {/* decrease the timing */
if (idx != 0)
idx -= 1;
}
pRaInfo->RptTime = DynamicTxRPTTiming[idx];
}
static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo)
{
u8 RateID, LowestRate, HighestRate;
u8 i;
if (NULL == pRaInfo)
return -1;
RateID = pRaInfo->PreRate;
LowestRate = pRaInfo->LowestRate;
HighestRate = pRaInfo->HighestRate;
if (RateID > HighestRate) {
RateID = HighestRate;
} else if (pRaInfo->RateSGI) {
pRaInfo->RateSGI = 0;
} else if (RateID > LowestRate) {
if (RateID > 0) {
for (i = RateID - 1; i > LowestRate; i--) {
if (pRaInfo->RAUseRate & BIT(i)) {
RateID = i;
goto RateDownFinish;
}
}
}
} else if (RateID <= LowestRate) {
RateID = LowestRate;
}
RateDownFinish:
if (pRaInfo->RAWaitingCounter == 1) {
pRaInfo->RAWaitingCounter += 1;
pRaInfo->RAPendingCounter += 1;
} else if (pRaInfo->RAWaitingCounter == 0) {
;
} else {
pRaInfo->RAWaitingCounter = 0;
pRaInfo->RAPendingCounter = 0;
}
if (pRaInfo->RAPendingCounter >= 4)
pRaInfo->RAPendingCounter = 4;
pRaInfo->DecisionRate = RateID;
odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 2);
return 0;
}
static int odm_RateUp_8188E(
struct odm_dm_struct *dm_odm,
struct odm_ra_info *pRaInfo
)
{
u8 RateID, HighestRate;
u8 i;
if (NULL == pRaInfo)
return -1;
RateID = pRaInfo->PreRate;
HighestRate = pRaInfo->HighestRate;
if (pRaInfo->RAWaitingCounter == 1) {
pRaInfo->RAWaitingCounter = 0;
pRaInfo->RAPendingCounter = 0;
} else if (pRaInfo->RAWaitingCounter > 1) {
pRaInfo->PreRssiStaRA = pRaInfo->RssiStaRA;
goto RateUpfinish;
}
odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 0);
if (RateID < HighestRate) {
for (i = RateID + 1; i <= HighestRate; i++) {
if (pRaInfo->RAUseRate & BIT(i)) {
RateID = i;
goto RateUpfinish;
}
}
} else if (RateID == HighestRate) {
if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1))
pRaInfo->RateSGI = 1;
else if ((pRaInfo->SGIEnable) != 1)
pRaInfo->RateSGI = 0;
} else {
RateID = HighestRate;
}
RateUpfinish:
if (pRaInfo->RAWaitingCounter == (4 + PendingForRateUpFail[pRaInfo->RAPendingCounter]))
pRaInfo->RAWaitingCounter = 0;
else
pRaInfo->RAWaitingCounter++;
pRaInfo->DecisionRate = RateID;
return 0;
}
static void odm_ResetRaCounter_8188E(struct odm_ra_info *pRaInfo)
{
u8 RateID;
RateID = pRaInfo->DecisionRate;
pRaInfo->NscUp = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1;
pRaInfo->NscDown = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1;
}
static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm,
struct odm_ra_info *pRaInfo
)
{
u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
/* u32 pool_retry; */
static u8 DynamicTxRPTTimingCounter;
if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) { /* STA used and data packet exits */
if ((pRaInfo->RssiStaRA < (pRaInfo->PreRssiStaRA - 3)) ||
(pRaInfo->RssiStaRA > (pRaInfo->PreRssiStaRA + 3))) {
pRaInfo->RAWaitingCounter = 0;
pRaInfo->RAPendingCounter = 0;
}
/* Start RA decision */
if (pRaInfo->PreRate > pRaInfo->HighestRate)
RateID = pRaInfo->HighestRate;
else
RateID = pRaInfo->PreRate;
if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID])
RtyPtID = 0;
else
RtyPtID = 1;
PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */
pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0];
pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1];
pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2];
pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3];
pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4];
if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))
pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5];
else
pRaInfo->NscDown = 0;
/* rate up */
PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID];
pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0];
pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1];
pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2];
pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3];
pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4];
if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))
pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5];
else
pRaInfo->NscUp = 0;
if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||
(pRaInfo->DROP > DROPING_NECESSARY[RateID]))
odm_RateDown_8188E(dm_odm, pRaInfo);
else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])
odm_RateUp_8188E(dm_odm, pRaInfo);
if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
pRaInfo->DecisionRate = pRaInfo->HighestRate;
if ((pRaInfo->DecisionRate) == (pRaInfo->PreRate))
DynamicTxRPTTimingCounter += 1;
else
DynamicTxRPTTimingCounter = 0;
if (DynamicTxRPTTimingCounter >= 4) {
odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 1);
DynamicTxRPTTimingCounter = 0;
}
pRaInfo->PreRate = pRaInfo->DecisionRate; /* YJ, add, 120120 */
odm_ResetRaCounter_8188E(pRaInfo);
}
}
static int odm_ARFBRefresh_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo)
{ /* Wilson 2011/10/26 */
u32 MaskFromReg;
s8 i;
int res;
switch (pRaInfo->RateID) {
case RATR_INX_WIRELESS_NGB:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff015;
break;
case RATR_INX_WIRELESS_NG:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff010;
break;
case RATR_INX_WIRELESS_NB:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff005;
break;
case RATR_INX_WIRELESS_N:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff000;
break;
case RATR_INX_WIRELESS_GB:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff5;
break;
case RATR_INX_WIRELESS_G:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff0;
break;
case RATR_INX_WIRELESS_B:
pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0000000d;
break;
case 12:
res = rtw_read32(dm_odm->Adapter, REG_ARFR0, &MaskFromReg);
if (res)
return res;
pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
break;
case 13:
res = rtw_read32(dm_odm->Adapter, REG_ARFR1, &MaskFromReg);
if (res)
return res;
pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
break;
case 14:
res = rtw_read32(dm_odm->Adapter, REG_ARFR2, &MaskFromReg);
if (res)
return res;
pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
break;
case 15:
res = rtw_read32(dm_odm->Adapter, REG_ARFR3, &MaskFromReg);
if (res)
return res;
pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
break;
default:
pRaInfo->RAUseRate = (pRaInfo->RateMask);
break;
}
/* Highest rate */
if (pRaInfo->RAUseRate) {
for (i = RATESIZE; i >= 0; i--) {
if ((pRaInfo->RAUseRate) & BIT(i)) {
pRaInfo->HighestRate = i;
break;
}
}
} else {
pRaInfo->HighestRate = 0;
}
/* Lowest rate */
if (pRaInfo->RAUseRate) {
for (i = 0; i < RATESIZE; i++) {
if ((pRaInfo->RAUseRate) & BIT(i)) {
pRaInfo->LowestRate = i;
break;
}
}
} else {
pRaInfo->LowestRate = 0;
}
if (pRaInfo->HighestRate > 0x13)
pRaInfo->PTModeSS = 3;
else if (pRaInfo->HighestRate > 0x0b)
pRaInfo->PTModeSS = 2;
else if (pRaInfo->HighestRate > 0x03)
pRaInfo->PTModeSS = 1;
else
pRaInfo->PTModeSS = 0;
if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
pRaInfo->DecisionRate = pRaInfo->HighestRate;
return 0;
}
static void odm_PTTryState_8188E(struct odm_ra_info *pRaInfo)
{
pRaInfo->PTTryState = 0;
switch (pRaInfo->PTModeSS) {
case 3:
if (pRaInfo->DecisionRate >= 0x19)
pRaInfo->PTTryState = 1;
break;
case 2:
if (pRaInfo->DecisionRate >= 0x11)
pRaInfo->PTTryState = 1;
break;
case 1:
if (pRaInfo->DecisionRate >= 0x0a)
pRaInfo->PTTryState = 1;
break;
case 0:
if (pRaInfo->DecisionRate >= 0x03)
pRaInfo->PTTryState = 1;
break;
default:
pRaInfo->PTTryState = 0;
break;
}
if (pRaInfo->RssiStaRA < 48) {
pRaInfo->PTStage = 0;
} else if (pRaInfo->PTTryState == 1) {
if ((pRaInfo->PTStopCount >= 10) ||
(pRaInfo->PTPreRssi > pRaInfo->RssiStaRA + 5) ||
(pRaInfo->PTPreRssi < pRaInfo->RssiStaRA - 5) ||
(pRaInfo->DecisionRate != pRaInfo->PTPreRate)) {
if (pRaInfo->PTStage == 0)
pRaInfo->PTStage = 1;
else if (pRaInfo->PTStage == 1)
pRaInfo->PTStage = 3;
else
pRaInfo->PTStage = 5;
pRaInfo->PTPreRssi = pRaInfo->RssiStaRA;
pRaInfo->PTStopCount = 0;
} else {
pRaInfo->RAstage = 0;
pRaInfo->PTStopCount++;
}
} else {
pRaInfo->PTStage = 0;
pRaInfo->RAstage = 0;
}
pRaInfo->PTPreRate = pRaInfo->DecisionRate;
}
static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo)
{
u8 j;
u8 temp_stage;
u32 numsc;
u32 num_total;
u8 stage_id;
numsc = 0;
num_total = pRaInfo->TOTAL * PT_PENALTY[5];
for (j = 0; j <= 4; j++) {
numsc += pRaInfo->RTY[j] * PT_PENALTY[j];
if (numsc > num_total)
break;
}
j = j >> 1;
temp_stage = (pRaInfo->PTStage + 1) >> 1;
if (temp_stage > j)
stage_id = temp_stage - j;
else
stage_id = 0;
pRaInfo->PTSmoothFactor = (pRaInfo->PTSmoothFactor >> 1) + (pRaInfo->PTSmoothFactor >> 2) + stage_id * 16 + 2;
if (pRaInfo->PTSmoothFactor > 192)
pRaInfo->PTSmoothFactor = 192;
stage_id = pRaInfo->PTSmoothFactor >> 6;
temp_stage = stage_id * 2;
if (temp_stage != 0)
temp_stage -= 1;
if (pRaInfo->DROP > 3)
temp_stage = 0;
pRaInfo->PTStage = temp_stage;
}
static void
odm_RATxRPTTimerSetting(
struct odm_dm_struct *dm_odm,
u16 minRptTime
)
{
if (dm_odm->CurrminRptTime != minRptTime) {
rtw_rpt_timer_cfg_cmd(dm_odm->Adapter, minRptTime);
dm_odm->CurrminRptTime = minRptTime;
}
}
int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 macid)
{
struct odm_ra_info *pRaInfo = &dm_odm->RAInfo[macid];
u8 WirelessMode = 0xFF; /* invalid value */
u8 max_rate_idx = 0x13; /* MCS7 */
if (dm_odm->pWirelessMode)
WirelessMode = *dm_odm->pWirelessMode;
if (WirelessMode != 0xFF) {
if (WirelessMode & ODM_WM_N24G)
max_rate_idx = 0x13;
else if (WirelessMode & ODM_WM_G)
max_rate_idx = 0x0b;
else if (WirelessMode & ODM_WM_B)
max_rate_idx = 0x03;
}
pRaInfo->DecisionRate = max_rate_idx;
pRaInfo->PreRate = max_rate_idx;
pRaInfo->HighestRate = max_rate_idx;
pRaInfo->LowestRate = 0;
pRaInfo->RateID = 0;
pRaInfo->RateMask = 0xffffffff;
pRaInfo->RssiStaRA = 0;
pRaInfo->PreRssiStaRA = 0;
pRaInfo->SGIEnable = 0;
pRaInfo->RAUseRate = 0xffffffff;
pRaInfo->NscDown = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2;
pRaInfo->NscUp = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2;
pRaInfo->RateSGI = 0;
pRaInfo->Active = 1; /* Active is not used at present. by page, 110819 */
pRaInfo->RptTime = 0x927c;
pRaInfo->DROP = 0;
pRaInfo->RTY[0] = 0;
pRaInfo->RTY[1] = 0;
pRaInfo->RTY[2] = 0;
pRaInfo->RTY[3] = 0;
pRaInfo->RTY[4] = 0;
pRaInfo->TOTAL = 0;
pRaInfo->RAWaitingCounter = 0;
pRaInfo->RAPendingCounter = 0;
pRaInfo->PTActive = 1; /* Active when this STA is use */
pRaInfo->PTTryState = 0;
pRaInfo->PTStage = 5; /* Need to fill into HW_PWR_STATUS */
pRaInfo->PTSmoothFactor = 192;
pRaInfo->PTStopCount = 0;
pRaInfo->PTPreRate = 0;
pRaInfo->PTPreRssi = 0;
pRaInfo->PTModeSS = 0;
pRaInfo->RAstage = 0;
return 0;
}
int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm)
{
u8 macid = 0;
dm_odm->CurrminRptTime = 0;
for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++)
ODM_RAInfo_Init(dm_odm, macid);
return 0;
}
u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 macid)
{
if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
return 0;
return dm_odm->RAInfo[macid].RateSGI;
}
u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 macid)
{
u8 DecisionRate = 0;
if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
return 0;
DecisionRate = (dm_odm->RAInfo[macid].DecisionRate);
return DecisionRate;
}
u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 macid)
{
u8 PTStage = 5;
if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
return 0;
PTStage = (dm_odm->RAInfo[macid].PTStage);
return PTStage;
}
void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 RateID, u32 RateMask, u8 SGIEnable)
{
struct odm_ra_info *pRaInfo = NULL;
if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
return;
pRaInfo = &dm_odm->RAInfo[macid];
pRaInfo->RateID = RateID;
pRaInfo->RateMask = RateMask;
pRaInfo->SGIEnable = SGIEnable;
odm_ARFBRefresh_8188E(dm_odm, pRaInfo);
}
void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 Rssi)
{
struct odm_ra_info *pRaInfo = NULL;
if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
return;
pRaInfo = &dm_odm->RAInfo[macid];
pRaInfo->RssiStaRA = Rssi;
}
void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime)
{
rtw_write16(dm_odm->Adapter, REG_TX_RPT_TIME, minRptTime);
}
void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm, u8 *TxRPT_Buf, u16 TxRPT_Len, u32 macid_entry0, u32 macid_entry1)
{
struct odm_ra_info *pRAInfo = NULL;
u8 MacId = 0;
u8 *pBuffer = NULL;
u32 valid = 0, ItemNum = 0;
u16 minRptTime = 0x927c;
ItemNum = TxRPT_Len >> 3;
pBuffer = TxRPT_Buf;
do {
if (MacId >= ODM_ASSOCIATE_ENTRY_NUM)
valid = 0;
else if (MacId >= 32)
valid = (1 << (MacId - 32)) & macid_entry1;
else
valid = (1 << MacId) & macid_entry0;
pRAInfo = &dm_odm->RAInfo[MacId];
if (valid) {
pRAInfo->RTY[0] = le16_to_cpup((__le16 *)pBuffer);
pRAInfo->RTY[1] = pBuffer[2];
pRAInfo->RTY[2] = pBuffer[3];
pRAInfo->RTY[3] = pBuffer[4];
pRAInfo->RTY[4] = pBuffer[5];
pRAInfo->DROP = pBuffer[6];
pRAInfo->TOTAL = pRAInfo->RTY[0] + pRAInfo->RTY[1] +
pRAInfo->RTY[2] + pRAInfo->RTY[3] +
pRAInfo->RTY[4] + pRAInfo->DROP;
if (pRAInfo->TOTAL != 0) {
if (pRAInfo->PTActive) {
if (pRAInfo->RAstage < 5)
odm_RateDecision_8188E(dm_odm, pRAInfo);
else if (pRAInfo->RAstage == 5) /* Power training try state */
odm_PTTryState_8188E(pRAInfo);
else /* RAstage == 6 */
odm_PTDecision_8188E(pRAInfo);
/* Stage_RA counter */
if (pRAInfo->RAstage <= 5)
pRAInfo->RAstage++;
else
pRAInfo->RAstage = 0;
} else {
odm_RateDecision_8188E(dm_odm, pRAInfo);
}
}
}
if (minRptTime > pRAInfo->RptTime)
minRptTime = pRAInfo->RptTime;
pBuffer += TX_RPT2_ITEM_SIZE;
MacId++;
} while (MacId < ItemNum);
odm_RATxRPTTimerSetting(dm_odm, minRptTime);
}

733
drivers/staging/r8188eu/hal/HalHWImg8188E_BB.c
View File

@ -1,733 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/rtw_iol.h"
#define read_next_pair(array, v1, v2, i) \
do { \
i += 2; \
v1 = array[i]; \
v2 = array[i + 1]; \
} while (0)
static bool CheckCondition(const u32 condition, const u32 hex)
{
u32 _interface = (hex & 0x0000FF00) >> 8;
u32 _platform = (hex & 0x00FF0000) >> 16;
u32 cond = condition;
if (condition == 0xCDCDCDCD)
return true;
cond = condition & 0x0000FF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = condition & 0x00FF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
/******************************************************************************
* AGC_TAB_1T.TXT
******************************************************************************/
static u32 array_agc_tab_1t_8188e[] = {
0xC78, 0xFB000001,
0xC78, 0xFB010001,
0xC78, 0xFB020001,
0xC78, 0xFB030001,
0xC78, 0xFB040001,
0xC78, 0xFB050001,
0xC78, 0xFA060001,
0xC78, 0xF9070001,
0xC78, 0xF8080001,
0xC78, 0xF7090001,
0xC78, 0xF60A0001,
0xC78, 0xF50B0001,
0xC78, 0xF40C0001,
0xC78, 0xF30D0001,
0xC78, 0xF20E0001,
0xC78, 0xF10F0001,
0xC78, 0xF0100001,
0xC78, 0xEF110001,
0xC78, 0xEE120001,
0xC78, 0xED130001,
0xC78, 0xEC140001,
0xC78, 0xEB150001,
0xC78, 0xEA160001,
0xC78, 0xE9170001,
0xC78, 0xE8180001,
0xC78, 0xE7190001,
0xC78, 0xE61A0001,
0xC78, 0xE51B0001,
0xC78, 0xE41C0001,
0xC78, 0xE31D0001,
0xC78, 0xE21E0001,
0xC78, 0xE11F0001,
0xC78, 0x8A200001,
0xC78, 0x89210001,
0xC78, 0x88220001,
0xC78, 0x87230001,
0xC78, 0x86240001,
0xC78, 0x85250001,
0xC78, 0x84260001,
0xC78, 0x83270001,
0xC78, 0x82280001,
0xC78, 0x6B290001,
0xC78, 0x6A2A0001,
0xC78, 0x692B0001,
0xC78, 0x682C0001,
0xC78, 0x672D0001,
0xC78, 0x662E0001,
0xC78, 0x652F0001,
0xC78, 0x64300001,
0xC78, 0x63310001,
0xC78, 0x62320001,
0xC78, 0x61330001,
0xC78, 0x46340001,
0xC78, 0x45350001,
0xC78, 0x44360001,
0xC78, 0x43370001,
0xC78, 0x42380001,
0xC78, 0x41390001,
0xC78, 0x403A0001,
0xC78, 0x403B0001,
0xC78, 0x403C0001,
0xC78, 0x403D0001,
0xC78, 0x403E0001,
0xC78, 0x403F0001,
0xC78, 0xFB400001,
0xC78, 0xFB410001,
0xC78, 0xFB420001,
0xC78, 0xFB430001,
0xC78, 0xFB440001,
0xC78, 0xFB450001,
0xC78, 0xFB460001,
0xC78, 0xFB470001,
0xC78, 0xFB480001,
0xC78, 0xFA490001,
0xC78, 0xF94A0001,
0xC78, 0xF84B0001,
0xC78, 0xF74C0001,
0xC78, 0xF64D0001,
0xC78, 0xF54E0001,
0xC78, 0xF44F0001,
0xC78, 0xF3500001,
0xC78, 0xF2510001,
0xC78, 0xF1520001,
0xC78, 0xF0530001,
0xC78, 0xEF540001,
0xC78, 0xEE550001,
0xC78, 0xED560001,
0xC78, 0xEC570001,
0xC78, 0xEB580001,
0xC78, 0xEA590001,
0xC78, 0xE95A0001,
0xC78, 0xE85B0001,
0xC78, 0xE75C0001,
0xC78, 0xE65D0001,
0xC78, 0xE55E0001,
0xC78, 0xE45F0001,
0xC78, 0xE3600001,
0xC78, 0xE2610001,
0xC78, 0xC3620001,
0xC78, 0xC2630001,
0xC78, 0xC1640001,
0xC78, 0x8B650001,
0xC78, 0x8A660001,
0xC78, 0x89670001,
0xC78, 0x88680001,
0xC78, 0x87690001,
0xC78, 0x866A0001,
0xC78, 0x856B0001,
0xC78, 0x846C0001,
0xC78, 0x676D0001,
0xC78, 0x666E0001,
0xC78, 0x656F0001,
0xC78, 0x64700001,
0xC78, 0x63710001,
0xC78, 0x62720001,
0xC78, 0x61730001,
0xC78, 0x60740001,
0xC78, 0x46750001,
0xC78, 0x45760001,
0xC78, 0x44770001,
0xC78, 0x43780001,
0xC78, 0x42790001,
0xC78, 0x417A0001,
0xC78, 0x407B0001,
0xC78, 0x407C0001,
0xC78, 0x407D0001,
0xC78, 0x407E0001,
0xC78, 0x407F0001,
};
static void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
{
rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
}
int ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *dm_odm)
{
u32 hex = 0;
u32 i = 0;
u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
u32 *array = array_agc_tab_1t_8188e;
bool biol = false;
struct adapter *adapter = dm_odm->Adapter;
struct xmit_frame *pxmit_frame = NULL;
u8 bndy_cnt = 1;
hex += ODM_ITRF_USB << 8;
hex += ODM_CE << 16;
hex += 0xFF000000;
biol = rtw_IOL_applied(adapter);
if (biol) {
pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
if (!pxmit_frame) {
pr_info("rtw_IOL_accquire_xmit_frame failed\n");
return -ENOMEM;
}
}
for (i = 0; i < arraylen; i += 2) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
} else {
odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2);
}
continue;
} else {
/* This line is the start line of branch. */
if (!CheckCondition(array[i], hex)) {
/* Discard the following (offset, data) pairs. */
read_next_pair(array, v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2)
read_next_pair(array, v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else { /* Configure matched pairs and skip to end of if-else. */
read_next_pair(array, v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
} else {
odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2);
}
read_next_pair(array, v1, v2, i);
}
while (v2 != 0xDEAD && i < arraylen - 2)
read_next_pair(array, v1, v2, i);
}
}
}
if (biol) {
if (!rtl8188e_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
printk("~~~ %s IOL_exec_cmds Failed !!!\n", __func__);
return -1;
}
}
return 0;
}
/******************************************************************************
* PHY_REG_1T.TXT
******************************************************************************/
static u32 array_phy_reg_1t_8188e[] = {
0x800, 0x80040000,
0x804, 0x00000003,
0x808, 0x0000FC00,
0x80C, 0x0000000A,
0x810, 0x10001331,
0x814, 0x020C3D10,
0x818, 0x02200385,
0x81C, 0x00000000,
0x820, 0x01000100,
0x824, 0x00390204,
0x828, 0x00000000,
0x82C, 0x00000000,
0x830, 0x00000000,
0x834, 0x00000000,
0x838, 0x00000000,
0x83C, 0x00000000,
0x840, 0x00010000,
0x844, 0x00000000,
0x848, 0x00000000,
0x84C, 0x00000000,
0x850, 0x00000000,
0x854, 0x00000000,
0x858, 0x569A11A9,
0x85C, 0x01000014,
0x860, 0x66F60110,
0x864, 0x061F0649,
0x868, 0x00000000,
0x86C, 0x27272700,
0x870, 0x07000760,
0x874, 0x25004000,
0x878, 0x00000808,
0x87C, 0x00000000,
0x880, 0xB0000C1C,
0x884, 0x00000001,
0x888, 0x00000000,
0x88C, 0xCCC000C0,
0x890, 0x00000800,
0x894, 0xFFFFFFFE,
0x898, 0x40302010,
0x89C, 0x00706050,
0x900, 0x00000000,
0x904, 0x00000023,
0x908, 0x00000000,
0x90C, 0x81121111,
0x910, 0x00000002,
0x914, 0x00000201,
0xA00, 0x00D047C8,
0xA04, 0x80FF000C,
0xA08, 0x8C838300,
0xA0C, 0x2E7F120F,
0xA10, 0x9500BB78,
0xA14, 0x1114D028,
0xA18, 0x00881117,
0xA1C, 0x89140F00,
0xA20, 0x1A1B0000,
0xA24, 0x090E1317,
0xA28, 0x00000204,
0xA2C, 0x00D30000,
0xA70, 0x101FBF00,
0xA74, 0x00000007,
0xA78, 0x00000900,
0xA7C, 0x225B0606,
0xA80, 0x218075B1,
0xB2C, 0x80000000,
0xC00, 0x48071D40,
0xC04, 0x03A05611,
0xC08, 0x000000E4,
0xC0C, 0x6C6C6C6C,
0xC10, 0x08800000,
0xC14, 0x40000100,
0xC18, 0x08800000,
0xC1C, 0x40000100,
0xC20, 0x00000000,
0xC24, 0x00000000,
0xC28, 0x00000000,
0xC2C, 0x00000000,
0xC30, 0x69E9AC47,
0xC34, 0x469652AF,
0xC38, 0x49795994,
0xC3C, 0x0A97971C,
0xC40, 0x1F7C403F,
0xC44, 0x000100B7,
0xC48, 0xEC020107,
0xC4C, 0x007F037F,
0xC50, 0x69553420,
0xC54, 0x43BC0094,
0xC58, 0x00013169,
0xC5C, 0x00250492,
0xC60, 0x00000000,
0xC64, 0x7112848B,
0xC68, 0x47C00BFF,
0xC6C, 0x00000036,
0xC70, 0x2C7F000D,
0xC74, 0x020610DB,
0xC78, 0x0000001F,
0xC7C, 0x00B91612,
0xC80, 0x390000E4,
0xC84, 0x20F60000,
0xC88, 0x40000100,
0xC8C, 0x20200000,
0xC90, 0x00091521,
0xC94, 0x00000000,
0xC98, 0x00121820,
0xC9C, 0x00007F7F,
0xCA0, 0x00000000,
0xCA4, 0x000300A0,
0xCA8, 0x00000000,
0xCAC, 0x00000000,
0xCB0, 0x00000000,
0xCB4, 0x00000000,
0xCB8, 0x00000000,
0xCBC, 0x28000000,
0xCC0, 0x00000000,
0xCC4, 0x00000000,
0xCC8, 0x00000000,
0xCCC, 0x00000000,
0xCD0, 0x00000000,
0xCD4, 0x00000000,
0xCD8, 0x64B22427,
0xCDC, 0x00766932,
0xCE0, 0x00222222,
0xCE4, 0x00000000,
0xCE8, 0x37644302,
0xCEC, 0x2F97D40C,
0xD00, 0x00000740,
0xD04, 0x00020401,
0xD08, 0x0000907F,
0xD0C, 0x20010201,
0xD10, 0xA0633333,
0xD14, 0x3333BC43,
0xD18, 0x7A8F5B6F,
0xD2C, 0xCC979975,
0xD30, 0x00000000,
0xD34, 0x80608000,
0xD38, 0x00000000,
0xD3C, 0x00127353,
0xD40, 0x00000000,
0xD44, 0x00000000,
0xD48, 0x00000000,
0xD4C, 0x00000000,
0xD50, 0x6437140A,
0xD54, 0x00000000,
0xD58, 0x00000282,
0xD5C, 0x30032064,
0xD60, 0x4653DE68,
0xD64, 0x04518A3C,
0xD68, 0x00002101,
0xD6C, 0x2A201C16,
0xD70, 0x1812362E,
0xD74, 0x322C2220,
0xD78, 0x000E3C24,
0xE00, 0x2D2D2D2D,
0xE04, 0x2D2D2D2D,
0xE08, 0x0390272D,
0xE10, 0x2D2D2D2D,
0xE14, 0x2D2D2D2D,
0xE18, 0x2D2D2D2D,
0xE1C, 0x2D2D2D2D,
0xE28, 0x00000000,
0xE30, 0x1000DC1F,
0xE34, 0x10008C1F,
0xE38, 0x02140102,
0xE3C, 0x681604C2,
0xE40, 0x01007C00,
0xE44, 0x01004800,
0xE48, 0xFB000000,
0xE4C, 0x000028D1,
0xE50, 0x1000DC1F,
0xE54, 0x10008C1F,
0xE58, 0x02140102,
0xE5C, 0x28160D05,
0xE60, 0x00000008,
0xE68, 0x001B25A4,
0xE6C, 0x00C00014,
0xE70, 0x00C00014,
0xE74, 0x01000014,
0xE78, 0x01000014,
0xE7C, 0x01000014,
0xE80, 0x01000014,
0xE84, 0x00C00014,
0xE88, 0x01000014,
0xE8C, 0x00C00014,
0xED0, 0x00C00014,
0xED4, 0x00C00014,
0xED8, 0x00C00014,
0xEDC, 0x00000014,
0xEE0, 0x00000014,
0xEEC, 0x01C00014,
0xF14, 0x00000003,
0xF4C, 0x00000000,
0xF00, 0x00000300,
};
static void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
{
if (Addr == 0xfe) {
msleep(50);
} else if (Addr == 0xfd) {
mdelay(5);
} else if (Addr == 0xfc) {
mdelay(1);
} else if (Addr == 0xfb) {
udelay(50);
} else if (Addr == 0xfa) {
udelay(5);
} else if (Addr == 0xf9) {
udelay(1);
} else {
if (Addr == 0xa24)
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
}
}
int ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *dm_odm)
{
u32 hex = 0;
u32 i = 0;
u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
u32 *array = array_phy_reg_1t_8188e;
bool biol = false;
struct adapter *adapter = dm_odm->Adapter;
struct xmit_frame *pxmit_frame = NULL;
u8 bndy_cnt = 1;
hex += ODM_ITRF_USB << 8;
hex += ODM_CE << 16;
hex += 0xFF000000;
biol = rtw_IOL_applied(adapter);
if (biol) {
pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
if (!pxmit_frame) {
pr_info("rtw_IOL_accquire_xmit_frame failed\n");
return -ENOMEM;
}
}
for (i = 0; i < arraylen; i += 2) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
if (v1 == 0xfe) {
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
} else if (v1 == 0xfd) {
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
} else if (v1 == 0xfc) {
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
} else if (v1 == 0xfb) {
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
} else if (v1 == 0xfa) {
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
} else if (v1 == 0xf9) {
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
} else {
if (v1 == 0xa24)
dm_odm->RFCalibrateInfo.RegA24 = v2;
rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
}
} else {
odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2);
}
continue;
} else { /* This line is the start line of branch. */
if (!CheckCondition(array[i], hex)) {
/* Discard the following (offset, data) pairs. */
read_next_pair(array, v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2)
read_next_pair(array, v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else { /* Configure matched pairs and skip to end of if-else. */
read_next_pair(array, v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
if (v1 == 0xfe) {
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
} else if (v1 == 0xfd) {
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
} else if (v1 == 0xfc) {
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
} else if (v1 == 0xfb) {
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
} else if (v1 == 0xfa) {
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
} else if (v1 == 0xf9) {
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
} else {
if (v1 == 0xa24)
dm_odm->RFCalibrateInfo.RegA24 = v2;
rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
}
} else {
odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2);
}
read_next_pair(array, v1, v2, i);
}
while (v2 != 0xDEAD && i < arraylen - 2)
read_next_pair(array, v1, v2, i);
}
}
}
if (biol) {
if (!rtl8188e_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
pr_info("~~~ IOL Config %s Failed !!!\n", __func__);
return -1;
}
}
return 0;
}
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
static u32 array_phy_reg_pg_8188e[] = {
0xE00, 0xFFFFFFFF, 0x06070809,
0xE04, 0xFFFFFFFF, 0x02020405,
0xE08, 0x0000FF00, 0x00000006,
0x86C, 0xFFFFFF00, 0x00020400,
0xE10, 0xFFFFFFFF, 0x08090A0B,
0xE14, 0xFFFFFFFF, 0x01030607,
0xE18, 0xFFFFFFFF, 0x08090A0B,
0xE1C, 0xFFFFFFFF, 0x01030607,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x02020202,
0xE04, 0xFFFFFFFF, 0x00020202,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x04040404,
0xE14, 0xFFFFFFFF, 0x00020404,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x02020202,
0xE04, 0xFFFFFFFF, 0x00020202,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x04040404,
0xE14, 0xFFFFFFFF, 0x00020404,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x02020202,
0xE04, 0xFFFFFFFF, 0x00020202,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x04040404,
0xE14, 0xFFFFFFFF, 0x00020404,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
};
static void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask,
u32 Data)
{
if (Addr == 0xfe)
msleep(50);
else if (Addr == 0xfd)
mdelay(5);
else if (Addr == 0xfc)
mdelay(1);
else if (Addr == 0xfb)
udelay(50);
else if (Addr == 0xfa)
udelay(5);
else if (Addr == 0xf9)
udelay(1);
else
storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
}
void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm)
{
u32 hex;
u32 i = 0;
u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
u32 *array = array_phy_reg_pg_8188e;
hex = ODM_ITRF_USB << 8;
hex += (ODM_CE << 16) + 0xFF000000;
for (i = 0; i < arraylen; i += 3) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
/* this line is a line of pure_body */
if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_PHY_REG_PG_8188E(dm_odm, v1, v2, v3);
continue;
} else { /* this line is the start of branch */
if (!CheckCondition(array[i], hex)) {
/* don't need the hw_body */
i += 2; /* skip the pair of expression */
v1 = array[i];
v2 = array[i + 1];
v3 = array[i + 2];
while (v2 != 0xDEAD) {
i += 3;
v1 = array[i];
v2 = array[i + 1];
v3 = array[i + 1];
}
}
}
}
}

212
drivers/staging/r8188eu/hal/HalHWImg8188E_MAC.c
View File

@ -1,212 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/rtw_iol.h"
static bool Checkcondition(const u32 condition, const u32 hex)
{
u32 _board = (hex & 0x000000FF);
u32 _interface = (hex & 0x0000FF00) >> 8;
u32 _platform = (hex & 0x00FF0000) >> 16;
u32 cond = condition;
if (condition == 0xCDCDCDCD)
return true;
cond = condition & 0x000000FF;
if ((_board == cond) && cond != 0x00)
return false;
cond = condition & 0x0000FF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = condition & 0x00FF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
static u32 array_MAC_REG_8188E[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000001,
0x432, 0x00000002,
0x433, 0x00000004,
0x434, 0x00000005,
0x435, 0x00000006,
0x436, 0x00000007,
0x437, 0x00000008,
0x438, 0x00000000,
0x439, 0x00000000,
0x43A, 0x00000001,
0x43B, 0x00000002,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000006,
0x43F, 0x00000007,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000015,
0x445, 0x000000F0,
0x446, 0x0000000F,
0x447, 0x00000000,
0x458, 0x00000041,
0x459, 0x000000A8,
0x45A, 0x00000072,
0x45B, 0x000000B9,
0x460, 0x00000066,
0x461, 0x00000066,
0x480, 0x00000008,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4D3, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x652, 0x00000020,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
static void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)
{
rtw_write8(pDM_Odm->Adapter, Addr, Data);
}
int ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *dm_odm)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0)
u32 hex = 0;
u32 i;
u32 array_len = ARRAY_SIZE(array_MAC_REG_8188E);
u32 *array = array_MAC_REG_8188E;
bool biol = false;
struct adapter *adapt = dm_odm->Adapter;
struct xmit_frame *pxmit_frame = NULL;
u8 bndy_cnt = 1;
hex += ODM_ITRF_USB << 8;
hex += ODM_CE << 16;
hex += 0xFF000000;
biol = rtw_IOL_applied(adapt);
if (biol) {
pxmit_frame = rtw_IOL_accquire_xmit_frame(adapt);
if (!pxmit_frame) {
pr_info("rtw_IOL_accquire_xmit_frame failed\n");
return -ENOMEM;
}
}
for (i = 0; i < array_len; i += 2) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF);
} else {
odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2);
}
continue;
} else { /* This line is the start line of branch. */
if (!Checkcondition(array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < array_len - 2) {
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2 */
} else { /* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < array_len - 2) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF);
} else {
odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < array_len - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
if (biol) {
if (!rtl8188e_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
pr_info("~~~ MAC IOL_exec_cmds Failed !!!\n");
return -1;
}
}
return 0;
}

269
drivers/staging/r8188eu/hal/HalHWImg8188E_RF.c
View File

@ -1,269 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/rtw_iol.h"
static bool CheckCondition(const u32 Condition, const u32 Hex)
{
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if (Condition == 0xCDCDCDCD)
return true;
cond = Condition & 0x0000FF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = Condition & 0x00FF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
static u32 Array_RadioA_1T_8188E[] = {
0x000, 0x00030000,
0x008, 0x00084000,
0x018, 0x00000407,
0x019, 0x00000012,
0x01E, 0x00080009,
0x01F, 0x00000880,
0x02F, 0x0001A060,
0x03F, 0x00000000,
0x042, 0x000060C0,
0x057, 0x000D0000,
0x058, 0x000BE180,
0x067, 0x00001552,
0x083, 0x00000000,
0x0B0, 0x000FF8FC,
0x0B1, 0x00054400,
0x0B2, 0x000CCC19,
0x0B4, 0x00043003,
0x0B6, 0x0004953E,
0x0B7, 0x0001C718,
0x0B8, 0x000060FF,
0x0B9, 0x00080001,
0x0BA, 0x00040000,
0x0BB, 0x00000400,
0x0BF, 0x000C0000,
0x0C2, 0x00002400,
0x0C3, 0x00000009,
0x0C4, 0x00040C91,
0x0C5, 0x00099999,
0x0C6, 0x000000A3,
0x0C7, 0x00088820,
0x0C8, 0x00076C06,
0x0C9, 0x00000000,
0x0CA, 0x00080000,
0x0DF, 0x00000180,
0x0EF, 0x000001A0,
0x051, 0x0006B27D,
0xFF0F041F, 0xABCD,
0x052, 0x0007E4DD,
0xCDCDCDCD, 0xCDCD,
0x052, 0x0007E49D,
0xFF0F041F, 0xDEAD,
0x053, 0x00000073,
0x056, 0x00051FF3,
0x035, 0x00000086,
0x035, 0x00000186,
0x035, 0x00000286,
0x036, 0x00001C25,
0x036, 0x00009C25,
0x036, 0x00011C25,
0x036, 0x00019C25,
0x0B6, 0x00048538,
0x018, 0x00000C07,
0x05A, 0x0004BD00,
0x019, 0x000739D0,
0x034, 0x0000ADF3,
0x034, 0x00009DF0,
0x034, 0x00008DED,
0x034, 0x00007DEA,
0x034, 0x00006DE7,
0x034, 0x000054EE,
0x034, 0x000044EB,
0x034, 0x000034E8,
0x034, 0x0000246B,
0x034, 0x00001468,
0x034, 0x0000006D,
0x000, 0x00030159,
0x084, 0x00068200,
0x086, 0x000000CE,
0x087, 0x00048A00,
0x08E, 0x00065540,
0x08F, 0x00088000,
0x0EF, 0x000020A0,
0x03B, 0x000F02B0,
0x03B, 0x000EF7B0,
0x03B, 0x000D4FB0,
0x03B, 0x000CF060,
0x03B, 0x000B0090,
0x03B, 0x000A0080,
0x03B, 0x00090080,
0x03B, 0x0008F780,
0x03B, 0x000722B0,
0x03B, 0x0006F7B0,
0x03B, 0x00054FB0,
0x03B, 0x0004F060,
0x03B, 0x00030090,
0x03B, 0x00020080,
0x03B, 0x00010080,
0x03B, 0x0000F780,
0x0EF, 0x000000A0,
0x000, 0x00010159,
0x018, 0x0000F407,
0xFFE, 0x00000000,
0xFFE, 0x00000000,
0x01F, 0x00080003,
0xFFE, 0x00000000,
0xFFE, 0x00000000,
0x01E, 0x00000001,
0x01F, 0x00080000,
0x000, 0x00033E60,
};
static void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
u32 Data, u32 RegAddr)
{
if (Addr == 0xffe) {
msleep(50);
} else if (Addr == 0xfd) {
mdelay(5);
} else if (Addr == 0xfc) {
mdelay(1);
} else if (Addr == 0xfb) {
udelay(50);
} else if (Addr == 0xfa) {
udelay(5);
} else if (Addr == 0xf9) {
udelay(1);
} else {
rtl8188e_PHY_SetRFReg(pDM_Odm->Adapter, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
}
}
static void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskforPhySet = (u32)(content & 0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, Addr | maskforPhySet);
}
int ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *pDM_Odm)
{
#define READ_NEXT_PAIR(v1, v2, i) do \
{ i += 2; v1 = Array[i]; \
v2 = Array[i + 1]; } while (0)
u32 hex = 0;
u32 i = 0;
u32 ArrayLen = ARRAY_SIZE(Array_RadioA_1T_8188E);
u32 *Array = Array_RadioA_1T_8188E;
bool biol = false;
struct adapter *Adapter = pDM_Odm->Adapter;
struct xmit_frame *pxmit_frame = NULL;
u8 bndy_cnt = 1;
hex += ODM_ITRF_USB << 8;
hex += ODM_CE << 16;
hex += 0xFF000000;
biol = rtw_IOL_applied(Adapter);
if (biol) {
pxmit_frame = rtw_IOL_accquire_xmit_frame(Adapter);
if (!pxmit_frame) {
pr_info("rtw_IOL_accquire_xmit_frame failed\n");
return -ENOMEM;
}
}
for (i = 0; i < ArrayLen; i += 2) {
u32 v1 = Array[i];
u32 v2 = Array[i + 1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
if (v1 == 0xffe)
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
else if (v1 == 0xfd)
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
else if (v1 == 0xfc)
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
else if (v1 == 0xfb)
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
else if (v1 == 0xfa)
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
else if (v1 == 0xf9)
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
else
rtw_IOL_append_WRF_cmd(pxmit_frame, RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask);
} else {
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
continue;
} else { /* This line is the start line of branch. */
if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else { /* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) {
if (biol) {
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
if (v1 == 0xffe)
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
else if (v1 == 0xfd)
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
else if (v1 == 0xfc)
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
else if (v1 == 0xfb)
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
else if (v1 == 0xfa)
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
else if (v1 == 0xf9)
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
else
rtw_IOL_append_WRF_cmd(pxmit_frame, RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask);
} else {
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
if (biol) {
if (!rtl8188e_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
pr_info("~~~ IOL Config %s Failed !!!\n", __func__);
return -1;
}
}
return 0;
}

900
drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
View File

@ -1,900 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/drv_types.h"
/*---------------------------Define Local Constant---------------------------*/
/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
#define ODM_TXPWRTRACK_MAX_IDX_88E 6
/*---------------------------Define Local Constant---------------------------*/
/* 3============================================================ */
/* 3 Tx Power Tracking */
/* 3============================================================ */
/*-----------------------------------------------------------------------------
* Function: ODM_TxPwrTrackAdjust88E()
*
* Overview: 88E we can not write 0xc80/c94/c4c/ 0xa2x. Instead of write TX agc.
* No matter OFDM & CCK use the same method.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 04/23/2012 MHC Create Version 0.
* 04/23/2012 MHC Adjust TX agc directly not throughput BB digital.
*
*---------------------------------------------------------------------------*/
void ODM_TxPwrTrackAdjust88E(struct odm_dm_struct *dm_odm, u8 Type,/* 0 = OFDM, 1 = CCK */
u8 *pDirection, /* 1 = +(increase) 2 = -(decrease) */
u32 *pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */
)
{
u8 pwr_value = 0;
/* Tx power tracking BB swing table. */
/* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
if (Type == 0) { /* For OFDM afjust */
if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) {
*pDirection = 1;
pwr_value = (dm_odm->BbSwingIdxOfdmBase - dm_odm->BbSwingIdxOfdm);
} else {
*pDirection = 2;
pwr_value = (dm_odm->BbSwingIdxOfdm - dm_odm->BbSwingIdxOfdmBase);
}
} else if (Type == 1) { /* For CCK adjust. */
if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) {
*pDirection = 1;
pwr_value = (dm_odm->BbSwingIdxCckBase - dm_odm->BbSwingIdxCck);
} else {
*pDirection = 2;
pwr_value = (dm_odm->BbSwingIdxCck - dm_odm->BbSwingIdxCckBase);
}
}
/* */
/* 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking */
/* need to be less than 6 power index for 88E. */
/* */
if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1)
pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E;
*pOutWriteVal = pwr_value | (pwr_value << 8) | (pwr_value << 16) | (pwr_value << 24);
} /* ODM_TxPwrTrackAdjust88E */
/*-----------------------------------------------------------------------------
* Function: odm_TxPwrTrackSetPwr88E()
*
* Overview: 88E change all channel tx power according to flag.
* OFDM & CCK are all different.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 04/23/2012 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
static void odm_TxPwrTrackSetPwr88E(struct odm_dm_struct *dm_odm)
{
if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) {
PHY_SetTxPowerLevel8188E(dm_odm->Adapter, *dm_odm->pChannel);
dm_odm->BbSwingFlagOfdm = false;
dm_odm->BbSwingFlagCck = false;
}
} /* odm_TxPwrTrackSetPwr88E */
/* 091212 chiyokolin */
void
odm_TXPowerTrackingCallback_ThermalMeter_8188E(
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
u8 ThermalValue_AVG_count = 0;
u32 ThermalValue_AVG = 0;
s32 ele_D, TempCCk;
s8 OFDM_index, CCK_index = 0;
s8 OFDM_index_old = 0, CCK_index_old = 0;
u32 i = 0, j = 0;
u8 OFDM_min_index = 6; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
s8 OFDM_index_mapping[2][index_mapping_NUM_88E] = {
{0, 0, 2, 3, 4, 4, /* 2.4G, decrease power */
5, 6, 7, 7, 8, 9,
10, 10, 11}, /* For lower temperature, 20120220 updated on 20120220. */
{0, 0, -1, -2, -3, -4, /* 2.4G, increase power */
-4, -4, -4, -5, -7, -8,
-9, -9, -10},
};
u8 Thermal_mapping[2][index_mapping_NUM_88E] = {
{0, 2, 4, 6, 8, 10, /* 2.4G, decrease power */
12, 14, 16, 18, 20, 22,
24, 26, 27},
{0, 2, 4, 6, 8, 10, /* 2.4G,, increase power */
12, 14, 16, 18, 20, 22,
25, 25, 25},
};
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
odm_TxPwrTrackSetPwr88E(dm_odm);
/* <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */
dm_odm->RFCalibrateInfo.RegA24 = 0x090e1317;
ThermalValue = (u8)rtl8188e_PHY_QueryRFReg(Adapter, RF_T_METER_88E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
if (ThermalValue) {
/* Query OFDM path A default setting */
ele_D = rtl8188e_PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) & bMaskOFDM_D;
for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { /* find the index */
if (ele_D == (OFDMSwingTable[i] & bMaskOFDM_D)) {
OFDM_index_old = (u8)i;
dm_odm->BbSwingIdxOfdmBase = (u8)i;
break;
}
}
/* Query CCK default setting From 0xa24 */
TempCCk = dm_odm->RFCalibrateInfo.RegA24;
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (memcmp((void *)&TempCCk, (void *)&cck_swing_table[i][2], 4)) {
CCK_index_old = (u8)i;
dm_odm->BbSwingIdxCckBase = (u8)i;
break;
}
}
if (!dm_odm->RFCalibrateInfo.ThermalValue) {
dm_odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
dm_odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
dm_odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
dm_odm->RFCalibrateInfo.OFDM_index = OFDM_index_old;
dm_odm->RFCalibrateInfo.CCK_index = CCK_index_old;
}
/* calculate average thermal meter */
dm_odm->RFCalibrateInfo.ThermalValue_AVG[dm_odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
dm_odm->RFCalibrateInfo.ThermalValue_AVG_index++;
if (dm_odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
dm_odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
if (dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]) {
ThermalValue_AVG += dm_odm->RFCalibrateInfo.ThermalValue_AVG[i];
ThermalValue_AVG_count++;
}
}
if (ThermalValue_AVG_count)
ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count);
if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
delta = ThermalValue > pHalData->EEPROMThermalMeter ?
(ThermalValue - pHalData->EEPROMThermalMeter) :
(pHalData->EEPROMThermalMeter - ThermalValue);
dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false;
dm_odm->RFCalibrateInfo.bDoneTxpower = false;
} else if (dm_odm->RFCalibrateInfo.bDoneTxpower) {
delta = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue) ?
(ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue) :
(dm_odm->RFCalibrateInfo.ThermalValue - ThermalValue);
} else {
delta = ThermalValue > pHalData->EEPROMThermalMeter ?
(ThermalValue - pHalData->EEPROMThermalMeter) :
(pHalData->EEPROMThermalMeter - ThermalValue);
}
delta_LCK = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue_LCK) ?
(ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue_LCK) :
(dm_odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue);
delta_IQK = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue_IQK) ?
(ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue_IQK) :
(dm_odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
if ((delta_LCK >= 8)) { /* Delta temperature is equal to or larger than 20 centigrade. */
dm_odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
PHY_LCCalibrate_8188E(Adapter);
}
if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) {
delta = ThermalValue > pHalData->EEPROMThermalMeter ?
(ThermalValue - pHalData->EEPROMThermalMeter) :
(pHalData->EEPROMThermalMeter - ThermalValue);
/* calculate new OFDM / CCK offset */
if (ThermalValue > pHalData->EEPROMThermalMeter)
j = 1;
else
j = 0;
for (offset = 0; offset < index_mapping_NUM_88E; offset++) {
if (delta < Thermal_mapping[j][offset]) {
if (offset != 0)
offset--;
break;
}
}
if (offset >= index_mapping_NUM_88E)
offset = index_mapping_NUM_88E - 1;
OFDM_index = dm_odm->RFCalibrateInfo.OFDM_index + OFDM_index_mapping[j][offset];
CCK_index = dm_odm->RFCalibrateInfo.CCK_index + OFDM_index_mapping[j][offset];
if (OFDM_index > OFDM_TABLE_SIZE_92D - 1)
OFDM_index = OFDM_TABLE_SIZE_92D - 1;
else if (OFDM_index < OFDM_min_index)
OFDM_index = OFDM_min_index;
if (CCK_index > CCK_TABLE_SIZE - 1)
CCK_index = CCK_TABLE_SIZE - 1;
else if (CCK_index < 0)
CCK_index = 0;
/* 2 temporarily remove bNOPG */
/* Config by SwingTable */
if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) {
dm_odm->RFCalibrateInfo.bDoneTxpower = true;
/* Revse TX power table. */
dm_odm->BbSwingIdxOfdm = (u8)OFDM_index;
dm_odm->BbSwingIdxCck = (u8)CCK_index;
if (dm_odm->BbSwingIdxOfdmCurrent != dm_odm->BbSwingIdxOfdm) {
dm_odm->BbSwingIdxOfdmCurrent = dm_odm->BbSwingIdxOfdm;
dm_odm->BbSwingFlagOfdm = true;
}
if (dm_odm->BbSwingIdxCckCurrent != dm_odm->BbSwingIdxCck) {
dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck;
dm_odm->BbSwingFlagCck = true;
}
}
}
if (delta_IQK >= 8) { /* Delta temperature is equal to or larger than 20 centigrade. */
dm_odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
PHY_IQCalibrate_8188E(Adapter, false);
}
/* update thermal meter value */
if (dm_odm->RFCalibrateInfo.TxPowerTrackControl)
dm_odm->RFCalibrateInfo.ThermalValue = ThermalValue;
}
}
/* 1 7. IQK */
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 /* ms */
static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_IQK_8188E(struct adapter *adapt)
{
u32 regeac, regE94, regE9C;
u8 result = 0x00;
/* 1 Tx IQK */
/* path-A IQK setting */
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
/* LO calibration setting */
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
/* One shot, path A LOK & IQK */
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
/* delay x ms */
/* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
mdelay(IQK_DELAY_TIME_88E);
/* Check failed */
regeac = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
if (!(regeac & BIT(28)) &&
(((regE94 & 0x03FF0000) >> 16) != 0x142) &&
(((regE9C & 0x03FF0000) >> 16) != 0x42))
result |= 0x01;
return result;
}
static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_RxIQK(struct adapter *adapt)
{
u32 regeac, regE94, regE9C, regEA4, u4tmp;
u8 result = 0x00;
/* 1 Get TXIMR setting */
/* modify RXIQK mode table */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
rtl8188e_PHY_SetRFReg(adapt, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
rtl8188e_PHY_SetRFReg(adapt, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
/* PA,PAD off */
rtl8188e_PHY_SetRFReg(adapt, 0xdf, bRFRegOffsetMask, 0x980);
rtl8188e_PHY_SetRFReg(adapt, 0x56, bRFRegOffsetMask, 0x51000);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
/* IQK setting */
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
/* path-A IQK setting */
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
/* LO calibration setting */
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
/* One shot, path A LOK & IQK */
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
/* delay x ms */
mdelay(IQK_DELAY_TIME_88E);
/* Check failed */
regeac = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
if (!(regeac & BIT(28)) &&
(((regE94 & 0x03FF0000) >> 16) != 0x142) &&
(((regE9C & 0x03FF0000) >> 16) != 0x42))
result |= 0x01;
else /* if Tx not OK, ignore Rx */
return result;
u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16);
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, u4tmp);
/* 1 RX IQK */
/* modify RXIQK mode table */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
rtl8188e_PHY_SetRFReg(adapt, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
rtl8188e_PHY_SetRFReg(adapt, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
/* IQK setting */
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x01004800);
/* path-A IQK setting */
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
/* LO calibration setting */
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
/* One shot, path A LOK & IQK */
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
/* delay x ms */
/* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
mdelay(IQK_DELAY_TIME_88E);
/* Check failed */
regeac = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
regEA4 = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord);
/* reload RF 0xdf */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
rtl8188e_PHY_SetRFReg(adapt, 0xdf, bRFRegOffsetMask, 0x180);
if (!(regeac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((regEA4 & 0x03FF0000) >> 16) != 0x132) &&
(((regeac & 0x03FF0000) >> 16) != 0x36))
result |= 0x02;
return result;
}
static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u8 final_candidate, bool txonly)
{
u32 Oldval_0, X, TX0_A, reg;
s32 Y, TX0_C;
if (final_candidate == 0xFF) {
return;
} else if (iqkok) {
Oldval_0 = (rtl8188e_PHY_QueryBBReg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
X = result[final_candidate][0];
if ((X & 0x00000200) != 0)
X = X | 0xFFFFFC00;
TX0_A = (X * Oldval_0) >> 8;
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1));
Y = result[final_candidate][1];
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
TX0_C = (Y * Oldval_0) >> 8;
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F));
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1));
if (txonly)
return;
reg = result[final_candidate][2];
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg);
reg = result[final_candidate][3] & 0x3F;
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg);
reg = (result[final_candidate][3] >> 6) & 0xF;
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
}
}
void _PHY_SaveADDARegisters(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum)
{
u32 i;
for (i = 0; i < RegisterNum; i++) {
ADDABackup[i] = rtl8188e_PHY_QueryBBReg(adapt, ADDAReg[i], bMaskDWord);
}
}
/* FIXME: return an error to caller */
static void _PHY_SaveMACRegisters(
struct adapter *adapt,
u32 *MACReg,
u32 *MACBackup
)
{
u32 i;
int res;
for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) {
u8 reg;
res = rtw_read8(adapt, MACReg[i], &reg);
if (res)
return;
MACBackup[i] = reg;
}
res = rtw_read32(adapt, MACReg[i], MACBackup + i);
(void)res;
}
static void reload_adda_reg(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegiesterNum)
{
u32 i;
for (i = 0; i < RegiesterNum; i++)
rtl8188e_PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, ADDABackup[i]);
}
static void
_PHY_ReloadMACRegisters(
struct adapter *adapt,
u32 *MACReg,
u32 *MACBackup
)
{
u32 i;
for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
rtw_write8(adapt, MACReg[i], (u8)MACBackup[i]);
rtw_write32(adapt, MACReg[i], MACBackup[i]);
}
static void
_PHY_PathADDAOn(
struct adapter *adapt,
u32 *ADDAReg)
{
u32 i;
rtl8188e_PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
for (i = 1; i < IQK_ADDA_REG_NUM; i++)
rtl8188e_PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, 0x0bdb25a0);
}
void
_PHY_MACSettingCalibration(
struct adapter *adapt,
u32 *MACReg,
u32 *MACBackup
)
{
u32 i = 0;
rtw_write8(adapt, MACReg[i], 0x3F);
for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
rtw_write8(adapt, MACReg[i], (u8)(MACBackup[i] & (~BIT(3))));
rtw_write8(adapt, MACReg[i], (u8)(MACBackup[i] & (~BIT(5))));
}
static void _PHY_PIModeSwitch(
struct adapter *adapt,
bool PIMode
)
{
u32 mode;
mode = PIMode ? 0x01000100 : 0x01000000;
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
}
static bool phy_SimularityCompare_8188E(
struct adapter *adapt,
s32 resulta[][8],
u8 c1,
u8 c2
)
{
u32 i, j, diff, sim_bitmap, bound = 0;
u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
bool result = true;
s32 tmp1 = 0, tmp2 = 0;
bound = 4;
sim_bitmap = 0;
for (i = 0; i < bound; i++) {
if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
if ((resulta[c1][i] & 0x00000200) != 0)
tmp1 = resulta[c1][i] | 0xFFFFFC00;
else
tmp1 = resulta[c1][i];
if ((resulta[c2][i] & 0x00000200) != 0)
tmp2 = resulta[c2][i] | 0xFFFFFC00;
else
tmp2 = resulta[c2][i];
} else {
tmp1 = resulta[c1][i];
tmp2 = resulta[c2][i];
}
diff = abs(tmp1 - tmp2);
if (diff > MAX_TOLERANCE) {
if ((i == 2 || i == 6) && !sim_bitmap) {
if (resulta[c1][i] + resulta[c1][i + 1] == 0)
final_candidate[(i / 4)] = c2;
else if (resulta[c2][i] + resulta[c2][i + 1] == 0)
final_candidate[(i / 4)] = c1;
else
sim_bitmap = sim_bitmap | (1 << i);
} else {
sim_bitmap = sim_bitmap | (1 << i);
}
}
}
if (sim_bitmap == 0) {
for (i = 0; i < (bound / 4); i++) {
if (final_candidate[i] != 0xFF) {
for (j = i * 4; j < (i + 1) * 4 - 2; j++)
resulta[3][j] = resulta[final_candidate[i]][j];
result = false;
}
}
return result;
} else {
if (!(sim_bitmap & 0x03)) { /* path A TX OK */
for (i = 0; i < 2; i++)
resulta[3][i] = resulta[c1][i];
}
if (!(sim_bitmap & 0x0c)) { /* path A RX OK */
for (i = 2; i < 4; i++)
resulta[3][i] = resulta[c1][i];
}
if (!(sim_bitmap & 0x30)) { /* path B TX OK */
for (i = 4; i < 6; i++)
resulta[3][i] = resulta[c1][i];
}
if (!(sim_bitmap & 0xc0)) { /* path B RX OK */
for (i = 6; i < 8; i++)
resulta[3][i] = resulta[c1][i];
}
return false;
}
}
static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t)
{
struct hal_data_8188e *pHalData = &adapt->haldata;
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
u32 i;
u8 PathAOK;
u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
/* since 92C & 92D have the different define in IQK_BB_REG */
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
};
u32 retryCount = 2;
/* Note: IQ calibration must be performed after loading */
/* PHY_REG.txt , and radio_a, radio_b.txt */
if (t == 0) {
/* Save ADDA parameters, turn Path A ADDA on */
_PHY_SaveADDARegisters(adapt, ADDA_REG, dm_odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveMACRegisters(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
}
_PHY_PathADDAOn(adapt, ADDA_REG);
if (t == 0)
dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)rtl8188e_PHY_QueryBBReg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8));
if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
/* Switch BB to PI mode to do IQ Calibration. */
_PHY_PIModeSwitch(adapt, true);
}
/* BB setting */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_RFMOD, BIT(24), 0x00);
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
rtl8188e_PHY_SetBBReg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
/* MAC settings */
_PHY_MACSettingCalibration(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup);
/* Page B init */
/* AP or IQK */
rtl8188e_PHY_SetBBReg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);
/* IQ calibration setting */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
for (i = 0; i < retryCount; i++) {
PathAOK = phy_PathA_IQK_8188E(adapt);
if (PathAOK == 0x01) {
result[t][0] = (rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16;
result[t][1] = (rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16;
break;
}
}
for (i = 0; i < retryCount; i++) {
PathAOK = phy_PathA_RxIQK(adapt);
if (PathAOK == 0x03) {
result[t][2] = (rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16;
result[t][3] = (rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16;
break;
}
}
/* Back to BB mode, load original value */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0);
if (t != 0) {
if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
/* Switch back BB to SI mode after finish IQ Calibration. */
_PHY_PIModeSwitch(adapt, false);
}
/* Reload ADDA power saving parameters */
reload_adda_reg(adapt, ADDA_REG, dm_odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
/* Reload MAC parameters */
_PHY_ReloadMACRegisters(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup);
reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
/* Restore RX initial gain */
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
/* load 0xe30 IQC default value */
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
}
}
static void phy_LCCalibrate_8188E(struct adapter *adapt)
{
u8 tmpreg;
u32 RF_Amode = 0, LC_Cal;
int res;
/* Check continuous TX and Packet TX */
res = rtw_read8(adapt, 0xd03, &tmpreg);
if (res)
return;
if ((tmpreg & 0x70) != 0) /* Deal with contisuous TX case */
rtw_write8(adapt, 0xd03, tmpreg & 0x8F); /* disable all continuous TX */
else /* Deal with Packet TX case */
rtw_write8(adapt, REG_TXPAUSE, 0xFF); /* block all queues */
if ((tmpreg & 0x70) != 0) {
/* 1. Read original RF mode */
/* Path-A */
RF_Amode = rtl8188e_PHY_QueryRFReg(adapt, RF_AC, bMask12Bits);
/* 2. Set RF mode = standby mode */
/* Path-A */
rtl8188e_PHY_SetRFReg(adapt, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000);
}
/* 3. Read RF reg18 */
LC_Cal = rtl8188e_PHY_QueryRFReg(adapt, RF_CHNLBW, bMask12Bits);
/* 4. Set LC calibration begin bit15 */
rtl8188e_PHY_SetRFReg(adapt, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000);
msleep(100);
/* Restore original situation */
if ((tmpreg & 0x70) != 0) {
/* Deal with continuous TX case */
/* Path-A */
rtw_write8(adapt, 0xd03, tmpreg);
rtl8188e_PHY_SetRFReg(adapt, RF_AC, bMask12Bits, RF_Amode);
} else {
/* Deal with Packet TX case */
rtw_write8(adapt, REG_TXPAUSE, 0x00);
}
}
void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
{
struct hal_data_8188e *pHalData = &adapt->haldata;
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
s32 result[4][8]; /* last is final result */
u8 i, final_candidate;
bool pathaok;
s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC;
bool is12simular, is13simular, is23simular;
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_RxIQExtAnta};
if (recovery) {
reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
return;
}
for (i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
result[2][i] = 0;
if ((i == 0) || (i == 2) || (i == 4) || (i == 6))
result[3][i] = 0x100;
else
result[3][i] = 0;
}
final_candidate = 0xff;
pathaok = false;
is12simular = false;
is23simular = false;
is13simular = false;
for (i = 0; i < 3; i++) {
phy_IQCalibrate_8188E(adapt, result, i);
if (i == 1) {
is12simular = phy_SimularityCompare_8188E(adapt, result, 0, 1);
if (is12simular) {
final_candidate = 0;
break;
}
}
if (i == 2) {
is13simular = phy_SimularityCompare_8188E(adapt, result, 0, 2);
if (is13simular) {
final_candidate = 0;
break;
}
is23simular = phy_SimularityCompare_8188E(adapt, result, 1, 2);
if (is23simular) {
final_candidate = 1;
} else {
final_candidate = 3;
}
}
}
for (i = 0; i < 4; i++) {
RegE94 = result[i][0];
RegE9C = result[i][1];
RegEA4 = result[i][2];
RegEB4 = result[i][4];
RegEBC = result[i][5];
}
if (final_candidate != 0xff) {
RegE94 = result[final_candidate][0];
RegE9C = result[final_candidate][1];
RegEA4 = result[final_candidate][2];
RegEB4 = result[final_candidate][4];
RegEBC = result[final_candidate][5];
dm_odm->RFCalibrateInfo.RegE94 = RegE94;
dm_odm->RFCalibrateInfo.RegE9C = RegE9C;
dm_odm->RFCalibrateInfo.RegEB4 = RegEB4;
dm_odm->RFCalibrateInfo.RegEBC = RegEBC;
pathaok = true;
} else {
dm_odm->RFCalibrateInfo.RegE94 = 0x100;
dm_odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */
dm_odm->RFCalibrateInfo.RegE9C = 0x0;
dm_odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */
}
if (RegE94 != 0)
patha_fill_iqk(adapt, pathaok, result, final_candidate, (RegEA4 == 0));
_PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
}
void PHY_LCCalibrate_8188E(struct adapter *adapt)
{
u32 timeout = 2000, timecount = 0;
struct hal_data_8188e *pHalData = &adapt->haldata;
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
while (*dm_odm->pbScanInProcess && timecount < timeout) {
mdelay(50);
timecount += 50;
}
phy_LCCalibrate_8188E(adapt);
}

149
drivers/staging/r8188eu/hal/HalPwrSeqCmd.c
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@ -1,149 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/HalPwrSeqCmd.h"
#define PWR_CMD_WRITE 0x01
/* offset: the read register offset */
/* msk: the mask of the write bits */
/* value: write value */
/* note: driver shall implement this cmd by read & msk after write */
#define PWR_CMD_POLLING 0x02
/* offset: the read register offset */
/* msk: the mask of the polled value */
/* value: the value to be polled, masked by the msd field. */
/* note: driver shall implement this cmd by */
/* do{ */
/* if ( (Read(offset) & msk) == (value & msk) ) */
/* break; */
/* } while (not timeout); */
#define PWR_CMD_DELAY 0x03
/* offset: the value to delay (in us) */
/* msk: N/A */
/* value: N/A */
struct wl_pwr_cfg {
u16 offset;
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
static struct wl_pwr_cfg rtl8188E_power_on_flow[] = {
{ 0x0006, PWR_CMD_POLLING, BIT(1), BIT(1) },
{ 0x0002, PWR_CMD_WRITE, BIT(0) | BIT(1), 0 }, /* reset BB */
{ 0x0026, PWR_CMD_WRITE, BIT(7), BIT(7) }, /* schmitt trigger */
{ 0x0005, PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN (control by DRV)*/
{ 0x0005, PWR_CMD_WRITE, BIT(4) | BIT(3), 0 }, /* disable WL suspend*/
{ 0x0005, PWR_CMD_WRITE, BIT(0), BIT(0) },
{ 0x0005, PWR_CMD_POLLING, BIT(0), 0 },
{ 0x0023, PWR_CMD_WRITE, BIT(4), 0 },
};
static struct wl_pwr_cfg rtl8188E_card_disable_flow[] = {
{ 0x001F, PWR_CMD_WRITE, 0xFF, 0 }, /* turn off RF */
{ 0x0023, PWR_CMD_WRITE, BIT(4), BIT(4) }, /* LDO Sleep mode */
{ 0x0005, PWR_CMD_WRITE, BIT(1), BIT(1) }, /* turn off MAC by HW state machine */
{ 0x0005, PWR_CMD_POLLING, BIT(1), 0 },
{ 0x0026, PWR_CMD_WRITE, BIT(7), BIT(7) }, /* schmitt trigger */
{ 0x0005, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /* enable WL suspend */
{ 0x0007, PWR_CMD_WRITE, 0xFF, 0 }, /* enable bandgap mbias in suspend */
{ 0x0041, PWR_CMD_WRITE, BIT(4), 0 }, /* Clear SIC_EN register */
{ 0xfe10, PWR_CMD_WRITE, BIT(4), BIT(4) }, /* Set USB suspend enable local register */
};
/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
static struct wl_pwr_cfg rtl8188E_enter_lps_flow[] = {
{ 0x0522, PWR_CMD_WRITE, 0xFF, 0x7F },/* Tx Pause */
{ 0x05F8, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */
{ 0x05F9, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */
{ 0x05FA, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */
{ 0x05FB, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */
{ 0x0002, PWR_CMD_WRITE, BIT(0), 0 }, /* CCK and OFDM are disabled, clocks are gated */
{ 0x0002, PWR_CMD_DELAY, 0, 0 },
{ 0x0100, PWR_CMD_WRITE, 0xFF, 0x3F }, /* Reset MAC TRX */
{ 0x0101, PWR_CMD_WRITE, BIT(1), 0 }, /* check if removed later */
{ 0x0553, PWR_CMD_WRITE, BIT(5), BIT(5) }, /* Respond TxOK to scheduler */
};
u8 HalPwrSeqCmdParsing(struct adapter *padapter, enum r8188eu_pwr_seq seq)
{
struct wl_pwr_cfg pwrcfgcmd = {0};
struct wl_pwr_cfg *pwrseqcmd;
u8 poll_bit = false;
u8 idx, num_steps;
u8 value = 0;
u32 offset = 0;
u32 poll_count = 0; /* polling autoload done. */
u32 max_poll_count = 5000;
int res;
switch (seq) {
case PWR_ON_FLOW:
pwrseqcmd = rtl8188E_power_on_flow;
num_steps = ARRAY_SIZE(rtl8188E_power_on_flow);
break;
case DISABLE_FLOW:
pwrseqcmd = rtl8188E_card_disable_flow;
num_steps = ARRAY_SIZE(rtl8188E_card_disable_flow);
break;
case LPS_ENTER_FLOW:
pwrseqcmd = rtl8188E_enter_lps_flow;
num_steps = ARRAY_SIZE(rtl8188E_enter_lps_flow);
break;
default:
return false;
}
for (idx = 0; idx < num_steps; idx++) {
pwrcfgcmd = pwrseqcmd[idx];
switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
case PWR_CMD_WRITE:
offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
/* Read the value from system register */
res = rtw_read8(padapter, offset, &value);
if (res)
return false;
value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd));
/* Write the value back to system register */
rtw_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
poll_bit = false;
offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
do {
res = rtw_read8(padapter, offset, &value);
if (res)
return false;
value &= GET_PWR_CFG_MASK(pwrcfgcmd);
if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))
poll_bit = true;
else
udelay(10);
if (poll_count++ > max_poll_count)
return false;
} while (!poll_bit);
break;
case PWR_CMD_DELAY:
udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));
break;
default:
break;
}
}
return true;
}

139
drivers/staging/r8188eu/hal/hal_com.c
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@ -1,139 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/hal_intf.h"
#include "../include/hal_com.h"
#include "../include/rtl8188e_hal.h"
#define _HAL_INIT_C_
#define CHAN_PLAN_HW 0x80
u8 /* return the final channel plan decision */
hal_com_get_channel_plan(struct adapter *padapter, u8 hw_channel_plan,
u8 sw_channel_plan, u8 def_channel_plan,
bool load_fail)
{
u8 sw_cfg;
u8 chnlplan;
sw_cfg = true;
if (!load_fail) {
if (!rtw_is_channel_plan_valid(sw_channel_plan))
sw_cfg = false;
if (hw_channel_plan & CHAN_PLAN_HW)
sw_cfg = false;
}
if (sw_cfg)
chnlplan = sw_channel_plan;
else
chnlplan = hw_channel_plan & (~CHAN_PLAN_HW);
if (!rtw_is_channel_plan_valid(chnlplan))
chnlplan = def_channel_plan;
return chnlplan;
}
u8 MRateToHwRate(u8 rate)
{
u8 ret = DESC_RATE1M;
switch (rate) {
/* CCK and OFDM non-HT rates */
case IEEE80211_CCK_RATE_1MB:
ret = DESC_RATE1M;
break;
case IEEE80211_CCK_RATE_2MB:
ret = DESC_RATE2M;
break;
case IEEE80211_CCK_RATE_5MB:
ret = DESC_RATE5_5M;
break;
case IEEE80211_CCK_RATE_11MB:
ret = DESC_RATE11M;
break;
case IEEE80211_OFDM_RATE_6MB:
ret = DESC_RATE6M;
break;
case IEEE80211_OFDM_RATE_9MB:
ret = DESC_RATE9M;
break;
case IEEE80211_OFDM_RATE_12MB:
ret = DESC_RATE12M;
break;
case IEEE80211_OFDM_RATE_18MB:
ret = DESC_RATE18M;
break;
case IEEE80211_OFDM_RATE_24MB:
ret = DESC_RATE24M;
break;
case IEEE80211_OFDM_RATE_36MB:
ret = DESC_RATE36M;
break;
case IEEE80211_OFDM_RATE_48MB:
ret = DESC_RATE48M;
break;
case IEEE80211_OFDM_RATE_54MB:
ret = DESC_RATE54M;
break;
default:
break;
}
return ret;
}
void HalSetBrateCfg(struct adapter *adapt, u8 *brates, u16 *rate_cfg)
{
u8 i, is_brate, brate;
for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
is_brate = brates[i] & IEEE80211_BASIC_RATE_MASK;
brate = brates[i] & 0x7f;
if (is_brate) {
switch (brate) {
case IEEE80211_CCK_RATE_1MB:
*rate_cfg |= RATE_1M;
break;
case IEEE80211_CCK_RATE_2MB:
*rate_cfg |= RATE_2M;
break;
case IEEE80211_CCK_RATE_5MB:
*rate_cfg |= RATE_5_5M;
break;
case IEEE80211_CCK_RATE_11MB:
*rate_cfg |= RATE_11M;
break;
case IEEE80211_OFDM_RATE_6MB:
*rate_cfg |= RATE_6M;
break;
case IEEE80211_OFDM_RATE_9MB:
*rate_cfg |= RATE_9M;
break;
case IEEE80211_OFDM_RATE_12MB:
*rate_cfg |= RATE_12M;
break;
case IEEE80211_OFDM_RATE_18MB:
*rate_cfg |= RATE_18M;
break;
case IEEE80211_OFDM_RATE_24MB:
*rate_cfg |= RATE_24M;
break;
case IEEE80211_OFDM_RATE_36MB:
*rate_cfg |= RATE_36M;
break;
case IEEE80211_OFDM_RATE_48MB:
*rate_cfg |= RATE_48M;
break;
case IEEE80211_OFDM_RATE_54MB:
*rate_cfg |= RATE_54M;
break;
}
}
}
}

50
drivers/staging/r8188eu/hal/hal_intf.c
View File

@ -1,50 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#define _HAL_INTF_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/hal_intf.h"
uint rtw_hal_init(struct adapter *adapt)
{
adapt->hw_init_completed = false;
if (rtl8188eu_hal_init(adapt) != _SUCCESS)
return _FAIL;
adapt->hw_init_completed = true;
if (adapt->registrypriv.notch_filter == 1)
hal_notch_filter_8188e(adapt, 1);
return _SUCCESS;
}
uint rtw_hal_deinit(struct adapter *adapt)
{
uint status = _SUCCESS;
status = rtl8188eu_hal_deinit(adapt);
if (status == _SUCCESS)
adapt->hw_init_completed = false;
return status;
}
void rtw_hal_update_ra_mask(struct adapter *adapt, u32 mac_id, u8 rssi_level)
{
struct mlme_priv *pmlmepriv = &adapt->mlmepriv;
if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &adapt->stapriv;
if (mac_id >= 2)
psta = pstapriv->sta_aid[(mac_id - 1) - 1];
if (psta)
add_RATid(adapt, psta, 0);/* todo: based on rssi_level*/
} else {
UpdateHalRAMask8188EUsb(adapt, mac_id, rssi_level);
}
}

821
drivers/staging/r8188eu/hal/odm.c
View File

@ -1,821 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/drv_types.h"
/* avoid to warn in FreeBSD ==> To DO modify */
static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
/* UL DL */
{0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
{0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
{0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
{0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
{0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
{0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
{0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
{0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
{0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */
{0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
};
/* Global var */
u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
0x7f8001fe, /* 0, +6.0dB */
0x788001e2, /* 1, +5.5dB */
0x71c001c7, /* 2, +5.0dB */
0x6b8001ae, /* 3, +4.5dB */
0x65400195, /* 4, +4.0dB */
0x5fc0017f, /* 5, +3.5dB */
0x5a400169, /* 6, +3.0dB */
0x55400155, /* 7, +2.5dB */
0x50800142, /* 8, +2.0dB */
0x4c000130, /* 9, +1.5dB */
0x47c0011f, /* 10, +1.0dB */
0x43c0010f, /* 11, +0.5dB */
0x40000100, /* 12, +0dB */
0x3c8000f2, /* 13, -0.5dB */
0x390000e4, /* 14, -1.0dB */
0x35c000d7, /* 15, -1.5dB */
0x32c000cb, /* 16, -2.0dB */
0x300000c0, /* 17, -2.5dB */
0x2d4000b5, /* 18, -3.0dB */
0x2ac000ab, /* 19, -3.5dB */
0x288000a2, /* 20, -4.0dB */
0x26000098, /* 21, -4.5dB */
0x24000090, /* 22, -5.0dB */
0x22000088, /* 23, -5.5dB */
0x20000080, /* 24, -6.0dB */
0x1e400079, /* 25, -6.5dB */
0x1c800072, /* 26, -7.0dB */
0x1b00006c, /* 27. -7.5dB */
0x19800066, /* 28, -8.0dB */
0x18000060, /* 29, -8.5dB */
0x16c0005b, /* 30, -9.0dB */
0x15800056, /* 31, -9.5dB */
0x14400051, /* 32, -10.0dB */
0x1300004c, /* 33, -10.5dB */
0x12000048, /* 34, -11.0dB */
0x11000044, /* 35, -11.5dB */
0x10000040, /* 36, -12.0dB */
0x0f00003c,/* 37, -12.5dB */
0x0e400039,/* 38, -13.0dB */
0x0d800036,/* 39, -13.5dB */
0x0cc00033,/* 40, -14.0dB */
0x0c000030,/* 41, -14.5dB */
0x0b40002d,/* 42, -15.0dB */
};
u8 cck_swing_table[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
};
#define RxDefaultAnt1 0x65a9
#define RxDefaultAnt2 0x569a
static void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
{
struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
struct adapter *adapter = pDM_Odm->Adapter;
pDM_DigTable->CurIGValue = (u8)rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N);
pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
pDM_DigTable->CurCCK_CCAThres = 0x83;
pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
pDM_DigTable->LargeFAHit = 0;
pDM_DigTable->Recover_cnt = 0;
pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
pDM_DigTable->bMediaConnect_0 = false;
/* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
pDM_Odm->bDMInitialGainEnable = true;
}
static void odm_DIG(struct odm_dm_struct *pDM_Odm)
{
struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
u8 DIG_Dynamic_MIN;
u8 DIG_MaxOfMin;
bool FirstConnect, FirstDisConnect;
u8 dm_dig_max, dm_dig_min;
u8 CurrentIGI = pDM_DigTable->CurIGValue;
if (*pDM_Odm->pbScanInProcess)
return;
/* add by Neil Chen to avoid PSD is processing */
if (!pDM_Odm->bDMInitialGainEnable)
return;
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
/* 1 Boundary Decision */
dm_dig_max = DM_DIG_MAX_NIC;
dm_dig_min = DM_DIG_MIN_NIC;
DIG_MaxOfMin = DM_DIG_MAX_AP;
if (pDM_Odm->bLinked) {
/* 2 8723A Series, offset need to be 10 */
/* 2 Modify DIG upper bound */
if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
pDM_DigTable->rx_gain_range_max = dm_dig_max;
else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
pDM_DigTable->rx_gain_range_max = dm_dig_min;
else
pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
/* 2 Modify DIG lower bound */
if (pDM_Odm->bOneEntryOnly) {
if (pDM_Odm->RSSI_Min < dm_dig_min)
DIG_Dynamic_MIN = dm_dig_min;
else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
DIG_Dynamic_MIN = DIG_MaxOfMin;
else
DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
} else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) {
/* 1 Lower Bound for 88E AntDiv */
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
DIG_Dynamic_MIN = (u8)pDM_DigTable->AntDiv_RSSI_max;
} else {
DIG_Dynamic_MIN = dm_dig_min;
}
} else {
pDM_DigTable->rx_gain_range_max = dm_dig_max;
DIG_Dynamic_MIN = dm_dig_min;
}
/* 1 Modify DIG lower bound, deal with abnormally large false alarm */
if (pFalseAlmCnt->Cnt_all > 10000) {
if (pDM_DigTable->LargeFAHit != 3)
pDM_DigTable->LargeFAHit++;
if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
pDM_DigTable->ForbiddenIGI = CurrentIGI;
pDM_DigTable->LargeFAHit = 1;
}
if (pDM_DigTable->LargeFAHit >= 3) {
if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max)
pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
else
pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
}
} else {
/* Recovery mechanism for IGI lower bound */
if (pDM_DigTable->Recover_cnt != 0) {
pDM_DigTable->Recover_cnt--;
} else {
if (pDM_DigTable->LargeFAHit < 3) {
if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
} else {
pDM_DigTable->ForbiddenIGI--;
pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
}
} else {
pDM_DigTable->LargeFAHit = 0;
}
}
}
/* 1 Adjust initial gain by false alarm */
if (pDM_Odm->bLinked) {
if (FirstConnect) {
CurrentIGI = pDM_Odm->RSSI_Min;
} else {
if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
}
} else {
if (FirstDisConnect) {
CurrentIGI = pDM_DigTable->rx_gain_range_min;
} else {
/* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
if (pFalseAlmCnt->Cnt_all > 10000)
CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
else if (pFalseAlmCnt->Cnt_all > 8000)
CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
else if (pFalseAlmCnt->Cnt_all < 500)
CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
}
}
/* 1 Check initial gain by upper/lower bound */
if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
CurrentIGI = pDM_DigTable->rx_gain_range_max;
if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
CurrentIGI = pDM_DigTable->rx_gain_range_min;
/* 2 High power RSSI threshold */
ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
}
static void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
{
struct adapter *adapter = pDM_Odm->Adapter;
pDM_Odm->bCckHighPower = (bool)rtl8188e_PHY_QueryBBReg(adapter, 0x824, BIT(9));
pDM_Odm->RFPathRxEnable = (u8)rtl8188e_PHY_QueryBBReg(adapter, 0xc04, 0x0F);
}
static void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
{
u8 EntryCnt = 0;
u8 i;
struct sta_info *pEntry;
if (*pDM_Odm->pBandWidth == HT_CHANNEL_WIDTH_40) {
if (*pDM_Odm->pSecChOffset == 1)
pDM_Odm->ControlChannel = *pDM_Odm->pChannel - 2;
else if (*pDM_Odm->pSecChOffset == 2)
pDM_Odm->ControlChannel = *pDM_Odm->pChannel + 2;
} else {
pDM_Odm->ControlChannel = *pDM_Odm->pChannel;
}
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
pEntry = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(pEntry))
EntryCnt++;
}
if (EntryCnt == 1)
pDM_Odm->bOneEntryOnly = true;
else
pDM_Odm->bOneEntryOnly = false;
}
static void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
{
struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
pOdmRA->RATRState = DM_RATR_STA_INIT;
pOdmRA->HighRSSIThresh = 50;
pOdmRA->LowRSSIThresh = 20;
}
static void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
{
u8 i;
struct adapter *pAdapter = pDM_Odm->Adapter;
if (pAdapter->bDriverStopped)
return;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(pstat)) {
if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level))
rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
}
}
}
static void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm)
{
struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
pDM_PSTable->pre_rf_state = RF_MAX;
pDM_PSTable->cur_rf_state = RF_MAX;
pDM_PSTable->initialize = 0;
}
static void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
{
u32 ret_value;
struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
struct adapter *adapter = pDM_Odm->Adapter;
/* hold ofdm counter */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
FalseAlmCnt->Cnt_Fast_Fsync = (ret_value & 0xffff);
FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff);
FalseAlmCnt->Cnt_Parity_Fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
FalseAlmCnt->Cnt_Rate_Illegal = (ret_value & 0xffff);
FalseAlmCnt->Cnt_Crc8_fail = ((ret_value & 0xffff0000) >> 16);
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
FalseAlmCnt->Cnt_Mcs_fail = (ret_value & 0xffff);
FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord);
FalseAlmCnt->Cnt_BW_LSC = (ret_value & 0xffff);
FalseAlmCnt->Cnt_BW_USC = ((ret_value & 0xffff0000) >> 16);
/* hold cck counter */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
FalseAlmCnt->Cnt_Cck_fail = ret_value;
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
FalseAlmCnt->Cnt_CCK_CCA = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8);
FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
FalseAlmCnt->Cnt_SB_Search_fail +
FalseAlmCnt->Cnt_Parity_Fail +
FalseAlmCnt->Cnt_Rate_Illegal +
FalseAlmCnt->Cnt_Crc8_fail +
FalseAlmCnt->Cnt_Mcs_fail +
FalseAlmCnt->Cnt_Cck_fail);
FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
}
static void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
{
u8 CurCCK_CCAThres;
struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
if (pDM_Odm->bLinked) {
if (pDM_Odm->RSSI_Min > 25) {
CurCCK_CCAThres = 0xcd;
} else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
CurCCK_CCAThres = 0x83;
} else {
if (FalseAlmCnt->Cnt_Cck_fail > 1000)
CurCCK_CCAThres = 0x83;
else
CurCCK_CCAThres = 0x40;
}
} else {
if (FalseAlmCnt->Cnt_Cck_fail > 1000)
CurCCK_CCAThres = 0x83;
else
CurCCK_CCAThres = 0x40;
}
ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
}
static void FindMinimumRSSI(struct adapter *pAdapter)
{
struct hal_data_8188e *pHalData = &pAdapter->haldata;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
/* 1 1.Determine the minimum RSSI */
if (!check_fwstate(pmlmepriv, _FW_LINKED) &&
pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)
pdmpriv->MinUndecoratedPWDBForDM = 0;
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
static void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
{
struct adapter *Adapter = pDM_Odm->Adapter;
struct hal_data_8188e *pHalData = &Adapter->haldata;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
int i;
int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
u8 sta_cnt = 0;
u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
struct sta_info *psta;
if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
return;
if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
return;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
psta = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(psta) &&
(psta->state & WIFI_ASOC_STATE) &&
!is_broadcast_ether_addr(psta->hwaddr) &&
memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16));
}
}
for (i = 0; i < sta_cnt; i++) {
if (PWDB_rssi[i] != (0)) {
if (pHalData->fw_ractrl) {
/* Report every sta's RSSI to FW */
} else {
ODM_RA_SetRSSI_8188E(
&pHalData->odmpriv, (PWDB_rssi[i] & 0xFF), (u8)((PWDB_rssi[i] >> 16) & 0xFF));
}
}
}
if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
else
pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
FindMinimumRSSI(Adapter);
pHalData->odmpriv.RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
}
static void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm)
{
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
}
static void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
{
if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
return;
ODM_AntennaDiversityInit_88E(pDM_Odm);
}
static void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
{
if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
return;
ODM_AntennaDiversity_88E(pDM_Odm);
}
static void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
{
struct adapter *Adapter = pDM_Odm->Adapter;
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
Adapter->recvpriv.bIsAnyNonBEPkts = false;
}
static void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
{
struct adapter *Adapter = pDM_Odm->Adapter;
u32 trafficIndex;
u32 edca_param;
u64 cur_tx_bytes = 0;
u64 cur_rx_bytes = 0;
u8 bbtchange = false;
struct hal_data_8188e *pHalData = &Adapter->haldata;
struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
struct recv_priv *precvpriv = &Adapter->recvpriv;
struct registry_priv *pregpriv = &Adapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
if (pregpriv->wifi_spec == 1)
goto dm_CheckEdcaTurbo_EXIT;
if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
goto dm_CheckEdcaTurbo_EXIT;
/* Check if the status needs to be changed. */
if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
/* traffic, TX or RX */
if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
if (cur_tx_bytes > (cur_rx_bytes << 2)) {
/* Uplink TP is present. */
trafficIndex = UP_LINK;
} else {
/* Balance TP is present. */
trafficIndex = DOWN_LINK;
}
} else {
if (cur_rx_bytes > (cur_tx_bytes << 2)) {
/* Downlink TP is present. */
trafficIndex = DOWN_LINK;
} else {
/* Balance TP is present. */
trafficIndex = UP_LINK;
}
}
if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
else
edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
}
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
} else {
/* Turn Off EDCA turbo here. */
/* Restore original EDCA according to the declaration of AP. */
if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
}
}
dm_CheckEdcaTurbo_EXIT:
/* Set variables for next time. */
precvpriv->bIsAnyNonBEPkts = false;
pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
precvpriv->last_rx_bytes = precvpriv->rx_bytes;
}
/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
{
/* 2012.05.03 Luke: For all IC series */
odm_CommonInfoSelfInit(pDM_Odm);
odm_DIGInit(pDM_Odm);
odm_RateAdaptiveMaskInit(pDM_Odm);
odm_DynamicBBPowerSavingInit(pDM_Odm);
odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
ODM_EdcaTurboInit(pDM_Odm);
ODM_RAInfo_Init_all(pDM_Odm);
if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
odm_InitHybridAntDiv(pDM_Odm);
}
/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
/* You can not add any dummy function here, be care, you can only use DM structure */
/* to perform any new ODM_DM. */
void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
{
/* 2012.05.03 Luke: For all IC series */
odm_CommonInfoSelfUpdate(pDM_Odm);
odm_FalseAlarmCounterStatistics(pDM_Odm);
odm_RSSIMonitorCheck(pDM_Odm);
odm_DIG(pDM_Odm);
odm_CCKPacketDetectionThresh(pDM_Odm);
if (*pDM_Odm->pbPowerSaving)
return;
odm_RefreshRateAdaptiveMask(pDM_Odm);
if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
odm_HwAntDiv(pDM_Odm);
ODM_TXPowerTrackingCheck(pDM_Odm);
odm_EdcaTurboCheck(pDM_Odm);
}
/* Init /.. Fixed HW value. Only init time. */
void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value)
{
/* This section is used for init value */
switch (CmnInfo) {
/* Fixed ODM value. */
case ODM_CMNINFO_MP_TEST_CHIP:
pDM_Odm->bIsMPChip = (u8)Value;
break;
case ODM_CMNINFO_RF_ANTENNA_TYPE:
pDM_Odm->AntDivType = (u8)Value;
break;
default:
/* do nothing */
break;
}
/* Tx power tracking BB swing table. */
/* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */
pDM_Odm->BbSwingIdxOfdmCurrent = 12;
pDM_Odm->BbSwingFlagOfdm = false;
}
void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
{
struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
struct adapter *adapter = pDM_Odm->Adapter;
if (pDM_DigTable->CurIGValue != CurrentIGI) {
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
pDM_DigTable->CurIGValue = CurrentIGI;
}
}
void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
{
struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */
rtw_write8(pDM_Odm->Adapter, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres);
pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
}
void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
{
struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
struct adapter *adapter = pDM_Odm->Adapter;
u8 Rssi_Up_bound = 30;
u8 Rssi_Low_bound = 25;
if (pDM_PSTable->initialize == 0) {
pDM_PSTable->reg_874 = (rtl8188e_PHY_QueryBBReg(adapter, 0x874, bMaskDWord) & 0x1CC000) >> 14;
pDM_PSTable->reg_c70 = (rtl8188e_PHY_QueryBBReg(adapter, 0xc70, bMaskDWord) & BIT(3)) >> 3;
pDM_PSTable->reg_85c = (rtl8188e_PHY_QueryBBReg(adapter, 0x85c, bMaskDWord) & 0xFF000000) >> 24;
pDM_PSTable->reg_a74 = (rtl8188e_PHY_QueryBBReg(adapter, 0xa74, bMaskDWord) & 0xF000) >> 12;
pDM_PSTable->initialize = 1;
}
if (!bForceInNormal) {
if (pDM_Odm->RSSI_Min != 0xFF) {
if (pDM_PSTable->pre_rf_state == RF_Normal) {
if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
pDM_PSTable->cur_rf_state = RF_Save;
else
pDM_PSTable->cur_rf_state = RF_Normal;
} else {
if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
pDM_PSTable->cur_rf_state = RF_Normal;
else
pDM_PSTable->cur_rf_state = RF_Save;
}
} else {
pDM_PSTable->cur_rf_state = RF_MAX;
}
} else {
pDM_PSTable->cur_rf_state = RF_Normal;
}
if (pDM_PSTable->pre_rf_state != pDM_PSTable->cur_rf_state) {
if (pDM_PSTable->cur_rf_state == RF_Save) {
rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
rtl8188e_PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
} else {
rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1CC000, pDM_PSTable->reg_874);
rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), pDM_PSTable->reg_c70);
rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->reg_85c);
rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->reg_a74);
rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x0);
}
pDM_PSTable->pre_rf_state = pDM_PSTable->cur_rf_state;
}
}
u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
{
struct sta_info *pEntry;
u32 rate_bitmap = 0x0fffffff;
u8 WirelessMode;
pEntry = pDM_Odm->pODM_StaInfo[macid];
if (!IS_STA_VALID(pEntry))
return ra_mask;
WirelessMode = pEntry->wireless_mode;
switch (WirelessMode) {
case ODM_WM_B:
if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
rate_bitmap = 0x0000000d;
else
rate_bitmap = 0x0000000f;
break;
case (ODM_WM_B | ODM_WM_G):
if (rssi_level == DM_RATR_STA_HIGH)
rate_bitmap = 0x00000f00;
else if (rssi_level == DM_RATR_STA_MIDDLE)
rate_bitmap = 0x00000ff0;
else
rate_bitmap = 0x00000ff5;
break;
case (ODM_WM_B | ODM_WM_G | ODM_WM_N24G):
if (rssi_level == DM_RATR_STA_HIGH) {
rate_bitmap = 0x000f0000;
} else if (rssi_level == DM_RATR_STA_MIDDLE) {
rate_bitmap = 0x000ff000;
} else {
if (*pDM_Odm->pBandWidth == HT_CHANNEL_WIDTH_40)
rate_bitmap = 0x000ff015;
else
rate_bitmap = 0x000ff005;
}
break;
default:
/* case WIRELESS_11_24N: */
rate_bitmap = 0x0fffffff;
break;
}
return rate_bitmap;
}
/* Return Value: bool */
/* - true: RATRState is changed. */
bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
{
struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
const u8 GoUpGap = 5;
u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
u8 RATRState;
/* Threshold Adjustment: */
/* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
/* Here GoUpGap is added to solve the boundary's level alternation issue. */
switch (*pRATRState) {
case DM_RATR_STA_INIT:
case DM_RATR_STA_HIGH:
break;
case DM_RATR_STA_MIDDLE:
HighRSSIThreshForRA += GoUpGap;
break;
case DM_RATR_STA_LOW:
HighRSSIThreshForRA += GoUpGap;
LowRSSIThreshForRA += GoUpGap;
break;
default:
break;
}
/* Decide RATRState by RSSI. */
if (RSSI > HighRSSIThreshForRA)
RATRState = DM_RATR_STA_HIGH;
else if (RSSI > LowRSSIThreshForRA)
RATRState = DM_RATR_STA_MIDDLE;
else
RATRState = DM_RATR_STA_LOW;
if (*pRATRState != RATRState || bForceUpdate) {
*pRATRState = RATRState;
return true;
}
return false;
}
void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
{
struct adapter *Adapter = pDM_Odm->Adapter;
if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */
rtl8188e_PHY_SetRFReg(Adapter, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
return;
} else {
odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
}
}

349
drivers/staging/r8188eu/hal/odm_HWConfig.c
View File

@ -1,349 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/drv_types.h"
static u8 odm_query_rxpwrpercentage(s8 antpower)
{
if ((antpower <= -100) || (antpower >= 20))
return 0;
else if (antpower >= 0)
return 100;
else
return 100 + antpower;
}
static s32 odm_signal_scale_mapping(struct odm_dm_struct *dm_odm, s32 currsig)
{
s32 retsig;
if (currsig >= 51 && currsig <= 100)
retsig = 100;
else if (currsig >= 41 && currsig <= 50)
retsig = 80 + ((currsig - 40) * 2);
else if (currsig >= 31 && currsig <= 40)
retsig = 66 + (currsig - 30);
else if (currsig >= 21 && currsig <= 30)
retsig = 54 + (currsig - 20);
else if (currsig >= 10 && currsig <= 20)
retsig = 42 + (((currsig - 10) * 2) / 3);
else if (currsig >= 5 && currsig <= 9)
retsig = 22 + (((currsig - 5) * 3) / 2);
else if (currsig >= 1 && currsig <= 4)
retsig = 6 + (((currsig - 1) * 3) / 2);
else
retsig = currsig;
return retsig;
}
static u8 odm_evm_db_to_percentage(s8 value)
{
/* -33dB~0dB to 0%~99% */
s8 ret_val = clamp(-value, 0, 33) * 3;
if (ret_val == 99)
ret_val = 100;
return ret_val;
}
static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm,
struct phy_info *pPhyInfo,
u8 *pPhyStatus,
struct odm_per_pkt_info *pPktinfo,
struct adapter *adapt)
{
u8 i, Max_spatial_stream;
s8 rx_pwr[4], rx_pwr_all = 0;
u8 EVM, PWDB_ALL = 0;
u8 RSSI, total_rssi = 0;
u8 isCCKrate = 0;
u8 rf_rx_num = 0;
u8 cck_highpwr = 0;
u8 LNA_idx, VGA_idx;
struct phy_status_rpt *pPhyStaRpt = (struct phy_status_rpt *)pPhyStatus;
isCCKrate = pPktinfo->Rate >= DESC92C_RATE1M && pPktinfo->Rate <= DESC92C_RATE11M;
if (isCCKrate) {
u8 cck_agc_rpt;
/* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */
cck_highpwr = dm_odm->bCckHighPower;
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a;
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
/* The RSSI formula should be modified according to the gain table */
/* In 88E, cck_highpwr is always set to 1 */
LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
VGA_idx = (cck_agc_rpt & 0x1F);
switch (LNA_idx) {
case 7:
if (VGA_idx <= 27)
rx_pwr_all = -100 + 2 * (27 - VGA_idx); /* VGA_idx = 27~2 */
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2 * (2 - VGA_idx); /* VGA_idx = 2~0 */
break;
case 5:
rx_pwr_all = -42 + 2 * (7 - VGA_idx); /* VGA_idx = 7~5 */
break;
case 4:
rx_pwr_all = -36 + 2 * (7 - VGA_idx); /* VGA_idx = 7~4 */
break;
case 3:
rx_pwr_all = -24 + 2 * (7 - VGA_idx); /* VGA_idx = 7~0 */
break;
case 2:
if (cck_highpwr)
rx_pwr_all = -12 + 2 * (5 - VGA_idx); /* VGA_idx = 5~0 */
else
rx_pwr_all = -6 + 2 * (5 - VGA_idx);
break;
case 1:
rx_pwr_all = 8 - 2 * VGA_idx;
break;
case 0:
rx_pwr_all = 14 - 2 * VGA_idx;
break;
default:
break;
}
rx_pwr_all += 6;
PWDB_ALL = odm_query_rxpwrpercentage(rx_pwr_all);
if (!cck_highpwr) {
if (PWDB_ALL >= 80)
PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80;
else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20))
PWDB_ALL += 3;
if (PWDB_ALL > 100)
PWDB_ALL = 100;
}
pPhyInfo->RxPWDBAll = PWDB_ALL;
pPhyInfo->recvpower = rx_pwr_all;
/* (3) Get Signal Quality (EVM) */
if (pPktinfo->bPacketMatchBSSID) {
u8 SQ, SQ_rpt;
if (pPhyInfo->RxPWDBAll > 40) {
SQ = 100;
} else {
SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all;
if (SQ_rpt > 64)
SQ = 0;
else if (SQ_rpt < 20)
SQ = 100;
else
SQ = ((64 - SQ_rpt) * 100) / 44;
}
pPhyInfo->SignalQuality = SQ;
}
} else { /* is OFDM rate */
/* (1)Get RSSI for HT rate */
for (i = RF_PATH_A; i < RF_PATH_MAX; i++) {
/* 2008/01/30 MH we will judge RF RX path now. */
if (dm_odm->RFPathRxEnable & BIT(i))
rf_rx_num++;
rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain & 0x3F) * 2) - 110;
if (i == RF_PATH_A)
adapt->signal_strength = rx_pwr[i];
pPhyInfo->RxPwr[i] = rx_pwr[i];
/* Translate DBM to percentage. */
RSSI = odm_query_rxpwrpercentage(rx_pwr[i]);
total_rssi += RSSI;
pPhyInfo->RxMIMOSignalStrength[i] = (u8)RSSI;
/* Get Rx snr value in DB */
dm_odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i] / 2);
}
/* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110;
PWDB_ALL = odm_query_rxpwrpercentage(rx_pwr_all);
pPhyInfo->RxPWDBAll = PWDB_ALL;
pPhyInfo->RxPower = rx_pwr_all;
pPhyInfo->recvpower = rx_pwr_all;
/* (3)EVM of HT rate */
if (pPktinfo->Rate >= DESC92C_RATEMCS8 && pPktinfo->Rate <= DESC92C_RATEMCS15)
Max_spatial_stream = 2; /* both spatial stream make sense */
else
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
for (i = 0; i < Max_spatial_stream; i++) {
/* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
/* fill most significant bit to "zero" when doing shifting operation which may change a negative */
/* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
EVM = odm_evm_db_to_percentage((pPhyStaRpt->stream_rxevm[i])); /* dbm */
if (pPktinfo->bPacketMatchBSSID) {
if (i == RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
}
}
}
/* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
/* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
if (isCCKrate) {
pPhyInfo->SignalStrength = (u8)(odm_signal_scale_mapping(dm_odm, PWDB_ALL));/* PWDB_ALL; */
} else {
if (rf_rx_num != 0)
pPhyInfo->SignalStrength = (u8)(odm_signal_scale_mapping(dm_odm, total_rssi /= rf_rx_num));
}
/* For 88E HW Antenna Diversity */
dm_odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel;
dm_odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b;
dm_odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2;
}
static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm,
struct phy_info *pPhyInfo,
struct odm_per_pkt_info *pPktinfo)
{
s32 UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK;
s32 UndecoratedSmoothedOFDM, RSSI_Ave;
u8 isCCKrate = 0;
u8 RSSI_max, RSSI_min, i;
u32 OFDM_pkt = 0;
u32 Weighting = 0;
struct sta_info *pEntry;
u8 antsel_tr_mux;
struct fast_ant_train *pDM_FatTable = &dm_odm->DM_FatTable;
if (pPktinfo->StationID == 0xFF)
return;
pEntry = dm_odm->pODM_StaInfo[pPktinfo->StationID];
if (!IS_STA_VALID(pEntry))
return;
if ((!pPktinfo->bPacketMatchBSSID))
return;
isCCKrate = pPktinfo->Rate >= DESC92C_RATE1M && pPktinfo->Rate <= DESC92C_RATE11M;
/* Smart Antenna Debug Message------------------ */
if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) {
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2 << 2) |
(pDM_FatTable->antsel_rx_keep_1 << 1) | pDM_FatTable->antsel_rx_keep_0;
ODM_AntselStatistics_88E(dm_odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll);
}
}
/* Smart Antenna Debug Message------------------ */
UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK;
UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM;
UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
if (!isCCKrate) { /* ofdm rate */
if (pPhyInfo->RxMIMOSignalStrength[RF_PATH_B] == 0) {
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A];
} else {
if (pPhyInfo->RxMIMOSignalStrength[RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[RF_PATH_B]) {
RSSI_max = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A];
RSSI_min = pPhyInfo->RxMIMOSignalStrength[RF_PATH_B];
} else {
RSSI_max = pPhyInfo->RxMIMOSignalStrength[RF_PATH_B];
RSSI_min = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A];
}
if ((RSSI_max - RSSI_min) < 3)
RSSI_Ave = RSSI_max;
else if ((RSSI_max - RSSI_min) < 6)
RSSI_Ave = RSSI_max - 1;
else if ((RSSI_max - RSSI_min) < 10)
RSSI_Ave = RSSI_max - 2;
else
RSSI_Ave = RSSI_max - 3;
}
/* 1 Process OFDM RSSI */
if (UndecoratedSmoothedOFDM <= 0) { /* initialize */
UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll;
} else {
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM) {
UndecoratedSmoothedOFDM =
(((UndecoratedSmoothedOFDM) * (Rx_Smooth_Factor - 1)) +
(RSSI_Ave)) / (Rx_Smooth_Factor);
UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1;
} else {
UndecoratedSmoothedOFDM =
(((UndecoratedSmoothedOFDM) * (Rx_Smooth_Factor - 1)) +
(RSSI_Ave)) / (Rx_Smooth_Factor);
}
}
pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap << 1) | BIT(0);
} else {
RSSI_Ave = pPhyInfo->RxPWDBAll;
/* 1 Process CCK RSSI */
if (UndecoratedSmoothedCCK <= 0) { /* initialize */
UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll;
} else {
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK) {
UndecoratedSmoothedCCK =
((UndecoratedSmoothedCCK * (Rx_Smooth_Factor - 1)) +
pPhyInfo->RxPWDBAll) / Rx_Smooth_Factor;
UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1;
} else {
UndecoratedSmoothedCCK =
((UndecoratedSmoothedCCK * (Rx_Smooth_Factor - 1)) +
pPhyInfo->RxPWDBAll) / Rx_Smooth_Factor;
}
}
pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap << 1;
}
/* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
if (pEntry->rssi_stat.ValidBit >= 64)
pEntry->rssi_stat.ValidBit = 64;
else
pEntry->rssi_stat.ValidBit++;
for (i = 0; i < pEntry->rssi_stat.ValidBit; i++)
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap >> i) & BIT(0);
if (pEntry->rssi_stat.ValidBit == 64) {
Weighting = ((OFDM_pkt << 4) > 64) ? 64 : (OFDM_pkt << 4);
UndecoratedSmoothedPWDB = (Weighting * UndecoratedSmoothedOFDM + (64 - Weighting) * UndecoratedSmoothedCCK) >> 6;
} else {
if (pEntry->rssi_stat.ValidBit != 0)
UndecoratedSmoothedPWDB = (OFDM_pkt * UndecoratedSmoothedOFDM +
(pEntry->rssi_stat.ValidBit - OFDM_pkt) *
UndecoratedSmoothedCCK) / pEntry->rssi_stat.ValidBit;
else
UndecoratedSmoothedPWDB = 0;
}
pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK;
pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM;
pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
}
}
/* Endianness before calling this API */
void ODM_PhyStatusQuery(struct odm_dm_struct *dm_odm,
struct phy_info *pPhyInfo,
u8 *pPhyStatus,
struct odm_per_pkt_info *pPktinfo,
struct adapter *adapt)
{
odm_RxPhyStatus92CSeries_Parsing(dm_odm, pPhyInfo, pPhyStatus, pPktinfo, adapt);
odm_Process_RSSIForDM(dm_odm, pPhyInfo, pPktinfo);
}

264
drivers/staging/r8188eu/hal/odm_RTL8188E.c
View File

@ -1,264 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/drv_types.h"
static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
/* MAC Setting */
value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
/* CCK Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
}
static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
/* MAC Setting */
value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
/* CCK Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
/* Tx Settings */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
/* antenna mapping table */
if (!dm_odm->bIsMPChip) { /* testchip */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
} else { /* MPchip */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
}
}
static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
/* MAC Setting */
value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x4c, bMaskDWord);
rtl8188e_PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord);
rtl8188e_PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
/* Match MAC ADDR */
rtl8188e_PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
rtl8188e_PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
rtl8188e_PHY_SetBBReg(adapter, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
rtl8188e_PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
if (!dm_odm->bIsMPChip) { /* testchip */
rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
} else { /* MPchip */
rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
}
/* Default Ant Setting when no fast training */
rtl8188e_PHY_SetBBReg(adapter, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
/* Enter Training state */
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
rtl8188e_PHY_SetBBReg(adapter, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
}
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
{
if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
odm_RX_HWAntDivInit(dm_odm);
else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
odm_TRX_HWAntDivInit(dm_odm);
else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
odm_FastAntTrainingInit(dm_odm);
}
void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
{
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
struct adapter *adapter = dm_odm->Adapter;
u32 DefaultAnt, OptionalAnt;
if (dm_fat_tbl->RxIdleAnt != Ant) {
if (Ant == MAIN_ANT) {
DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
} else {
DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
}
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT(6) | BIT(7), DefaultAnt); /* Resp Tx */
} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
}
}
dm_fat_tbl->RxIdleAnt = Ant;
if (Ant != MAIN_ANT)
pr_info("RxIdleAnt=AUX_ANT\n");
}
static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
{
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
u8 TargetAnt;
if (Ant == MAIN_ANT)
TargetAnt = MAIN_ANT_CG_TRX;
else
TargetAnt = AUX_ANT_CG_TRX;
dm_fat_tbl->antsel_a[MacId] = TargetAnt & BIT(0);
dm_fat_tbl->antsel_b[MacId] = (TargetAnt & BIT(1)) >> 1;
dm_fat_tbl->antsel_c[MacId] = (TargetAnt & BIT(2)) >> 2;
}
void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId)
{
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]);
SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]);
SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]);
}
}
void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll)
{
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
dm_fat_tbl->MainAnt_Cnt[MacId]++;
} else {
dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
dm_fat_tbl->AuxAnt_Cnt[MacId]++;
}
} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
dm_fat_tbl->MainAnt_Cnt[MacId]++;
} else {
dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
dm_fat_tbl->AuxAnt_Cnt[MacId]++;
}
}
}
static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
{
u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI;
u32 Main_RSSI, Aux_RSSI;
u8 RxIdleAnt = 0, TargetAnt = 7;
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
struct sta_info *pEntry;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
pEntry = dm_odm->pODM_StaInfo[i];
if (IS_STA_VALID(pEntry)) {
/* 2 Calculate RSSI per Antenna */
Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i] / dm_fat_tbl->MainAnt_Cnt[i]) : 0;
Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i] / dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT;
/* 2 Select MaxRSSI for DIG */
LocalMaxRSSI = max(Main_RSSI, Aux_RSSI);
if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
AntDivMaxRSSI = LocalMaxRSSI;
if (LocalMaxRSSI > MaxRSSI)
MaxRSSI = LocalMaxRSSI;
/* 2 Select RX Idle Antenna */
if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
Main_RSSI = Aux_RSSI;
else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
Aux_RSSI = Main_RSSI;
LocalMinRSSI = min(Main_RSSI, Aux_RSSI);
if (LocalMinRSSI < MinRSSI) {
MinRSSI = LocalMinRSSI;
RxIdleAnt = TargetAnt;
}
/* 2 Select TRX Antenna */
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i);
}
dm_fat_tbl->MainAnt_Sum[i] = 0;
dm_fat_tbl->AuxAnt_Sum[i] = 0;
dm_fat_tbl->MainAnt_Cnt[i] = 0;
dm_fat_tbl->AuxAnt_Cnt[i] = 0;
}
/* 2 Set RX Idle Antenna */
ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
pDM_DigTable->RSSI_max = MaxRSSI;
}
void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
{
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
struct adapter *adapter = dm_odm->Adapter;
if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
return;
if (!dm_odm->bLinked) {
if (dm_fat_tbl->bBecomeLinked) {
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
}
return;
} else {
if (!dm_fat_tbl->bBecomeLinked) {
/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
}
}
if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
odm_HWAntDiv(dm_odm);
}

694
drivers/staging/r8188eu/hal/rtl8188e_cmd.c
View File

@ -1,694 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _RTL8188E_CMD_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtw_ioctl_set.h"
#include "../include/rtl8188e_hal.h"
#define RTL88E_MAX_H2C_BOX_NUMS 4
#define RTL88E_MAX_CMD_LEN 7
#define RTL88E_MESSAGE_BOX_SIZE 4
#define RTL88E_EX_MESSAGE_BOX_SIZE 4
static u8 _is_fw_read_cmd_down(struct adapter *adapt, u8 msgbox_num)
{
u8 read_down = false, reg;
int retry_cnts = 100;
int res;
u8 valid;
do {
res = rtw_read8(adapt, REG_HMETFR, &reg);
if (res)
continue;
valid = reg & BIT(msgbox_num);
if (0 == valid)
read_down = true;
} while ((!read_down) && (retry_cnts--));
return read_down;
}
/*****************************************
* H2C Msg format :
* 0x1DF - 0x1D0
*| 31 - 8 | 7-5 4 - 0 |
*| h2c_msg |Class_ID CMD_ID |
*
* Extend 0x1FF - 0x1F0
*|31 - 0 |
*|ext_msg|
******************************************/
static s32 FillH2CCmd_88E(struct adapter *adapt, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
{
u8 bcmd_down = false;
s32 retry_cnts = 100;
u8 h2c_box_num;
u32 msgbox_addr;
u32 msgbox_ex_addr;
struct hal_data_8188e *haldata = &adapt->haldata;
u8 cmd_idx, ext_cmd_len;
u32 h2c_cmd = 0;
u32 h2c_cmd_ex = 0;
if (!adapt->bFWReady)
return _FAIL;
if (!pCmdBuffer || CmdLen > RTL88E_MAX_CMD_LEN || adapt->bSurpriseRemoved)
return _FAIL;
/* pay attention to if race condition happened in H2C cmd setting. */
do {
h2c_box_num = haldata->LastHMEBoxNum;
if (!_is_fw_read_cmd_down(adapt, h2c_box_num))
return _FAIL;
*(u8 *)(&h2c_cmd) = ElementID;
if (CmdLen <= 3) {
memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, CmdLen);
} else {
memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, 3);
ext_cmd_len = CmdLen - 3;
memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer + 3, ext_cmd_len);
/* Write Ext command */
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * RTL88E_EX_MESSAGE_BOX_SIZE);
for (cmd_idx = 0; cmd_idx < ext_cmd_len; cmd_idx++) {
rtw_write8(adapt, msgbox_ex_addr + cmd_idx, *((u8 *)(&h2c_cmd_ex) + cmd_idx));
}
}
/* Write command */
msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * RTL88E_MESSAGE_BOX_SIZE);
for (cmd_idx = 0; cmd_idx < RTL88E_MESSAGE_BOX_SIZE; cmd_idx++) {
rtw_write8(adapt, msgbox_addr + cmd_idx, *((u8 *)(&h2c_cmd) + cmd_idx));
}
bcmd_down = true;
haldata->LastHMEBoxNum = (h2c_box_num + 1) % RTL88E_MAX_H2C_BOX_NUMS;
} while ((!bcmd_down) && (retry_cnts--));
return _SUCCESS;
}
u8 rtl8188e_set_raid_cmd(struct adapter *adapt, u32 mask)
{
u8 buf[3];
u8 res = _SUCCESS;
struct hal_data_8188e *haldata = &adapt->haldata;
if (haldata->fw_ractrl) {
__le32 lmask;
memset(buf, 0, 3);
lmask = cpu_to_le32(mask);
memcpy(buf, &lmask, 3);
FillH2CCmd_88E(adapt, H2C_DM_MACID_CFG, 3, buf);
} else {
res = _FAIL;
}
return res;
}
/* bitmap[0:27] = tx_rate_bitmap */
/* bitmap[28:31]= Rate Adaptive id */
/* arg[0:4] = macid */
/* arg[5] = Short GI */
void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
{
struct hal_data_8188e *haldata = &pAdapter->haldata;
u8 macid, raid, short_gi_rate = false;
macid = arg & 0x1f;
raid = (bitmap >> 28) & 0x0f;
bitmap &= 0x0fffffff;
if (rssi_level != DM_RATR_STA_INIT)
bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, macid, bitmap, rssi_level);
bitmap |= ((raid << 28) & 0xf0000000);
short_gi_rate = (arg & BIT(5)) ? true : false;
raid = (bitmap >> 28) & 0x0f;
bitmap &= 0x0fffffff;
ODM_RA_UpdateRateInfo_8188E(&haldata->odmpriv, macid, raid, bitmap, short_gi_rate);
}
void rtl8188e_set_FwPwrMode_cmd(struct adapter *adapt, u8 Mode)
{
struct setpwrmode_parm H2CSetPwrMode;
struct pwrctrl_priv *pwrpriv = &adapt->pwrctrlpriv;
u8 RLBM = 0; /* 0:Min, 1:Max, 2:User define */
switch (Mode) {
case PS_MODE_ACTIVE:
H2CSetPwrMode.Mode = 0;
break;
case PS_MODE_MIN:
H2CSetPwrMode.Mode = 1;
break;
case PS_MODE_MAX:
RLBM = 1;
H2CSetPwrMode.Mode = 1;
break;
case PS_MODE_DTIM:
RLBM = 2;
H2CSetPwrMode.Mode = 1;
break;
case PS_MODE_UAPSD_WMM:
H2CSetPwrMode.Mode = 2;
break;
default:
H2CSetPwrMode.Mode = 0;
break;
}
H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps << 4) & 0xf0) | (RLBM & 0x0f));
H2CSetPwrMode.AwakeInterval = 1;
H2CSetPwrMode.bAllQueueUAPSD = adapt->registrypriv.uapsd_enable;
if (Mode > 0)
H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
else
H2CSetPwrMode.PwrState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
FillH2CCmd_88E(adapt, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);
}
void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, u16 mstatus_rpt)
{
__le16 mst_rpt = cpu_to_le16(mstatus_rpt);
FillH2CCmd_88E(adapt, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt);
}
static void ConstructBeacon(struct adapter *adapt, u8 *pframe, u32 *pLength)
{
struct ieee80211_hdr *pwlanhdr;
__le16 *fctrl;
u32 rate_len, pktlen;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
pwlanhdr = (struct ieee80211_hdr *)pframe;
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
eth_broadcast_addr(pwlanhdr->addr1);
memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN);
memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
SetFrameSubType(pframe, WIFI_BEACON);
pframe += sizeof(struct ieee80211_hdr_3addr);
pktlen = sizeof(struct ieee80211_hdr_3addr);
/* timestamp will be inserted by hardware */
pframe += 8;
pktlen += 8;
/* beacon interval: 2 bytes */
memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
pframe += 2;
pktlen += 2;
/* capability info: 2 bytes */
memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
pframe += 2;
pktlen += 2;
if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
pktlen += cur_network->IELength - sizeof(struct ndis_802_11_fixed_ie);
memcpy(pframe, cur_network->IEs + sizeof(struct ndis_802_11_fixed_ie), pktlen);
goto _ConstructBeacon;
}
/* below for ad-hoc mode */
/* SSID */
pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
/* supported rates... */
rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
/* DS parameter set */
pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&cur_network->Configuration.DSConfig, &pktlen);
if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
u32 ATIMWindow;
/* IBSS Parameter Set... */
ATIMWindow = 0;
pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
}
/* todo: ERP IE */
/* EXTERNDED SUPPORTED RATE */
if (rate_len > 8)
pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
/* todo:HT for adhoc */
_ConstructBeacon:
if ((pktlen + TXDESC_SIZE) > 512)
return;
*pLength = pktlen;
}
static void ConstructPSPoll(struct adapter *adapt, u8 *pframe, u32 *pLength)
{
struct ieee80211_hdr *pwlanhdr;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
__le16 *fctrl;
pwlanhdr = (struct ieee80211_hdr *)pframe;
/* Frame control. */
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
SetPwrMgt(fctrl);
SetFrameSubType(pframe, WIFI_PSPOLL);
/* AID. */
SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
/* BSSID. */
memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
/* TA. */
memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN);
*pLength = 16;
}
static void ConstructNullFunctionData(struct adapter *adapt, u8 *pframe,
u32 *pLength,
u8 *StaAddr,
u8 bQoS,
u8 AC,
u8 bEosp,
u8 bForcePowerSave)
{
struct ieee80211_hdr *pwlanhdr;
__le16 *fctrl;
u32 pktlen;
struct mlme_priv *pmlmepriv = &adapt->mlmepriv;
struct wlan_network *cur_network = &pmlmepriv->cur_network;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
pwlanhdr = (struct ieee80211_hdr *)pframe;
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
if (bForcePowerSave)
SetPwrMgt(fctrl);
switch (cur_network->network.InfrastructureMode) {
case Ndis802_11Infrastructure:
SetToDs(fctrl);
memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN);
memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);
break;
case Ndis802_11APMode:
SetFrDs(fctrl);
memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
memcpy(pwlanhdr->addr2, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
memcpy(pwlanhdr->addr3, myid(&adapt->eeprompriv), ETH_ALEN);
break;
case Ndis802_11IBSS:
default:
memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN);
memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
break;
}
SetSeqNum(pwlanhdr, 0);
if (bQoS) {
struct ieee80211_qos_hdr *pwlanqoshdr;
SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
pwlanqoshdr = (struct ieee80211_qos_hdr *)pframe;
SetPriority(&pwlanqoshdr->qos_ctrl, AC);
SetEOSP(&pwlanqoshdr->qos_ctrl, bEosp);
pktlen = sizeof(struct ieee80211_qos_hdr);
} else {
SetFrameSubType(pframe, WIFI_DATA_NULL);
pktlen = sizeof(struct ieee80211_qos_hdr);
}
*pLength = pktlen;
}
static void ConstructProbeRsp(struct adapter *adapt, u8 *pframe, u32 *pLength, u8 *StaAddr, bool bHideSSID)
{
struct ieee80211_hdr *pwlanhdr;
__le16 *fctrl;
u8 *mac, *bssid;
u32 pktlen;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
pwlanhdr = (struct ieee80211_hdr *)pframe;
mac = myid(&adapt->eeprompriv);
bssid = cur_network->MacAddress;
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
SetFrameSubType(fctrl, WIFI_PROBERSP);
pktlen = sizeof(struct ieee80211_hdr_3addr);
pframe += pktlen;
if (cur_network->IELength > MAX_IE_SZ)
return;
memcpy(pframe, cur_network->IEs, cur_network->IELength);
pframe += cur_network->IELength;
pktlen += cur_network->IELength;
*pLength = pktlen;
}
/* To check if reserved page content is destroyed by beacon because beacon is too large. */
/* 2010.06.23. Added by tynli. */
void CheckFwRsvdPageContent(struct adapter *Adapter)
{
}
/* */
/* Description: Fill the reserved packets that FW will use to RSVD page. */
/* Now we just send 4 types packet to rsvd page. */
/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */
/* Input: */
/* bDLFinished - false: At the first time we will send all the packets as a large packet to Hw, */
/* so we need to set the packet length to total length. */
/* true: At the second time, we should send the first packet (default:beacon) */
/* to Hw again and set the length in descriptor to the real beacon length. */
/* 2009.10.15 by tynli. */
static void SetFwRsvdPagePkt(struct adapter *adapt, bool bDLFinished)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv;
struct mlme_ext_priv *pmlmeext;
struct mlme_ext_info *pmlmeinfo;
u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength;
u32 NullDataLength, QosNullLength;
u8 *ReservedPagePacket;
u8 PageNum, PageNeed, TxDescLen;
u16 BufIndex;
u32 TotalPacketLen;
struct rsvdpage_loc RsvdPageLoc;
ReservedPagePacket = kzalloc(1000, GFP_KERNEL);
if (!ReservedPagePacket)
return;
pxmitpriv = &adapt->xmitpriv;
pmlmeext = &adapt->mlmeextpriv;
pmlmeinfo = &pmlmeext->mlmext_info;
TxDescLen = TXDESC_SIZE;
PageNum = 0;
/* 3 (1) beacon * 2 pages */
BufIndex = TXDESC_OFFSET;
ConstructBeacon(adapt, &ReservedPagePacket[BufIndex], &BeaconLength);
/* When we count the first page size, we need to reserve description size for the RSVD */
/* packet, it will be filled in front of the packet in TXPKTBUF. */
PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);
/* To reserved 2 pages for beacon buffer. 2010.06.24. */
if (PageNeed == 1)
PageNeed += 1;
PageNum += PageNeed;
BufIndex += PageNeed * 128;
/* 3 (2) ps-poll *1 page */
RsvdPageLoc.LocPsPoll = PageNum;
ConstructPSPoll(adapt, &ReservedPagePacket[BufIndex], &PSPollLength);
rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], PSPollLength, true, false);
PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength);
PageNum += PageNeed;
BufIndex += PageNeed * 128;
/* 3 (3) null data * 1 page */
RsvdPageLoc.LocNullData = PageNum;
ConstructNullFunctionData(adapt, &ReservedPagePacket[BufIndex], &NullDataLength, get_my_bssid(&pmlmeinfo->network), false, 0, 0, false);
rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], NullDataLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength);
PageNum += PageNeed;
BufIndex += PageNeed * 128;
/* 3 (4) probe response * 1page */
RsvdPageLoc.LocProbeRsp = PageNum;
ConstructProbeRsp(adapt, &ReservedPagePacket[BufIndex], &ProbeRspLength, get_my_bssid(&pmlmeinfo->network), false);
rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], ProbeRspLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength);
PageNum += PageNeed;
BufIndex += PageNeed * 128;
/* 3 (5) Qos null data */
RsvdPageLoc.LocQosNull = PageNum;
ConstructNullFunctionData(adapt, &ReservedPagePacket[BufIndex],
&QosNullLength, get_my_bssid(&pmlmeinfo->network), true, 0, 0, false);
rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], QosNullLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength);
PageNum += PageNeed;
TotalPacketLen = BufIndex + QosNullLength;
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (!pmgntframe)
goto exit;
/* update attribute */
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(adapt, pattrib);
pattrib->qsel = 0x10;
pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET;
pattrib->pktlen = pattrib->last_txcmdsz;
memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);
rtl8188eu_mgnt_xmit(adapt, pmgntframe);
FillH2CCmd_88E(adapt, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc);
exit:
kfree(ReservedPagePacket);
}
void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus)
{
struct hal_data_8188e *haldata = &adapt->haldata;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
bool bSendBeacon = false;
bool bcn_valid = false;
u8 DLBcnCount = 0;
u32 poll = 0;
u8 reg;
int res;
if (mstatus == 1) {
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
rtw_write16(adapt, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid));
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
/* Set REG_CR bit 8. DMA beacon by SW. */
haldata->RegCR_1 |= BIT(0);
rtw_write8(adapt, REG_CR + 1, haldata->RegCR_1);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
/* 2010.05.11. Added by tynli. */
res = rtw_read8(adapt, REG_BCN_CTRL, &reg);
if (res)
return;
rtw_write8(adapt, REG_BCN_CTRL, reg & (~BIT(3)));
res = rtw_read8(adapt, REG_BCN_CTRL, &reg);
if (res)
return;
rtw_write8(adapt, REG_BCN_CTRL, reg | BIT(4));
if (haldata->RegFwHwTxQCtrl & BIT(6))
bSendBeacon = true;
/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
rtw_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl & (~BIT(6))));
haldata->RegFwHwTxQCtrl &= (~BIT(6));
clear_beacon_valid_bit(adapt);
DLBcnCount = 0;
poll = 0;
do {
/* download rsvd page. */
SetFwRsvdPagePkt(adapt, false);
DLBcnCount++;
do {
yield();
/* mdelay(10); */
/* check rsvd page download OK. */
bcn_valid = get_beacon_valid_bit(adapt);
poll++;
} while (!bcn_valid && (poll % 10) != 0 && !adapt->bSurpriseRemoved && !adapt->bDriverStopped);
} while (!bcn_valid && DLBcnCount <= 100 && !adapt->bSurpriseRemoved && !adapt->bDriverStopped);
/* */
/* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */
/* because we need to free the Tx BCN Desc which is used by the first reserved page packet. */
/* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */
/* the beacon TCB in the following code. 2011.11.23. by tynli. */
/* */
/* Enable Bcn */
res = rtw_read8(adapt, REG_BCN_CTRL, &reg);
if (res)
return;
rtw_write8(adapt, REG_BCN_CTRL, reg | BIT(3));
res = rtw_read8(adapt, REG_BCN_CTRL, &reg);
if (res)
return;
rtw_write8(adapt, REG_BCN_CTRL, reg & (~BIT(4)));
/* To make sure that if there exists an adapter which would like to send beacon. */
/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bSendBeacon) {
rtw_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl | BIT(6)));
haldata->RegFwHwTxQCtrl |= BIT(6);
}
/* Update RSVD page location H2C to Fw. */
if (bcn_valid)
clear_beacon_valid_bit(adapt);
/* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
haldata->RegCR_1 &= (~BIT(0));
rtw_write8(adapt, REG_CR + 1, haldata->RegCR_1);
}
}
void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state)
{
struct hal_data_8188e *haldata = &adapt->haldata;
struct wifidirect_info *pwdinfo = &adapt->wdinfo;
struct P2P_PS_Offload_t *p2p_ps_offload = &haldata->p2p_ps_offload;
u8 i;
switch (p2p_ps_state) {
case P2P_PS_DISABLE:
memset(p2p_ps_offload, 0, 1);
break;
case P2P_PS_ENABLE:
/* update CTWindow value. */
if (pwdinfo->ctwindow > 0) {
p2p_ps_offload->CTWindow_En = 1;
rtw_write8(adapt, REG_P2P_CTWIN, pwdinfo->ctwindow);
}
/* hw only support 2 set of NoA */
for (i = 0; i < pwdinfo->noa_num; i++) {
/* To control the register setting for which NOA */
rtw_write8(adapt, REG_NOA_DESC_SEL, (i << 4));
if (i == 0)
p2p_ps_offload->NoA0_En = 1;
else
p2p_ps_offload->NoA1_En = 1;
/* config P2P NoA Descriptor Register */
rtw_write32(adapt, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
rtw_write32(adapt, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
rtw_write32(adapt, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
rtw_write8(adapt, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
}
if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
/* rst p2p circuit */
rtw_write8(adapt, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->Offload_En = 1;
if (pwdinfo->role == P2P_ROLE_GO) {
p2p_ps_offload->role = 1;
p2p_ps_offload->AllStaSleep = 0;
} else {
p2p_ps_offload->role = 0;
}
p2p_ps_offload->discovery = 0;
}
break;
case P2P_PS_SCAN:
p2p_ps_offload->discovery = 1;
break;
case P2P_PS_SCAN_DONE:
p2p_ps_offload->discovery = 0;
pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
break;
default:
break;
}
FillH2CCmd_88E(adapt, H2C_PS_P2P_OFFLOAD, 1, (u8 *)p2p_ps_offload);
}

146
drivers/staging/r8188eu/hal/rtl8188e_dm.c
View File

@ -1,146 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
/* This file is for 92CE/92CU dynamic mechanism only */
#define _RTL8188E_DM_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtl8188e_hal.h"
/* Initialize GPIO setting registers */
static void dm_InitGPIOSetting(struct adapter *Adapter)
{
u8 tmp1byte;
int res;
res = rtw_read8(Adapter, REG_GPIO_MUXCFG, &tmp1byte);
if (res)
return;
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
}
/* */
/* functions */
/* */
static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
{
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
struct hal_data_8188e *hal_data = &Adapter->haldata;
struct odm_dm_struct *dm_odm = &hal_data->odmpriv;
struct dm_priv *pdmpriv = &hal_data->dmpriv;
int i;
pdmpriv->InitODMFlag = ODM_BB_RSSI_MONITOR;
if (hal_data->AntDivCfg)
pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
dm_odm->SupportAbility = pdmpriv->InitODMFlag;
dm_odm->pWirelessMode = &pmlmeext->cur_wireless_mode;
dm_odm->pSecChOffset = &hal_data->nCur40MhzPrimeSC;
dm_odm->pBandWidth = &hal_data->CurrentChannelBW;
dm_odm->pChannel = &hal_data->CurrentChannel;
dm_odm->pbScanInProcess = &pmlmepriv->bScanInProcess;
dm_odm->pbPowerSaving = &pwrctrlpriv->bpower_saving;
ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType);
for (i = 0; i < NUM_STA; i++)
dm_odm->pODM_StaInfo[i] = NULL;
}
void rtl8188e_InitHalDm(struct adapter *Adapter)
{
struct hal_data_8188e *hal_data = &Adapter->haldata;
struct odm_dm_struct *dm_odm = &hal_data->odmpriv;
dm_InitGPIOSetting(Adapter);
Update_ODM_ComInfo_88E(Adapter);
ODM_DMInit(dm_odm);
}
void rtl8188e_HalDmWatchDog(struct adapter *Adapter)
{
u8 hw_init_completed = Adapter->hw_init_completed;
struct hal_data_8188e *hal_data = &Adapter->haldata;
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
u8 bLinked = false;
if (!hw_init_completed)
return;
if ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))) {
if (Adapter->stapriv.asoc_sta_count > 2)
bLinked = true;
} else {/* Station mode */
if (check_fwstate(pmlmepriv, _FW_LINKED))
bLinked = true;
}
hal_data->odmpriv.bLinked = bLinked;
ODM_DMWatchdog(&hal_data->odmpriv);
}
void rtl8188e_init_dm_priv(struct adapter *Adapter)
{
struct hal_data_8188e *hal_data = &Adapter->haldata;
struct dm_priv *pdmpriv = &hal_data->dmpriv;
struct odm_dm_struct *dm_odm = &hal_data->odmpriv;
memset(pdmpriv, 0, sizeof(struct dm_priv));
memset(dm_odm, 0, sizeof(*dm_odm));
dm_odm->Adapter = Adapter;
ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(hal_data->VersionID));
ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType);
}
/* Add new function to reset the state of antenna diversity before link. */
/* Compare RSSI for deciding antenna */
void AntDivCompare8188E(struct adapter *Adapter, struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src)
{
struct hal_data_8188e *hal_data = &Adapter->haldata;
if (0 != hal_data->AntDivCfg) {
/* select optimum_antenna for before linked =>For antenna diversity */
if (dst->Rssi >= src->Rssi) {/* keep org parameter */
src->Rssi = dst->Rssi;
src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
}
}
}
/* Add new function to reset the state of antenna diversity before link. */
u8 AntDivBeforeLink8188E(struct adapter *Adapter)
{
struct hal_data_8188e *hal_data = &Adapter->haldata;
struct odm_dm_struct *dm_odm = &hal_data->odmpriv;
struct sw_ant_switch *dm_swat_tbl = &dm_odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
/* Condition that does not need to use antenna diversity. */
if (hal_data->AntDivCfg == 0)
return false;
if (check_fwstate(pmlmepriv, _FW_LINKED))
return false;
if (dm_swat_tbl->SWAS_NoLink_State == 0) {
/* switch channel */
dm_swat_tbl->SWAS_NoLink_State = 1;
dm_swat_tbl->CurAntenna = (dm_swat_tbl->CurAntenna == Antenna_A) ? Antenna_B : Antenna_A;
rtw_antenna_select_cmd(Adapter, dm_swat_tbl->CurAntenna, false);
return true;
} else {
dm_swat_tbl->SWAS_NoLink_State = 0;
return false;
}
}

922
drivers/staging/r8188eu/hal/rtl8188e_hal_init.c
View File

@ -1,922 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _HAL_INIT_C_
#include "../include/drv_types.h"
#include "../include/rtw_efuse.h"
#include "../include/rtl8188e_hal.h"
#include "../include/rtw_iol.h"
#include "../include/usb_ops.h"
#include "../include/rtw_fw.h"
static void iol_mode_enable(struct adapter *padapter, u8 enable)
{
u8 reg_0xf0 = 0;
int res;
if (enable) {
/* Enable initial offload */
res = rtw_read8(padapter, REG_SYS_CFG, &reg_0xf0);
if (res)
return;
rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 | SW_OFFLOAD_EN);
if (!padapter->bFWReady)
rtw_reset_8051(padapter);
} else {
/* disable initial offload */
res = rtw_read8(padapter, REG_SYS_CFG, &reg_0xf0);
if (res)
return;
rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
}
}
static s32 iol_execute(struct adapter *padapter, u8 control)
{
s32 status = _FAIL;
u8 reg_0x88 = 0;
unsigned long timeout;
int res;
control = control & 0x0f;
res = rtw_read8(padapter, REG_HMEBOX_E0, &reg_0x88);
if (res)
return _FAIL;
rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88 | control);
timeout = jiffies + msecs_to_jiffies(1000);
do {
res = rtw_read8(padapter, REG_HMEBOX_E0, &reg_0x88);
if (res)
continue;
if (!(reg_0x88 & control))
break;
} while (time_before(jiffies, timeout));
res = rtw_read8(padapter, REG_HMEBOX_E0, &reg_0x88);
if (res)
return _FAIL;
status = (reg_0x88 & control) ? _FAIL : _SUCCESS;
if (reg_0x88 & control << 4)
status = _FAIL;
return status;
}
static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
{
s32 rst = _SUCCESS;
iol_mode_enable(padapter, 1);
rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
rst = iol_execute(padapter, CMD_INIT_LLT);
iol_mode_enable(padapter, 0);
return rst;
}
static void
efuse_phymap_to_logical(u8 *phymap, u16 _size_byte, u8 *pbuf)
{
u8 *efuseTbl = NULL;
u8 rtemp8;
u16 eFuse_Addr = 0;
u8 offset, wren;
u16 i, j;
u16 **eFuseWord = NULL;
u8 u1temp = 0;
efuseTbl = kzalloc(EFUSE_MAP_LEN_88E, GFP_KERNEL);
if (!efuseTbl)
goto exit;
eFuseWord = rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
if (!eFuseWord)
goto exit;
/* 0. Refresh efuse init map as all oxFF. */
for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
eFuseWord[i][j] = 0xFFFF;
/* */
/* 1. Read the first byte to check if efuse is empty!!! */
/* */
/* */
rtemp8 = *(phymap + eFuse_Addr);
if (rtemp8 != 0xFF) {
eFuse_Addr++;
} else {
goto exit;
}
/* */
/* 2. Read real efuse content. Filter PG header and every section data. */
/* */
while ((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
/* Check PG header for section num. */
if ((rtemp8 & 0x1F) == 0x0F) { /* extended header */
u1temp = ((rtemp8 & 0xE0) >> 5);
rtemp8 = *(phymap + eFuse_Addr);
if ((rtemp8 & 0x0F) == 0x0F) {
eFuse_Addr++;
rtemp8 = *(phymap + eFuse_Addr);
if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
eFuse_Addr++;
continue;
} else {
offset = ((rtemp8 & 0xF0) >> 1) | u1temp;
wren = (rtemp8 & 0x0F);
eFuse_Addr++;
}
} else {
offset = ((rtemp8 >> 4) & 0x0f);
wren = (rtemp8 & 0x0f);
}
if (offset < EFUSE_MAX_SECTION_88E) {
/* Get word enable value from PG header */
for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
/* Check word enable condition in the section */
if (!(wren & 0x01)) {
rtemp8 = *(phymap + eFuse_Addr);
eFuse_Addr++;
eFuseWord[offset][i] = (rtemp8 & 0xff);
if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
break;
rtemp8 = *(phymap + eFuse_Addr);
eFuse_Addr++;
eFuseWord[offset][i] |= (((u16)rtemp8 << 8) & 0xff00);
if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
break;
}
wren >>= 1;
}
}
/* Read next PG header */
rtemp8 = *(phymap + eFuse_Addr);
if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
eFuse_Addr++;
}
}
/* */
/* 3. Collect 16 sections and 4 word unit into Efuse map. */
/* */
for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) {
for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
efuseTbl[(i * 8) + (j * 2)] = (eFuseWord[i][j] & 0xff);
efuseTbl[(i * 8) + ((j * 2) + 1)] = ((eFuseWord[i][j] >> 8) & 0xff);
}
}
/* */
/* 4. Copy from Efuse map to output pointer memory!!! */
/* */
memcpy(pbuf, efuseTbl, _size_byte);
exit:
kfree(efuseTbl);
kfree(eFuseWord);
}
/* FIXME: add error handling in callers */
static int efuse_read_phymap_from_txpktbuf(
struct adapter *adapter,
u8 *content, /* buffer to store efuse physical map */
u16 *size /* for efuse content: the max byte to read. will update to byte read */
)
{
unsigned long timeout;
__le32 lo32 = 0, hi32 = 0;
u16 len = 0, count = 0;
int i = 0, res;
u16 limit = *size;
u8 reg;
u8 *pos = content;
u32 reg32;
rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
while (1) {
rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, i);
rtw_write8(adapter, REG_TXPKTBUF_DBG, 0);
timeout = jiffies + msecs_to_jiffies(1000);
do {
res = rtw_read8(adapter, REG_TXPKTBUF_DBG, &reg);
if (res)
continue;
if (reg)
break;
msleep(1);
} while (time_before(jiffies, timeout));
/* data from EEPROM needs to be in LE */
res = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L, &reg32);
if (res)
return res;
lo32 = cpu_to_le32(reg32);
res = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H, &reg32);
if (res)
return res;
hi32 = cpu_to_le32(reg32);
if (i == 0) {
u16 reg;
/* Although lenc is only used in a debug statement,
* do not remove it as the rtw_read16() call consumes
* 2 bytes from the EEPROM source.
*/
res = rtw_read16(adapter, REG_PKTBUF_DBG_DATA_L, &reg);
if (res)
return res;
len = le32_to_cpu(lo32) & 0x0000ffff;
limit = (len - 2 < limit) ? len - 2 : limit;
memcpy(pos, ((u8 *)&lo32) + 2, (limit >= count + 2) ? 2 : limit - count);
count += (limit >= count + 2) ? 2 : limit - count;
pos = content + count;
} else {
memcpy(pos, ((u8 *)&lo32), (limit >= count + 4) ? 4 : limit - count);
count += (limit >= count + 4) ? 4 : limit - count;
pos = content + count;
}
if (limit > count && len - 2 > count) {
memcpy(pos, (u8 *)&hi32, (limit >= count + 4) ? 4 : limit - count);
count += (limit >= count + 4) ? 4 : limit - count;
pos = content + count;
}
if (limit <= count || len - 2 <= count)
break;
i++;
}
rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
*size = count;
return 0;
}
static s32 iol_read_efuse(struct adapter *padapter, u16 size_byte, u8 *logical_map)
{
s32 status = _FAIL;
u8 physical_map[512];
u16 size = 512;
rtw_write8(padapter, REG_TDECTRL + 1, 0);
memset(physical_map, 0xFF, 512);
rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
status = iol_execute(padapter, CMD_READ_EFUSE_MAP);
if (status == _SUCCESS)
efuse_read_phymap_from_txpktbuf(padapter, physical_map, &size);
efuse_phymap_to_logical(physical_map, size_byte, logical_map);
return status;
}
s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
{
s32 result = _SUCCESS;
if (rtw_IOL_applied(padapter)) {
iol_mode_enable(padapter, 1);
result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
if (result == _SUCCESS)
result = iol_execute(padapter, CMD_EFUSE_PATCH);
iol_mode_enable(padapter, 0);
}
return result;
}
static s32 iol_ioconfig(struct adapter *padapter, u8 iocfg_bndy)
{
s32 rst = _SUCCESS;
rtw_write8(padapter, REG_TDECTRL + 1, iocfg_bndy);
rst = iol_execute(padapter, CMD_IOCONFIG);
return rst;
}
int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
{
struct pkt_attrib *pattrib = &xmit_frame->attrib;
u8 i;
int ret = _FAIL;
if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
goto exit;
if (rtw_usb_bulk_size_boundary(adapter, TXDESC_SIZE + pattrib->last_txcmdsz)) {
if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
goto exit;
}
dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
iol_mode_enable(adapter, 1);
for (i = 0; i < bndy_cnt; i++) {
u8 page_no = 0;
page_no = i * 2;
ret = iol_ioconfig(adapter, page_no);
if (ret != _SUCCESS)
break;
}
iol_mode_enable(adapter, 0);
exit:
/* restore BCN_HEAD */
rtw_write8(adapter, REG_TDECTRL + 1, 0);
return ret;
}
void rtl8188e_EfusePowerSwitch(struct adapter *pAdapter, u8 PwrState)
{
u16 tmpV16;
int res;
if (PwrState) {
rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
/* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), default valid */
res = rtw_read16(pAdapter, REG_SYS_ISO_CTRL, &tmpV16);
if (res)
return;
if (!(tmpV16 & PWC_EV12V)) {
tmpV16 |= PWC_EV12V;
rtw_write16(pAdapter, REG_SYS_ISO_CTRL, tmpV16);
}
/* Reset: 0x0000h[28], default valid */
res = rtw_read16(pAdapter, REG_SYS_FUNC_EN, &tmpV16);
if (res)
return;
if (!(tmpV16 & FEN_ELDR)) {
tmpV16 |= FEN_ELDR;
rtw_write16(pAdapter, REG_SYS_FUNC_EN, tmpV16);
}
/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
res = rtw_read16(pAdapter, REG_SYS_CLKR, &tmpV16);
if (res)
return;
if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
tmpV16 |= (LOADER_CLK_EN | ANA8M);
rtw_write16(pAdapter, REG_SYS_CLKR, tmpV16);
}
} else {
rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
}
}
static void Hal_EfuseReadEFuse88E(struct adapter *Adapter,
u16 _offset,
u16 _size_byte,
u8 *pbuf)
{
u8 *efuseTbl = NULL;
u8 rtemp8[1];
u16 eFuse_Addr = 0;
u8 offset, wren;
u16 i, j;
u16 **eFuseWord = NULL;
u16 efuse_utilized = 0;
u8 u1temp = 0;
/* */
/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
/* */
if ((_offset + _size_byte) > EFUSE_MAP_LEN_88E) /* total E-Fuse table is 512bytes */
goto exit;
efuseTbl = kzalloc(EFUSE_MAP_LEN_88E, GFP_KERNEL);
if (!efuseTbl)
goto exit;
eFuseWord = rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
if (!eFuseWord)
goto exit;
/* 0. Refresh efuse init map as all oxFF. */
for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
eFuseWord[i][j] = 0xFFFF;
/* */
/* 1. Read the first byte to check if efuse is empty!!! */
/* */
/* */
ReadEFuseByte(Adapter, eFuse_Addr, rtemp8);
if (*rtemp8 != 0xFF) {
efuse_utilized++;
eFuse_Addr++;
} else {
goto exit;
}
/* */
/* 2. Read real efuse content. Filter PG header and every section data. */
/* */
while ((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
/* Check PG header for section num. */
if ((*rtemp8 & 0x1F) == 0x0F) { /* extended header */
u1temp = ((*rtemp8 & 0xE0) >> 5);
ReadEFuseByte(Adapter, eFuse_Addr, rtemp8);
if ((*rtemp8 & 0x0F) == 0x0F) {
eFuse_Addr++;
ReadEFuseByte(Adapter, eFuse_Addr, rtemp8);
if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
eFuse_Addr++;
continue;
} else {
offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
wren = (*rtemp8 & 0x0F);
eFuse_Addr++;
}
} else {
offset = ((*rtemp8 >> 4) & 0x0f);
wren = (*rtemp8 & 0x0f);
}
if (offset < EFUSE_MAX_SECTION_88E) {
/* Get word enable value from PG header */
for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
/* Check word enable condition in the section */
if (!(wren & 0x01)) {
ReadEFuseByte(Adapter, eFuse_Addr, rtemp8);
eFuse_Addr++;
efuse_utilized++;
eFuseWord[offset][i] = (*rtemp8 & 0xff);
if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
break;
ReadEFuseByte(Adapter, eFuse_Addr, rtemp8);
eFuse_Addr++;
efuse_utilized++;
eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00);
if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
break;
}
wren >>= 1;
}
}
/* Read next PG header */
ReadEFuseByte(Adapter, eFuse_Addr, rtemp8);
if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) {
efuse_utilized++;
eFuse_Addr++;
}
}
/* 3. Collect 16 sections and 4 word unit into Efuse map. */
for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) {
for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
efuseTbl[(i * 8) + (j * 2)] = (eFuseWord[i][j] & 0xff);
efuseTbl[(i * 8) + ((j * 2) + 1)] = ((eFuseWord[i][j] >> 8) & 0xff);
}
}
/* 4. Copy from Efuse map to output pointer memory!!! */
for (i = 0; i < _size_byte; i++)
pbuf[i] = efuseTbl[_offset + i];
exit:
kfree(efuseTbl);
kfree(eFuseWord);
}
void rtl8188e_ReadEFuse(struct adapter *Adapter, u16 _size_byte, u8 *pbuf)
{
int ret = _FAIL;
if (rtw_IOL_applied(Adapter)) {
rtl8188eu_InitPowerOn(Adapter);
iol_mode_enable(Adapter, 1);
ret = iol_read_efuse(Adapter, _size_byte, pbuf);
iol_mode_enable(Adapter, 0);
if (_SUCCESS == ret)
return;
}
Hal_EfuseReadEFuse88E(Adapter, 0, _size_byte, pbuf);
}
static void dump_chip_info(struct adapter *adapter, struct HAL_VERSION chip_vers)
{
struct net_device *netdev = adapter->pnetdev;
char *cut = NULL;
char buf[25];
switch (chip_vers.CUTVersion) {
case A_CUT_VERSION:
cut = "A_CUT";
break;
case B_CUT_VERSION:
cut = "B_CUT";
break;
case C_CUT_VERSION:
cut = "C_CUT";
break;
case D_CUT_VERSION:
cut = "D_CUT";
break;
case E_CUT_VERSION:
cut = "E_CUT";
break;
default:
snprintf(buf, sizeof(buf), "UNKNOWN_CUT(%d)", chip_vers.CUTVersion);
cut = buf;
break;
}
netdev_dbg(netdev, "Chip Version Info: CHIP_8188E_%s_%s_%s_1T1R_RomVer(%d)\n",
IS_NORMAL_CHIP(chip_vers) ? "Normal_Chip" : "Test_Chip",
IS_CHIP_VENDOR_TSMC(chip_vers) ? "TSMC" : "UMC",
cut, 0);
}
void rtl8188e_read_chip_version(struct adapter *padapter)
{
u32 value32;
struct HAL_VERSION ChipVersion;
struct hal_data_8188e *pHalData = &padapter->haldata;
int res;
res = rtw_read32(padapter, REG_SYS_CFG, &value32);
if (res)
return;
ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
dump_chip_info(padapter, ChipVersion);
pHalData->VersionID = ChipVersion;
}
void rtl8188e_SetHalODMVar(struct adapter *Adapter, void *pValue1, bool bSet)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
struct sta_info *psta = (struct sta_info *)pValue1;
if (bSet) {
podmpriv->pODM_StaInfo[psta->mac_id] = psta;
ODM_RAInfo_Init(podmpriv, psta->mac_id);
} else {
podmpriv->pODM_StaInfo[psta->mac_id] = NULL;
}
}
void hal_notch_filter_8188e(struct adapter *adapter, bool enable)
{
int res;
u8 reg;
res = rtw_read8(adapter, rOFDM0_RxDSP + 1, &reg);
if (res)
return;
if (enable)
rtw_write8(adapter, rOFDM0_RxDSP + 1, reg | BIT(1));
else
rtw_write8(adapter, rOFDM0_RxDSP + 1, reg & ~BIT(1));
}
/* */
/* */
/* LLT R/W/Init function */
/* */
/* */
static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data)
{
s32 count;
u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
u16 LLTReg = REG_LLT_INIT;
int res;
rtw_write32(padapter, LLTReg, value);
/* polling */
for (count = 0; count <= POLLING_LLT_THRESHOLD; count++) {
res = rtw_read32(padapter, LLTReg, &value);
if (res)
continue;
if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
break;
}
return count > POLLING_LLT_THRESHOLD ? _FAIL : _SUCCESS;
}
s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
{
s32 status = _FAIL;
u32 i;
u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */
if (rtw_IOL_applied(padapter)) {
status = iol_InitLLTTable(padapter, txpktbuf_bndy);
} else {
for (i = 0; i < (txpktbuf_bndy - 1); i++) {
status = _LLTWrite(padapter, i, i + 1);
if (_SUCCESS != status)
return status;
}
/* end of list */
status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
if (_SUCCESS != status)
return status;
/* Make the other pages as ring buffer */
/* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */
/* Otherwise used as local loopback buffer. */
for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
status = _LLTWrite(padapter, i, (i + 1));
if (_SUCCESS != status)
return status;
}
/* Let last entry point to the start entry of ring buffer */
status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
if (_SUCCESS != status) {
return status;
}
}
return status;
}
void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo)
{
struct eeprom_priv *pEEPROM = &padapter->eeprompriv;
struct net_device *netdev = padapter->pnetdev;
u16 EEPROMId;
/* Check 0x8129 again for making sure autoload status!! */
EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
if (EEPROMId != RTL_EEPROM_ID) {
pr_err("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
pEEPROM->bautoload_fail_flag = true;
} else {
pEEPROM->bautoload_fail_flag = false;
}
netdev_dbg(netdev, "EEPROM ID = 0x%04x\n", EEPROMId);
}
static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail)
{
u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0;
memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g));
if (AutoLoadFail) {
for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
/* 2.4G default value */
for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
}
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
if (TxCount == 0) {
pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
} else {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
}
}
}
return;
}
for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
/* 2.4G default value */
for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
}
for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
}
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
if (TxCount == 0) {
pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
if (PROMContent[eeAddr] == 0xFF) {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
} else {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4;
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
}
if (PROMContent[eeAddr] == 0xFF) {
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
} else {
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f);
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
}
pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
eeAddr++;
} else {
if (PROMContent[eeAddr] == 0xFF) {
pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4;
if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
}
if (PROMContent[eeAddr] == 0xFF) {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f);
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
}
eeAddr++;
if (PROMContent[eeAddr] == 0xFF) {
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4;
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
}
if (PROMContent[eeAddr] == 0xFF) {
pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f);
if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
}
eeAddr++;
}
}
}
}
static void hal_get_chnl_group_88e(u8 chnl, u8 *group)
{
if (chnl < 3) /* Channel 1-2 */
*group = 0;
else if (chnl < 6) /* Channel 3-5 */
*group = 1;
else if (chnl < 9) /* Channel 6-8 */
*group = 2;
else if (chnl < 12) /* Channel 9-11 */
*group = 3;
else if (chnl < 14) /* Channel 12-13 */
*group = 4;
else if (chnl == 14) /* Channel 14 */
*group = 5;
}
void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
{
if (AutoLoadFail)
padapter->pwrctrlpriv.bSupportRemoteWakeup = false;
else
/* hw power down mode selection , 0:rf-off / 1:power down */
/* decide hw if support remote wakeup function */
/* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false;
}
void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail)
{
struct hal_data_8188e *pHalData = &padapter->haldata;
struct txpowerinfo24g pwrInfo24G;
u8 ch, group;
u8 TxCount;
Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
hal_get_chnl_group_88e(ch, &group);
pHalData->Index24G_CCK_Base[ch] = pwrInfo24G.IndexCCK_Base[0][group];
if (ch == 14)
pHalData->Index24G_BW40_Base[ch] = pwrInfo24G.IndexBW40_Base[0][4];
else
pHalData->Index24G_BW40_Base[ch] = pwrInfo24G.IndexBW40_Base[0][group];
}
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
pHalData->OFDM_24G_Diff[TxCount] = pwrInfo24G.OFDM_Diff[0][TxCount];
pHalData->BW20_24G_Diff[TxCount] = pwrInfo24G.BW20_Diff[0][TxCount];
}
/* 2010/10/19 MH Add Regulator recognize for CU. */
if (!AutoLoadFail) {
pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E] & 0x7); /* bit0~2 */
if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7); /* bit0~2 */
} else {
pHalData->EEPROMRegulatory = 0;
}
}
void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
{
struct hal_data_8188e *pHalData = &pAdapter->haldata;
if (!AutoLoadFail) {
pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
if (pHalData->CrystalCap == 0xFF)
pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
} else {
pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
}
}
void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
{
padapter->mlmepriv.ChannelPlan =
hal_com_get_channel_plan(padapter,
hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF,
padapter->registrypriv.channel_plan,
RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail);
}
void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail)
{
struct hal_data_8188e *pHalData = &pAdapter->haldata;
struct registry_priv *registry_par = &pAdapter->registrypriv;
if (!AutoLoadFail) {
/* Antenna Diversity setting. */
if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */
pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION & 0x18) >> 3;
} else {
pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */
}
if (registry_par->antdiv_type == 0) {
/* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
if (pHalData->TRxAntDivType == 0xFF)
pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
} else {
pHalData->TRxAntDivType = registry_par->antdiv_type;
}
if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */
} else {
pHalData->AntDivCfg = 0;
}
}
void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
/* ThermalMeter from EEPROM */
if (!AutoloadFail)
pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
else
pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail)
pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
}

705
drivers/staging/r8188eu/hal/rtl8188e_phycfg.c
View File

@ -1,705 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _RTL8188E_PHYCFG_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtw_iol.h"
#include "../include/rtl8188e_hal.h"
/* */
/* 1. BB register R/W API */
/* */
/* Get shifted position of the bit mask */
static u32 phy_calculate_bit_shift(u32 bitmask)
{
u32 i = ffs(bitmask);
return i ? i - 1 : 32;
}
/**
* Function: PHY_QueryBBReg
*
* Overview: Read "sepcific bits" from BB register
*
* Input:
* struct adapter *Adapter,
* u32 RegAddr, The target address to be readback
* u32 BitMask The target bit position in the target address
* to be readback
* Output: None
* Return: u32 Data The readback register value
* Note: This function is equal to "GetRegSetting" in PHY programming guide
*/
u32
rtl8188e_PHY_QueryBBReg(
struct adapter *Adapter,
u32 RegAddr,
u32 BitMask
)
{
u32 ReturnValue = 0, OriginalValue, BitShift;
int res;
res = rtw_read32(Adapter, RegAddr, &OriginalValue);
if (res)
return 0;
BitShift = phy_calculate_bit_shift(BitMask);
ReturnValue = (OriginalValue & BitMask) >> BitShift;
return ReturnValue;
}
/**
* Function: PHY_SetBBReg
*
* Overview: Write "Specific bits" to BB register (page 8~)
*
* Input:
* struct adapter *Adapter,
* u32 RegAddr, The target address to be modified
* u32 BitMask The target bit position in the target address
* to be modified
* u32 Data The new register value in the target bit position
* of the target address
*
* Output: None
* Return: None
* Note: This function is equal to "PutRegSetting" in PHY programming guide
*/
void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
{
u32 OriginalValue, BitShift;
int res;
if (BitMask != bMaskDWord) { /* if not "double word" write */
res = rtw_read32(Adapter, RegAddr, &OriginalValue);
if (res)
return;
BitShift = phy_calculate_bit_shift(BitMask);
Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
}
rtw_write32(Adapter, RegAddr, Data);
}
/* */
/* 2. RF register R/W API */
/* */
/**
* Function: phy_RFSerialRead
*
* Overview: Read register from RF chips
*
* Input:
* struct adapter *Adapter,
* u32 Offset, The target address to be read
*
* Output: None
* Return: u32 reback value
* Note: Threre are three types of serial operations:
* 1. Software serial write
* 2. Hardware LSSI-Low Speed Serial Interface
* 3. Hardware HSSI-High speed
* serial write. Driver need to implement (1) and (2).
* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
*/
static u32
phy_RFSerialRead(
struct adapter *Adapter,
u32 Offset
)
{
u32 retValue = 0;
struct hal_data_8188e *pHalData = &Adapter->haldata;
struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef;
u32 NewOffset;
u32 tmplong, tmplong2;
u8 RfPiEnable = 0;
/* */
/* Make sure RF register offset is correct */
/* */
Offset &= 0xff;
/* */
/* Switch page for 8256 RF IC */
/* */
NewOffset = Offset;
/* For 92S LSSI Read RFLSSIRead */
/* For RF A/B write 0x824/82c(does not work in the future) */
/* We must use 0x824 for RF A and B to execute read trigger */
tmplong = rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
tmplong2 = tmplong;
tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge));
udelay(10);/* PlatformStallExecution(10); */
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
udelay(100);/* PlatformStallExecution(100); */
udelay(10);/* PlatformStallExecution(10); */
RfPiEnable = (u8)rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8));
if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
retValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
} else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
retValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
}
return retValue;
}
/**
* Function: phy_RFSerialWrite
*
* Overview: Write data to RF register (page 8~)
*
* Input:
* struct adapter *Adapter,
* enum rf_radio_path eRFPath, Radio path of A/B/C/D
* u32 Offset, The target address to be read
* u32 Data The new register Data in the target bit position
* of the target to be read
*
* Output: None
* Return: None
* Note: Threre are three types of serial operations:
* 1. Software serial write
* 2. Hardware LSSI-Low Speed Serial Interface
* 3. Hardware HSSI-High speed
* serial write. Driver need to implement (1) and (2).
* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
*
* Note: For RF8256 only
* The total count of RTL8256(Zebra4) register is around 36 bit it only employs
* 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
* to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
* programming guide" for more details.
* Thus, we define a sub-finction for RTL8526 register address conversion
* ===========================================================
* Register Mode RegCTL[1] RegCTL[0] Note
* (Reg00[12]) (Reg00[10])
* ===========================================================
* Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
* ------------------------------------------------------------------
* Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
* ------------------------------------------------------------------
* Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
* ------------------------------------------------------------------
*
* 2008/09/02 MH Add 92S RF definition
*
*
*
*/
static void
phy_RFSerialWrite(
struct adapter *Adapter,
u32 Offset,
u32 Data
)
{
u32 DataAndAddr = 0;
struct hal_data_8188e *pHalData = &Adapter->haldata;
struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef;
u32 NewOffset;
/* 2009/06/17 MH We can not execute IO for power save or other accident mode. */
Offset &= 0xff;
/* */
/* Switch page for 8256 RF IC */
/* */
NewOffset = Offset;
/* */
/* Put write addr in [5:0] and write data in [31:16] */
/* */
DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
/* */
/* Write Operation */
/* */
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
}
/**
* Function: PHY_QueryRFReg
*
* Overview: Query "Specific bits" to RF register (page 8~)
*
* Input:
* struct adapter *Adapter,
* u32 RegAddr, The target address to be read
* u32 BitMask The target bit position in the target address
* to be read
*
* Output: None
* Return: u32 Readback value
* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
*/
u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
{
u32 Original_Value, Readback_Value, BitShift;
Original_Value = phy_RFSerialRead(Adapter, RegAddr);
BitShift = phy_calculate_bit_shift(BitMask);
Readback_Value = (Original_Value & BitMask) >> BitShift;
return Readback_Value;
}
/**
* Function: PHY_SetRFReg
*
* Overview: Write "Specific bits" to RF register (page 8~)
*
* Input:
* struct adapter *Adapter,
* u32 RegAddr, The target address to be modified
* u32 BitMask The target bit position in the target address
* to be modified
* u32 Data The new register Data in the target bit position
* of the target address
*
* Output: None
* Return: None
* Note: This function is equal to "PutRFRegSetting" in PHY programming guide
*/
void
rtl8188e_PHY_SetRFReg(
struct adapter *Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{
u32 Original_Value, BitShift;
/* RF data is 12 bits only */
if (BitMask != bRFRegOffsetMask) {
Original_Value = phy_RFSerialRead(Adapter, RegAddr);
BitShift = phy_calculate_bit_shift(BitMask);
Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
}
phy_RFSerialWrite(Adapter, RegAddr, Data);
}
/* */
/* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
/* */
/*-----------------------------------------------------------------------------
* Function: PHY_MACConfig8192C
*
* Overview: Condig MAC by header file or parameter file.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 08/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
int PHY_MACConfig8188E(struct adapter *Adapter)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
int err;
/* */
/* Config MAC */
/* */
err = ODM_ReadAndConfig_MAC_REG_8188E(&pHalData->odmpriv);
/* 2010.07.13 AMPDU aggregation number B */
rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
return err;
}
/**
* Function: phy_InitBBRFRegisterDefinition
*
* Overview: Initialize Register definition offset for Radio Path A/B/C/D
*
* Input:
* struct adapter *Adapter,
*
* Output: None
* Return: None
* Note: The initialization value is constant and it should never be changes
*/
static void
phy_InitBBRFRegisterDefinition(
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
/* RF Interface Sowrtware Control */
pHalData->PHYRegDef.rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
/* RF Interface Readback Value */
pHalData->PHYRegDef.rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */
/* RF Interface Output (and Enable) */
pHalData->PHYRegDef.rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
/* RF Interface (Output and) Enable */
pHalData->PHYRegDef.rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
/* Addr of LSSI. Write RF register by driver */
pHalData->PHYRegDef.rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
/* RF parameter */
pHalData->PHYRegDef.rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */
/* Tx AGC Gain Stage (same for all path. Should we remove this?) */
pHalData->PHYRegDef.rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
/* Transceiver A~D HSSI Parameter-1 */
pHalData->PHYRegDef.rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */
/* Transceiver A~D HSSI Parameter-2 */
pHalData->PHYRegDef.rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
/* RF switch Control */
pHalData->PHYRegDef.rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */
/* AGC control 1 */
pHalData->PHYRegDef.rfAGCControl1 = rOFDM0_XAAGCCore1;
/* AGC control 2 */
pHalData->PHYRegDef.rfAGCControl2 = rOFDM0_XAAGCCore2;
/* RX AFE control 1 */
pHalData->PHYRegDef.rfRxIQImbalance = rOFDM0_XARxIQImbalance;
/* RX AFE control 1 */
pHalData->PHYRegDef.rfRxAFE = rOFDM0_XARxAFE;
/* Tx AFE control 1 */
pHalData->PHYRegDef.rfTxIQImbalance = rOFDM0_XATxIQImbalance;
/* Tx AFE control 2 */
pHalData->PHYRegDef.rfTxAFE = rOFDM0_XATxAFE;
/* Transceiver LSSI Readback SI mode */
pHalData->PHYRegDef.rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
/* Transceiver LSSI Readback PI mode */
pHalData->PHYRegDef.rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
}
void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
if (RegAddr == rTxAGC_A_Rate18_06)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
if (RegAddr == rTxAGC_A_Rate54_24)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
if (RegAddr == rTxAGC_A_CCK1_Mcs32)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
if (RegAddr == rTxAGC_A_Mcs03_Mcs00)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
if (RegAddr == rTxAGC_A_Mcs07_Mcs04)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
if (RegAddr == rTxAGC_A_Mcs11_Mcs08)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
if (RegAddr == rTxAGC_A_Mcs15_Mcs12) {
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
pHalData->pwrGroupCnt++;
}
if (RegAddr == rTxAGC_B_Rate18_06)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
if (RegAddr == rTxAGC_B_Rate54_24)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
if (RegAddr == rTxAGC_B_CCK1_55_Mcs32)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
if (RegAddr == rTxAGC_B_Mcs03_Mcs00)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
if (RegAddr == rTxAGC_B_Mcs07_Mcs04)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
if (RegAddr == rTxAGC_B_Mcs11_Mcs08)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
if (RegAddr == rTxAGC_B_Mcs15_Mcs12)
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
}
static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter)
{
struct eeprom_priv *pEEPROM = &Adapter->eeprompriv;
struct hal_data_8188e *pHalData = &Adapter->haldata;
int err;
/* */
/* 1. Read PHY_REG.TXT BB INIT!! */
/* We will separate as 88C / 92C according to chip version */
/* */
err = ODM_ReadAndConfig_PHY_REG_1T_8188E(&pHalData->odmpriv);
if (err)
return err;
/* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
if (!pEEPROM->bautoload_fail_flag) {
pHalData->pwrGroupCnt = 0;
ODM_ReadAndConfig_PHY_REG_PG_8188E(&pHalData->odmpriv);
}
/* 3. BB AGC table Initialization */
err = ODM_ReadAndConfig_AGC_TAB_1T_8188E(&pHalData->odmpriv);
if (err)
return err;
return 0;
}
int
PHY_BBConfig8188E(
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u16 RegVal;
u8 CrystalCap;
int err;
phy_InitBBRFRegisterDefinition(Adapter);
/* Enable BB and RF */
err = rtw_read16(Adapter, REG_SYS_FUNC_EN, &RegVal);
if (err)
return err;
rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT(13) | BIT(0) | BIT(1)));
/* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
/* Config BB and AGC */
err = phy_BB8188E_Config_ParaFile(Adapter);
/* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
CrystalCap = pHalData->CrystalCap & 0x3F;
rtl8188e_PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
return err;
}
static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
u8 *ofdmPowerLevel, u8 *BW20PowerLevel,
u8 *BW40PowerLevel)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u8 index = (channel - 1);
/* 1. CCK */
cckPowerLevel[RF_PATH_A] = pHalData->Index24G_CCK_Base[index];
/* 2. OFDM */
ofdmPowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index] +
pHalData->OFDM_24G_Diff[RF_PATH_A];
/* 1. BW20 */
BW20PowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index] +
pHalData->BW20_24G_Diff[RF_PATH_A];
/* 2. BW40 */
BW40PowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index];
}
/*-----------------------------------------------------------------------------
* Function: SetTxPowerLevel8190()
*
* Overview: This function is export to "HalCommon" moudule
* We must consider RF path later!!!!!!!
*
* Input: struct adapter *Adapter
* u8 channel
*
* Output: NONE
*
* Return: NONE
* 2008/11/04 MHC We remove EEPROM_93C56.
* We need to move CCX relative code to independet file.
* 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
*
*---------------------------------------------------------------------------*/
void
PHY_SetTxPowerLevel8188E(
struct adapter *Adapter,
u8 channel
)
{
u8 cckPowerLevel[MAX_TX_COUNT] = {0};
u8 ofdmPowerLevel[MAX_TX_COUNT] = {0};/* [0]:RF-A, [1]:RF-B */
u8 BW20PowerLevel[MAX_TX_COUNT] = {0};
u8 BW40PowerLevel[MAX_TX_COUNT] = {0};
getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel);
}
/*-----------------------------------------------------------------------------
* Function: PHY_SetBWModeCallback8192C()
*
* Overview: Timer callback function for SetSetBWMode
*
* Input: PRT_TIMER pTimer
*
* Output: NONE
*
* Return: NONE
*
* Note: (1) We do not take j mode into consideration now
* (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
* concurrently?
*---------------------------------------------------------------------------*/
static void
_PHY_SetBWMode92C(
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u8 regBwOpMode;
u8 regRRSR_RSC;
int res;
if (Adapter->bDriverStopped)
return;
/* 3 */
/* 3<1>Set MAC register */
/* 3 */
res = rtw_read8(Adapter, REG_BWOPMODE, &regBwOpMode);
if (res)
return;
res = rtw_read8(Adapter, REG_RRSR + 2, &regRRSR_RSC);
if (res)
return;
switch (pHalData->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily because we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break;
case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily because we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
regRRSR_RSC = (regRRSR_RSC & 0x90) | (pHalData->nCur40MhzPrimeSC << 5);
rtw_write8(Adapter, REG_RRSR + 2, regRRSR_RSC);
break;
default:
break;
}
/* 3 */
/* 3 <2>Set PHY related register */
/* 3 */
switch (pHalData->CurrentChannelBW) {
/* 20 MHz channel*/
case HT_CHANNEL_WIDTH_20:
rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
break;
/* 40 MHz channel*/
case HT_CHANNEL_WIDTH_40:
rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
/* Set Control channel to upper or lower. These settings are required only for 40MHz */
rtl8188e_PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
rtl8188e_PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
rtl8188e_PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)),
(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break;
default:
break;
}
/* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
}
/*-----------------------------------------------------------------------------
* Function: SetBWMode8190Pci()
*
* Overview: This function is export to "HalCommon" moudule
*
* Input: struct adapter *Adapter
* enum ht_channel_width Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: We do not take j mode into consideration now
*---------------------------------------------------------------------------*/
void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */
unsigned char Offset) /* Upper, Lower, or Don't care */
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
enum ht_channel_width tmpBW = pHalData->CurrentChannelBW;
pHalData->CurrentChannelBW = Bandwidth;
pHalData->nCur40MhzPrimeSC = Offset;
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
_PHY_SetBWMode92C(Adapter);
else
pHalData->CurrentChannelBW = tmpBW;
}
static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
{
u32 param1, param2;
struct hal_data_8188e *pHalData = &Adapter->haldata;
/* s1. pre common command - CmdID_SetTxPowerLevel */
PHY_SetTxPowerLevel8188E(Adapter, channel);
/* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
param1 = RF_CHNLBW;
param2 = channel;
pHalData->RfRegChnlVal = ((pHalData->RfRegChnlVal & 0xfffffc00) | param2);
rtl8188e_PHY_SetRFReg(Adapter, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal);
}
void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
{
/* Call after initialization */
struct hal_data_8188e *pHalData = &Adapter->haldata;
if (channel == 0)
channel = 1;
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
pHalData->CurrentChannel = channel;
_PHY_SwChnl8192C(Adapter, channel);
}
}

405
drivers/staging/r8188eu/hal/rtl8188e_rf6052.c
View File

@ -1,405 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
/******************************************************************************
*
*
* Module: rtl8192c_rf6052.c ( Source C File)
*
* Note: Provide RF 6052 series relative API.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
* 11/05/2008 MHC Add API for tw power setting.
*
*
******************************************************************************/
#define _RTL8188E_RF6052_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtl8188e_hal.h"
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: struct adapter *Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
enum ht_channel_width Bandwidth)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal = ((pHalData->RfRegChnlVal & 0xfffff3ff) | BIT(10) | BIT(11));
rtl8188e_PHY_SetRFReg(Adapter, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal);
break;
case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal = ((pHalData->RfRegChnlVal & 0xfffff3ff) | BIT(10));
rtl8188e_PHY_SetRFReg(Adapter, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal);
break;
default:
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetCckTxPower
*
* Overview:
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/05/2008 MHC Simulate 8192series..
*
*---------------------------------------------------------------------------*/
void
rtl8188e_PHY_RF6052SetCckTxPower(
struct adapter *Adapter,
u8 *pPowerlevel)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
u8 idx1, idx2;
u8 *ptr;
u8 direction;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1] << 8) |
(pPowerlevel[idx1] << 16) | (pPowerlevel[idx1] << 24);
}
} else {
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1] << 8) |
(pPowerlevel[idx1] << 16) | (pPowerlevel[idx1] << 24);
}
if (pHalData->EEPROMRegulatory == 0) {
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][7] << 8);
TxAGC[RF_PATH_A] += tmpval;
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][15] << 24);
TxAGC[RF_PATH_B] += tmpval;
}
}
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
ptr = (u8 *)(&TxAGC[idx1]);
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
if (direction == 1) {
/* Increase TX power */
TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value;
} else if (direction == 2) {
/* Decrease TX power */
TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value;
}
/* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A] & 0xff;
rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
tmpval = TxAGC[RF_PATH_A] >> 8;
rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
/* rf-B cck tx power */
tmpval = TxAGC[RF_PATH_B] >> 24;
rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
tmpval = TxAGC[RF_PATH_B] & 0x00ffffff;
rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
} /* PHY_RF6052SetCckTxPower */
/* */
/* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */
/* */
static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u32 powerBase0, powerBase1;
u8 i;
for (i = 0; i < 2; i++) {
powerBase0 = pPowerLevelOFDM[i];
powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0;
*(OfdmBase + i) = powerBase0;
}
/* Check HT20 to HT40 diff */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
powerBase1 = pPowerLevelBW20[0];
else
powerBase1 = pPowerLevelBW40[0];
powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
*MCSBase = powerBase1;
}
static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
u8 index, u32 *powerBase0, u32 *powerBase1,
u32 *pOutWriteVal)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
s8 pwr_diff = 0;
u32 writeVal, customer_limit, rf;
u8 Regulatory = pHalData->EEPROMRegulatory;
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
for (rf = 0; rf < 2; rf++) {
switch (Regulatory) {
case 0: /* Realtek better performance */
/* increase power diff defined by Realtek for large power */
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= MAX_PG_GROUP) {
if (Channel < 3) /* Channel 1-2 */
chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if (Channel < 9) /* Channel 6-8 */
chnlGroup = 2;
else if (Channel < 12) /* Channel 9-11 */
chnlGroup = 3;
else if (Channel < 14) /* Channel 12-13 */
chnlGroup = 4;
else if (Channel == 14) /* Channel 14 */
chnlGroup = 5;
}
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0;
if (index < 2)
pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel - 1];
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel - 1];
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel - 1];
else
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel - 1];
if (pwr_diff >= customer_pwr_limit)
pwr_diff = 0;
else
pwr_diff = customer_pwr_limit - pwr_diff;
for (i = 0; i < 4; i++) {
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] & (0x7f << (i * 8))) >> (i * 8));
if (pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff;
}
customer_limit = (pwr_diff_limit[3] << 24) | (pwr_diff_limit[2] << 16) |
(pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
}
*(pOutWriteVal + rf) = writeVal;
}
}
static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
{
u16 regoffset_a[6] = {
rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
u16 regoffset_b[6] = {
rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
u8 i, rf, pwr_val[4];
u32 writeVal;
u16 regoffset;
for (rf = 0; rf < 2; rf++) {
writeVal = pValue[rf];
for (i = 0; i < 4; i++) {
pwr_val[i] = (u8)((writeVal & (0x7f << (i * 8))) >> (i * 8));
if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) | (pwr_val[1] << 8) | pwr_val[0];
if (rf == 0)
regoffset = regoffset_a[index];
else
regoffset = regoffset_b[index];
rtl8188e_PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04) {
writeVal = pwr_val[3];
if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
regoffset = 0xc90;
if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
regoffset = 0xc98;
for (i = 0; i < 3; i++) {
if (i != 2)
writeVal = (writeVal > 8) ? (writeVal - 8) : 0;
else
writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
rtw_write8(Adapter, (u32)(regoffset + i), (u8)writeVal);
}
}
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetOFDMTxPower
*
* Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
* different channel and read original value in TX power register area from
* 0xe00. We increase offset and original value to be correct tx pwr.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/05/2008 MHC Simulate 8192 series method.
* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
* A/B pwr difference or legacy/HT pwr diff.
* 2. We concern with path B legacy/HT OFDM difference.
* 01/22/2009 MHC Support new EPRO format from SD3.
*
*---------------------------------------------------------------------------*/
void
rtl8188e_PHY_RF6052SetOFDMTxPower(
struct adapter *Adapter,
u8 *pPowerLevelOFDM,
u8 *pPowerLevelBW20,
u8 *pPowerLevelBW40,
u8 Channel)
{
struct hal_data_8188e *pHalData = &Adapter->haldata;
u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
u8 direction;
u8 index = 0;
getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
/* This is ued to fix unstable power tracking mode. */
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
for (index = 0; index < 6; index++) {
get_rx_power_val_by_reg(Adapter, Channel, index,
&powerBase0[0], &powerBase1[0],
&writeVal[0]);
if (direction == 1) {
writeVal[0] += pwrtrac_value;
writeVal[1] += pwrtrac_value;
} else if (direction == 2) {
writeVal[0] -= pwrtrac_value;
writeVal[1] -= pwrtrac_value;
}
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
}
}
int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
{
struct bb_reg_def *pPhyReg;
struct hal_data_8188e *pHalData = &Adapter->haldata;
u32 u4RegValue = 0;
int err;
/* Initialize RF */
pPhyReg = &pHalData->PHYRegDef;
/*----Store original RFENV control type----*/
u4RegValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
/*----Set RF_ENV enable----*/
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
err = ODM_ReadAndConfig_RadioA_1T_8188E(&pHalData->odmpriv);
/*----Restore RFENV control type----*/;
rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
return err;
}

161
drivers/staging/r8188eu/hal/rtl8188e_rxdesc.c
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@ -1,161 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _RTL8188E_REDESC_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtl8188e_hal.h"
static void process_rssi(struct adapter *padapter, struct recv_frame *prframe)
{
struct rx_pkt_attrib *pattrib = &prframe->attrib;
struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
if (signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
}
signal_stat->total_num++;
signal_stat->total_val += pattrib->phy_info.SignalStrength;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
} /* Process_UI_RSSI_8192C */
static void process_link_qual(struct adapter *padapter, struct recv_frame *prframe)
{
struct rx_pkt_attrib *pattrib;
struct signal_stat *signal_stat;
if (!prframe || !padapter)
return;
pattrib = &prframe->attrib;
signal_stat = &padapter->recvpriv.signal_qual_data;
if (signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
}
signal_stat->total_num++;
signal_stat->total_val += pattrib->phy_info.SignalQuality;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
}
static void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe)
{
struct recv_frame *precvframe = (struct recv_frame *)prframe;
/* Check RSSI */
process_rssi(padapter, precvframe);
/* Check EVM */
process_link_qual(padapter, precvframe);
}
void update_recvframe_attrib_88e(struct recv_frame *precvframe, struct recv_stat *prxstat)
{
struct rx_pkt_attrib *pattrib = &precvframe->attrib;
memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
pattrib->crc_err = (le32_to_cpu(prxstat->rxdw0) >> 14) & 0x1;
pattrib->pkt_rpt_type = (le32_to_cpu(prxstat->rxdw3) >> 14) & 0x3;
if (pattrib->pkt_rpt_type == NORMAL_RX) {
pattrib->pkt_len = le32_to_cpu(prxstat->rxdw0) & 0x00003fff;
pattrib->icv_err = (le32_to_cpu(prxstat->rxdw0) >> 15) & 0x1;
pattrib->drvinfo_sz = ((le32_to_cpu(prxstat->rxdw0) >> 16) & 0xf) * 8;
pattrib->encrypt = (u8)((le32_to_cpu(prxstat->rxdw0) >> 20) & 0x7);
pattrib->qos = (le32_to_cpu(prxstat->rxdw0) >> 23) & 0x1;
pattrib->shift_sz = (le32_to_cpu(prxstat->rxdw0) >> 24) & 0x3;
pattrib->physt = (le32_to_cpu(prxstat->rxdw0) >> 26) & 0x1;
pattrib->bdecrypted = (le32_to_cpu(prxstat->rxdw0) & BIT(27)) ? 0 : 1;
pattrib->priority = (le32_to_cpu(prxstat->rxdw1) >> 8) & 0xf;
pattrib->amsdu = (le32_to_cpu(prxstat->rxdw1) >> 13) & 0x1;
pattrib->mdata = (le32_to_cpu(prxstat->rxdw1) >> 26) & 0x1;
pattrib->mfrag = (le32_to_cpu(prxstat->rxdw1) >> 27) & 0x1;
pattrib->seq_num = le32_to_cpu(prxstat->rxdw2) & 0x00000fff;
pattrib->frag_num = (le32_to_cpu(prxstat->rxdw2) >> 12) & 0xf;
pattrib->mcs_rate = le32_to_cpu(prxstat->rxdw3) & 0x3f;
pattrib->rxht = (le32_to_cpu(prxstat->rxdw3) >> 6) & 0x1;
} else if (pattrib->pkt_rpt_type == TX_REPORT1) { /* CCX */
pattrib->pkt_len = TX_RPT1_PKT_LEN;
} else if (pattrib->pkt_rpt_type == TX_REPORT2) {
pattrib->pkt_len = le32_to_cpu(prxstat->rxdw0) & 0x3FF;
pattrib->MacIDValidEntry[0] = le32_to_cpu(prxstat->rxdw4);
pattrib->MacIDValidEntry[1] = le32_to_cpu(prxstat->rxdw5);
} else if (pattrib->pkt_rpt_type == HIS_REPORT) {
pattrib->pkt_len = le32_to_cpu(prxstat->rxdw0) & 0x00003fff;
}
}
/*
* Notice:
* Before calling this function,
* precvframe->rx_data should be ready!
*/
void update_recvframe_phyinfo_88e(struct recv_frame *precvframe, struct phy_stat *pphy_status)
{
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)precvframe->rx_data;
struct adapter *padapter = precvframe->adapter;
struct rx_pkt_attrib *pattrib = &precvframe->attrib;
struct hal_data_8188e *pHalData = &padapter->haldata;
struct phy_info *pPHYInfo = &pattrib->phy_info;
u8 *wlanhdr = precvframe->rx_data;
struct odm_per_pkt_info pkt_info;
u8 *sa = NULL;
struct sta_priv *pstapriv;
struct sta_info *psta;
pkt_info.bPacketMatchBSSID = ((!ieee80211_is_ctl(hdr->frame_control)) &&
!pattrib->icv_err && !pattrib->crc_err &&
!memcmp(get_hdr_bssid(wlanhdr),
get_bssid(&padapter->mlmepriv), ETH_ALEN));
pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID &&
ether_addr_equal(ieee80211_get_DA(hdr),
myid(&padapter->eeprompriv));
pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID &&
ieee80211_is_beacon(hdr->frame_control);
if (pkt_info.bPacketBeacon) {
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE))
sa = padapter->mlmepriv.cur_network.network.MacAddress;
/* to do Ad-hoc */
} else {
sa = ieee80211_get_SA(hdr);
}
pstapriv = &padapter->stapriv;
pkt_info.StationID = 0xFF;
psta = rtw_get_stainfo(pstapriv, sa);
if (psta)
pkt_info.StationID = psta->mac_id;
pkt_info.Rate = pattrib->mcs_rate;
ODM_PhyStatusQuery(&pHalData->odmpriv, pPHYInfo, (u8 *)pphy_status, &(pkt_info), padapter);
precvframe->psta = NULL;
if (pkt_info.bPacketMatchBSSID &&
(check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE))) {
if (psta) {
precvframe->psta = psta;
rtl8188e_process_phy_info(padapter, precvframe);
}
} else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) {
if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
if (psta)
precvframe->psta = psta;
}
rtl8188e_process_phy_info(padapter, precvframe);
}
}

627
drivers/staging/r8188eu/hal/rtl8188eu_xmit.c
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@ -1,627 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _RTL8188E_XMIT_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/wifi.h"
#include "../include/osdep_intf.h"
#include "../include/usb_ops.h"
#include "../include/rtl8188e_hal.h"
static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
{
u16 *usptr = (u16 *)ptxdesc;
u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
u32 index;
u16 checksum = 0;
/* Clear first */
ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
for (index = 0; index < count; index++)
checksum = checksum ^ le16_to_cpu(*(__le16 *)(usptr + index));
ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff & checksum);
}
/* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
/* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
/* Fw can tell Hw to send these packet derectly. */
void rtl8188e_fill_fake_txdesc(struct adapter *adapt, u8 *desc, u32 BufferLen, u8 ispspoll, u8 is_btqosnull)
{
struct tx_desc *ptxdesc;
/* Clear all status */
ptxdesc = (struct tx_desc *)desc;
memset(desc, 0, TXDESC_SIZE);
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(BufferLen & 0x0000ffff); /* Buffer size + command header */
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT << QSEL_SHT) & 0x00001f00); /* Fixed queue of Mgnt queue */
/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
if (ispspoll) {
ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
} else {
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
ptxdesc->txdw3 |= cpu_to_le32((8 << 28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
}
if (is_btqosnull)
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
/* USB interface drop packet if the checksum of descriptor isn't correct. */
/* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
rtl8188eu_cal_txdesc_chksum(ptxdesc);
}
static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)
{
if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
switch (pattrib->encrypt) {
/* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
case _WEP40_:
case _WEP104_:
ptxdesc->txdw1 |= cpu_to_le32((0x01 << SEC_TYPE_SHT) & 0x00c00000);
ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
break;
case _TKIP_:
case _TKIP_WTMIC_:
ptxdesc->txdw1 |= cpu_to_le32((0x01 << SEC_TYPE_SHT) & 0x00c00000);
ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
break;
case _AES_:
ptxdesc->txdw1 |= cpu_to_le32((0x03 << SEC_TYPE_SHT) & 0x00c00000);
ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
break;
case _NO_PRIVACY_:
default:
break;
}
}
}
static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
{
switch (pattrib->vcs_mode) {
case RTS_CTS:
*pdw |= cpu_to_le32(RTS_EN);
break;
case CTS_TO_SELF:
*pdw |= cpu_to_le32(CTS_2_SELF);
break;
case NONE_VCS:
default:
break;
}
if (pattrib->vcs_mode) {
*pdw |= cpu_to_le32(HW_RTS_EN);
/* Set RTS BW */
if (pattrib->ht_en) {
*pdw |= (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0;
if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
*pdw |= cpu_to_le32((0x01 << 28) & 0x30000000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
*pdw |= cpu_to_le32((0x02 << 28) & 0x30000000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
*pdw |= 0;
else
*pdw |= cpu_to_le32((0x03 << 28) & 0x30000000);
}
}
}
static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw)
{
if (pattrib->ht_en) {
*pdw |= (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0;
if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
*pdw |= cpu_to_le32((0x01 << DATA_SC_SHT) & 0x003f0000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
*pdw |= cpu_to_le32((0x02 << DATA_SC_SHT) & 0x003f0000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
*pdw |= 0;
else
*pdw |= cpu_to_le32((0x03 << DATA_SC_SHT) & 0x003f0000);
}
}
static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz)
{
uint qsel;
u8 data_rate, pwr_status, offset;
struct adapter *adapt = pxmitframe->padapter;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct hal_data_8188e *haldata = &adapt->haldata;
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
memset(ptxdesc, 0, sizeof(struct tx_desc));
/* 4 offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */
offset = TXDESC_SIZE + OFFSET_SZ;
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */
if (is_multicast_ether_addr(pattrib->ra))
ptxdesc->txdw0 |= cpu_to_le32(BMC);
/* pkt_offset, unit:8 bytes padding */
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
/* driver uses rate */
ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3F);
qsel = (uint)(pattrib->qsel & 0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000);
fill_txdesc_sectype(pattrib, ptxdesc);
if (pattrib->ampdu_en) {
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
} else {
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
}
/* offset 8 */
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000);
/* offset 16 , offset 20 */
if (pattrib->qos_en)
ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
/* offset 20 */
if (pxmitframe->agg_num > 1)
ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
if ((pattrib->ether_type != 0x888e) &&
(pattrib->ether_type != 0x0806) &&
(pattrib->ether_type != 0x88b4) &&
(pattrib->dhcp_pkt != 1)) {
/* Non EAP & ARP & DHCP type data packet */
fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
if (pattrib->ht_en) {
if (ODM_RA_GetShortGI_8188E(&haldata->odmpriv, pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
}
data_rate = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, pattrib->mac_id);
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, pattrib->mac_id);
ptxdesc->txdw4 |= cpu_to_le32((pwr_status & 0x7) << PWR_STATUS_SHT);
} else {
/* EAP data packet and ARP packet and DHCP. */
/* Use the 1M data rate to send the EAP/ARP packet. */
/* This will maybe make the handshake smooth. */
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
} else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3f);
qsel = (uint)(pattrib->qsel & 0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000f0000);
/* offset 8 */
/* CCX-TXRPT ack for xmit mgmt frames. */
if (pxmitframe->ack_report)
ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000);
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
if (pattrib->retry_ctrl)
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
else
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
} else if ((pxmitframe->frame_tag & 0x0f) != TXAGG_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((4) & 0x3f);/* CAM_ID(MAC_ID) */
ptxdesc->txdw1 |= cpu_to_le32((6 << RATE_ID_SHT) & 0x000f0000);/* raid */
/* offset 8 */
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0fff0000);
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
/* mgnt frame should be controlled by Hw because Fw will also send null data */
/* which we cannot control when Fw LPS enable. */
/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
/* 2010.06.23. Added by tynli. */
if (!pattrib->qos_en) {
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
}
ODM_SetTxAntByTxInfo_88E(&haldata->odmpriv, pmem, pattrib->mac_id);
rtl8188eu_cal_txdesc_chksum(ptxdesc);
return 0;
}
/* for non-agg data frame or management frame */
static s32 rtw_dump_xframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
{
s32 ret = _SUCCESS;
s32 inner_ret = _SUCCESS;
int t, sz, w_sz, pull = 0;
u8 *mem_addr;
u32 ff_hwaddr;
struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
struct security_priv *psecuritypriv = &adapt->securitypriv;
if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.ether_type != 0x88b4) &&
(pxmitframe->attrib.dhcp_pkt != 1))
rtw_issue_addbareq_cmd(adapt, pxmitframe);
mem_addr = pxmitframe->buf_addr;
for (t = 0; t < pattrib->nr_frags; t++) {
if (inner_ret != _SUCCESS && ret == _SUCCESS)
ret = _FAIL;
if (t != (pattrib->nr_frags - 1)) {
sz = pxmitpriv->frag_len;
sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
} else {
/* no frag */
sz = pattrib->last_txcmdsz;
}
pull = update_txdesc(pxmitframe, mem_addr, sz);
if (pull) {
mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
pxmitframe->buf_addr = mem_addr;
w_sz = sz + TXDESC_SIZE;
} else {
w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ;
}
ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
inner_ret = rtw_write_port(adapt, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf);
rtw_count_tx_stats(adapt, pxmitframe, sz);
mem_addr += w_sz;
mem_addr = PTR_ALIGN(mem_addr, 4);
}
rtw_free_xmitframe(pxmitpriv, pxmitframe);
if (ret != _SUCCESS)
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
return ret;
}
static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
{
struct pkt_attrib *pattrib = &pxmitframe->attrib;
u32 len = 0;
/* no consider fragement */
len = pattrib->hdrlen + pattrib->iv_len +
SNAP_SIZE + sizeof(u16) +
pattrib->pktlen +
((pattrib->bswenc) ? pattrib->icv_len : 0);
if (pattrib->encrypt == _TKIP_)
len += 8;
return len;
}
bool rtl8188eu_xmitframe_complete(struct adapter *adapt)
{
struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
struct xmit_frame *pxmitframe = NULL;
struct xmit_frame *pfirstframe = NULL;
struct xmit_buf *pxmitbuf;
/* aggregate variable */
struct hw_xmit *phwxmit;
struct sta_info *psta = NULL;
struct tx_servq *ptxservq = NULL;
struct list_head *xmitframe_plist = NULL, *xmitframe_phead = NULL;
u32 pbuf; /* next pkt address */
u32 pbuf_tail; /* last pkt tail */
u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */
u32 bulksize;
u8 desc_cnt;
u32 bulkptr;
/* dump frame variable */
u32 ff_hwaddr;
if (pdvobjpriv->pusbdev->speed == USB_SPEED_HIGH)
bulksize = USB_HIGH_SPEED_BULK_SIZE;
else
bulksize = USB_FULL_SPEED_BULK_SIZE;
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (!pxmitbuf)
return false;
pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits);
if (!pxmitframe) {
/* no more xmit frame, release xmit buffer */
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
return false;
}
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf;
pxmitbuf->priv_data = pxmitframe;
pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */
pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */
rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
/* always return ndis_packet after rtw_xmitframe_coalesce */
rtw_xmit_complete(adapt, pxmitframe);
/* 3 2. aggregate same priority and same DA(AP or STA) frames */
pfirstframe = pxmitframe;
len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE + (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
pbuf_tail = len;
pbuf = round_up(pbuf_tail, 8);
/* check pkt amount in one bulk */
desc_cnt = 0;
bulkptr = bulksize;
if (pbuf < bulkptr) {
desc_cnt++;
} else {
desc_cnt = 0;
bulkptr = ((pbuf / bulksize) + 1) * bulksize; /* round to next bulksize */
}
/* dequeue same priority packet from station tx queue */
psta = pfirstframe->attrib.psta;
switch (pfirstframe->attrib.priority) {
case 1:
case 2:
ptxservq = &psta->sta_xmitpriv.bk_q;
phwxmit = pxmitpriv->hwxmits + 3;
break;
case 4:
case 5:
ptxservq = &psta->sta_xmitpriv.vi_q;
phwxmit = pxmitpriv->hwxmits + 1;
break;
case 6:
case 7:
ptxservq = &psta->sta_xmitpriv.vo_q;
phwxmit = pxmitpriv->hwxmits;
break;
case 0:
case 3:
default:
ptxservq = &psta->sta_xmitpriv.be_q;
phwxmit = pxmitpriv->hwxmits + 2;
break;
}
spin_lock_bh(&pxmitpriv->lock);
xmitframe_phead = &ptxservq->sta_pending;
xmitframe_plist = xmitframe_phead->next;
while (xmitframe_phead != xmitframe_plist) {
pxmitframe = container_of(xmitframe_plist, struct xmit_frame, list);
xmitframe_plist = xmitframe_plist->next;
pxmitframe->agg_num = 0; /* not first frame of aggregation */
pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */
len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
if (pbuf + len > MAX_XMITBUF_SZ) {
pxmitframe->agg_num = 1;
pxmitframe->pkt_offset = 1;
break;
}
list_del_init(&pxmitframe->list);
ptxservq->qcnt--;
phwxmit->accnt--;
pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
/* always return ndis_packet after rtw_xmitframe_coalesce */
rtw_xmit_complete(adapt, pxmitframe);
/* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */
update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz);
/* don't need xmitframe any more */
rtw_free_xmitframe(pxmitpriv, pxmitframe);
/* handle pointer and stop condition */
pbuf_tail = pbuf + len;
pbuf = round_up(pbuf_tail, 8);
pfirstframe->agg_num++;
if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num)
break;
if (pbuf < bulkptr) {
desc_cnt++;
if (desc_cnt == USB_TXAGG_DESC_NUM)
break;
} else {
desc_cnt = 0;
bulkptr = ((pbuf / bulksize) + 1) * bulksize;
}
} /* end while (aggregate same priority and same DA(AP or STA) frames) */
if (list_empty(&ptxservq->sta_pending))
list_del_init(&ptxservq->tx_pending);
spin_unlock_bh(&pxmitpriv->lock);
if ((pfirstframe->attrib.ether_type != 0x0806) &&
(pfirstframe->attrib.ether_type != 0x888e) &&
(pfirstframe->attrib.ether_type != 0x88b4) &&
(pfirstframe->attrib.dhcp_pkt != 1))
rtw_issue_addbareq_cmd(adapt, pfirstframe);
/* 3 3. update first frame txdesc */
if ((pbuf_tail % bulksize) == 0) {
/* remove pkt_offset */
pbuf_tail -= PACKET_OFFSET_SZ;
pfirstframe->buf_addr += PACKET_OFFSET_SZ;
pfirstframe->pkt_offset--;
}
update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz);
/* 3 4. write xmit buffer to USB FIFO */
ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
rtw_write_port(adapt, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf);
/* 3 5. update statisitc */
pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
rtw_count_tx_stats(adapt, pfirstframe, pbuf_tail);
rtw_free_xmitframe(pxmitpriv, pfirstframe);
return true;
}
static s32 xmitframe_direct(struct adapter *adapt, struct xmit_frame *pxmitframe)
{
s32 res = _SUCCESS;
res = rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
if (res == _SUCCESS)
rtw_dump_xframe(adapt, pxmitframe);
return res;
}
/*
* Return
* true dump packet directly
* false enqueue packet
*/
static s32 pre_xmitframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
{
s32 res;
struct xmit_buf *pxmitbuf = NULL;
struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct mlme_priv *pmlmepriv = &adapt->mlmepriv;
spin_lock_bh(&pxmitpriv->lock);
if (rtw_txframes_sta_ac_pending(adapt, pattrib) > 0)
goto enqueue;
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING))
goto enqueue;
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (!pxmitbuf)
goto enqueue;
spin_unlock_bh(&pxmitpriv->lock);
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf;
pxmitbuf->priv_data = pxmitframe;
if (xmitframe_direct(adapt, pxmitframe) != _SUCCESS) {
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
rtw_free_xmitframe(pxmitpriv, pxmitframe);
}
return true;
enqueue:
res = rtw_xmit_classifier(adapt, pxmitframe);
spin_unlock_bh(&pxmitpriv->lock);
if (res != _SUCCESS) {
rtw_free_xmitframe(pxmitpriv, pxmitframe);
/* Trick, make the statistics correct */
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
return true;
}
return false;
}
s32 rtl8188eu_mgnt_xmit(struct adapter *adapt, struct xmit_frame *pmgntframe)
{
return rtw_dump_xframe(adapt, pmgntframe);
}
/*
* Return
* true dump packet directly ok
* false temporary can't transmit packets to hardware
*/
s32 rtl8188eu_hal_xmit(struct adapter *adapt, struct xmit_frame *pxmitframe)
{
return pre_xmitframe(adapt, pxmitframe);
}

1069
drivers/staging/r8188eu/hal/usb_halinit.c
View File

File diff suppressed because it is too large Load Diff

476
drivers/staging/r8188eu/hal/usb_ops_linux.c
View File

@ -1,476 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/osdep_intf.h"
#include "../include/usb_ops.h"
#include "../include/rtl8188e_hal.h"
#define VENDOR_CMD_MAX_DATA_LEN 254
#define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */
static int usb_read(struct adapter *adapt, u16 value, void *data, u8 size)
{
struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt);
struct usb_device *udev = dvobjpriv->pusbdev;
int status;
u8 io_buf[4];
if (adapt->bSurpriseRemoved)
return -EPERM;
status = usb_control_msg_recv(udev, 0, REALTEK_USB_VENQT_CMD_REQ,
REALTEK_USB_VENQT_READ, value,
REALTEK_USB_VENQT_CMD_IDX, io_buf,
size, RTW_USB_CONTROL_MSG_TIMEOUT,
GFP_KERNEL);
if (status == -ESHUTDOWN ||
status == -ENODEV ||
status == -ENOENT) {
/*
* device or controller has been disabled due to
* some problem that could not be worked around,
* device or bus doesn’t exist, endpoint does not
* exist or is not enabled.
*/
adapt->bSurpriseRemoved = true;
return status;
}
if (status < 0) {
if (rtw_inc_and_chk_continual_urb_error(dvobjpriv))
adapt->bSurpriseRemoved = true;
return status;
}
rtw_reset_continual_urb_error(dvobjpriv);
memcpy(data, io_buf, size);
return status;
}
static int usb_write(struct adapter *adapt, u16 value, void *data, u8 size)
{
struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt);
struct usb_device *udev = dvobjpriv->pusbdev;
int status;
u8 io_buf[VENDOR_CMD_MAX_DATA_LEN];
if (adapt->bSurpriseRemoved)
return -EPERM;
memcpy(io_buf, data, size);
status = usb_control_msg_send(udev, 0, REALTEK_USB_VENQT_CMD_REQ,
REALTEK_USB_VENQT_WRITE, value,
REALTEK_USB_VENQT_CMD_IDX, io_buf,
size, RTW_USB_CONTROL_MSG_TIMEOUT,
GFP_KERNEL);
if (status == -ESHUTDOWN ||
status == -ENODEV ||
status == -ENOENT) {
/*
* device or controller has been disabled due to
* some problem that could not be worked around,
* device or bus doesn’t exist, endpoint does not
* exist or is not enabled.
*/
adapt->bSurpriseRemoved = true;
return status;
}
if (status < 0) {
if (rtw_inc_and_chk_continual_urb_error(dvobjpriv))
adapt->bSurpriseRemoved = true;
return status;
}
rtw_reset_continual_urb_error(dvobjpriv);
return status;
}
int __must_check rtw_read8(struct adapter *adapter, u32 addr, u8 *data)
{
u16 value = addr & 0xffff;
return usb_read(adapter, value, data, 1);
}
int __must_check rtw_read16(struct adapter *adapter, u32 addr, u16 *data)
{
u16 value = addr & 0xffff;
__le16 le_data;
int res;
res = usb_read(adapter, value, &le_data, 2);
if (res)
return res;
*data = le16_to_cpu(le_data);
return 0;
}
int __must_check rtw_read32(struct adapter *adapter, u32 addr, u32 *data)
{
u16 value = addr & 0xffff;
__le32 le_data;
int res;
res = usb_read(adapter, value, &le_data, 4);
if (res)
return res;
*data = le32_to_cpu(le_data);
return 0;
}
int rtw_write8(struct adapter *adapter, u32 addr, u8 val)
{
u16 value = addr & 0xffff;
int ret;
ret = usb_write(adapter, value, &val, 1);
return RTW_STATUS_CODE(ret);
}
int rtw_write16(struct adapter *adapter, u32 addr, u16 val)
{
u16 value = addr & 0xffff;
__le16 data = cpu_to_le16(val);
int ret;
ret = usb_write(adapter, value, &data, 2);
return RTW_STATUS_CODE(ret);
}
int rtw_write32(struct adapter *adapter, u32 addr, u32 val)
{
u16 value = addr & 0xffff;
__le32 data = cpu_to_le32(val);
int ret;
ret = usb_write(adapter, value, &data, 4);
return RTW_STATUS_CODE(ret);
}
int rtw_writeN(struct adapter *adapter, u32 addr, u32 length, u8 *data)
{
u16 value = addr & 0xffff;
if (length > VENDOR_CMD_MAX_DATA_LEN)
return -EINVAL;
return usb_write(adapter, value, data, length);
}
static void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf)
{
struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf;
if (txrpt_ccx->int_ccx) {
if (txrpt_ccx->pkt_ok)
rtw_ack_tx_done(&adapter->xmitpriv,
RTW_SCTX_DONE_SUCCESS);
else
rtw_ack_tx_done(&adapter->xmitpriv,
RTW_SCTX_DONE_CCX_PKT_FAIL);
}
}
static int recvbuf2recvframe(struct adapter *adapt, struct sk_buff *pskb)
{
u8 *pbuf;
u8 shift_sz = 0;
u16 pkt_cnt;
u32 pkt_offset, skb_len, alloc_sz;
s32 transfer_len;
struct recv_stat *prxstat;
struct phy_stat *pphy_status = NULL;
struct sk_buff *pkt_copy = NULL;
struct recv_frame *precvframe = NULL;
struct rx_pkt_attrib *pattrib = NULL;
struct hal_data_8188e *haldata = &adapt->haldata;
struct recv_priv *precvpriv = &adapt->recvpriv;
struct __queue *pfree_recv_queue = &precvpriv->free_recv_queue;
transfer_len = (s32)pskb->len;
pbuf = pskb->data;
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2) >> 16) & 0xff;
do {
prxstat = (struct recv_stat *)pbuf;
precvframe = rtw_alloc_recvframe(pfree_recv_queue);
if (!precvframe)
goto _exit_recvbuf2recvframe;
INIT_LIST_HEAD(&precvframe->list);
precvframe->precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->len = 0;
update_recvframe_attrib_88e(precvframe, prxstat);
pattrib = &precvframe->attrib;
if ((pattrib->crc_err) || (pattrib->icv_err)) {
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
if ((pattrib->physt) && (pattrib->pkt_rpt_type == NORMAL_RX))
pphy_status = (struct phy_stat *)(pbuf + RXDESC_OFFSET);
pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) {
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
shift_sz = 6;
else
shift_sz = 0;
skb_len = pattrib->pkt_len;
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
if (skb_len <= 1650)
alloc_sz = 1664;
else
alloc_sz = skb_len + 14;
} else {
alloc_sz = skb_len;
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
pkt_copy = netdev_alloc_skb(adapt->pnetdev, alloc_sz);
if (pkt_copy) {
precvframe->pkt = pkt_copy;
precvframe->rx_head = pkt_copy->data;
precvframe->rx_end = pkt_copy->data + alloc_sz;
skb_reserve(pkt_copy, 8 - ((size_t)(pkt_copy->data) & 7));/* force pkt_copy->data at 8-byte alignment address */
skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */
memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
precvframe->rx_tail = pkt_copy->data;
precvframe->rx_data = pkt_copy->data;
} else {
if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
precvframe->pkt = skb_clone(pskb, GFP_ATOMIC);
if (precvframe->pkt) {
precvframe->rx_tail = pbuf + pattrib->drvinfo_sz + RXDESC_SIZE;
precvframe->rx_head = precvframe->rx_tail;
precvframe->rx_data = precvframe->rx_tail;
precvframe->rx_end = pbuf + pattrib->drvinfo_sz + RXDESC_SIZE + alloc_sz;
} else {
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
}
recvframe_put(precvframe, skb_len);
pkt_offset = (u16)round_up(pkt_offset, 128);
if (pattrib->pkt_rpt_type == NORMAL_RX) { /* Normal rx packet */
if (pattrib->physt)
update_recvframe_phyinfo_88e(precvframe, (struct phy_stat *)pphy_status);
rtw_recv_entry(precvframe);
} else {
/* enqueue recvframe to txrtp queue */
if (pattrib->pkt_rpt_type == TX_REPORT1) {
/* CCX-TXRPT ack for xmit mgmt frames. */
handle_txrpt_ccx_88e(adapt, precvframe->rx_data);
} else if (pattrib->pkt_rpt_type == TX_REPORT2) {
ODM_RA_TxRPT2Handle_8188E(
&haldata->odmpriv,
precvframe->rx_data,
pattrib->pkt_len,
pattrib->MacIDValidEntry[0],
pattrib->MacIDValidEntry[1]
);
}
rtw_free_recvframe(precvframe, pfree_recv_queue);
}
pkt_cnt--;
transfer_len -= pkt_offset;
pbuf += pkt_offset;
precvframe = NULL;
pkt_copy = NULL;
if (transfer_len > 0 && pkt_cnt == 0)
pkt_cnt = (le32_to_cpu(prxstat->rxdw2) >> 16) & 0xff;
} while ((transfer_len > 0) && (pkt_cnt > 0));
_exit_recvbuf2recvframe:
return _SUCCESS;
}
void rtl8188eu_recv_tasklet(unsigned long priv)
{
struct sk_buff *pskb;
struct adapter *adapt = (struct adapter *)priv;
struct recv_priv *precvpriv = &adapt->recvpriv;
while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) {
if ((adapt->bDriverStopped) || (adapt->bSurpriseRemoved)) {
dev_kfree_skb_any(pskb);
break;
}
recvbuf2recvframe(adapt, pskb);
skb_reset_tail_pointer(pskb);
pskb->len = 0;
skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
}
}
static void usb_read_port_complete(struct urb *purb)
{
struct recv_buf *precvbuf = (struct recv_buf *)purb->context;
struct adapter *adapt = (struct adapter *)precvbuf->adapter;
struct recv_priv *precvpriv = &adapt->recvpriv;
precvpriv->rx_pending_cnt--;
if (adapt->bSurpriseRemoved || adapt->bDriverStopped || adapt->bReadPortCancel) {
precvbuf->reuse = true;
return;
}
if (purb->status == 0) { /* SUCCESS */
if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) {
precvbuf->reuse = true;
rtw_read_port(adapt, precvbuf);
} else {
rtw_reset_continual_urb_error(adapter_to_dvobj(adapt));
skb_put(precvbuf->pskb, purb->actual_length);
skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb);
if (skb_queue_len(&precvpriv->rx_skb_queue) <= 1)
tasklet_schedule(&precvpriv->recv_tasklet);
precvbuf->pskb = NULL;
precvbuf->reuse = false;
rtw_read_port(adapt, precvbuf);
}
} else {
skb_put(precvbuf->pskb, purb->actual_length);
precvbuf->pskb = NULL;
if (rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(adapt)))
adapt->bSurpriseRemoved = true;
switch (purb->status) {
case -EINVAL:
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
case -ENOENT:
adapt->bDriverStopped = true;
break;
case -EPROTO:
case -EOVERFLOW:
precvbuf->reuse = true;
rtw_read_port(adapt, precvbuf);
break;
case -EINPROGRESS:
break;
default:
break;
}
}
}
int rtw_read_port(struct adapter *adapter, struct recv_buf *precvbuf)
{
struct urb *purb = NULL;
struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter);
struct recv_priv *precvpriv = &adapter->recvpriv;
struct usb_device *pusbd = pdvobj->pusbdev;
int err;
unsigned int pipe;
size_t tmpaddr = 0;
size_t alignment = 0;
if (adapter->bDriverStopped || adapter->bSurpriseRemoved)
return -EPERM;
if (!precvbuf)
return -ENOMEM;
if (!precvbuf->reuse || !precvbuf->pskb) {
precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue);
if (precvbuf->pskb)
precvbuf->reuse = true;
}
/* re-assign for linux based on skb */
if (!precvbuf->reuse || !precvbuf->pskb) {
precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
if (!precvbuf->pskb)
return -ENOMEM;
tmpaddr = (size_t)precvbuf->pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
} else { /* reuse skb */
precvbuf->reuse = false;
}
precvpriv->rx_pending_cnt++;
purb = precvbuf->purb;
/* translate DMA FIFO addr to pipehandle */
pipe = usb_rcvbulkpipe(pusbd, pdvobj->RtInPipe);
usb_fill_bulk_urb(purb, pusbd, pipe,
precvbuf->pskb->data,
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);/* context is precvbuf */
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != (-EPERM)))
return err;
return 0;
}
void rtl8188eu_xmit_tasklet(unsigned long priv)
{
struct adapter *adapt = (struct adapter *)priv;
if (check_fwstate(&adapt->mlmepriv, _FW_UNDER_SURVEY))
return;
do {
if (adapt->bDriverStopped || adapt->bSurpriseRemoved || adapt->bWritePortCancel)
break;
} while (rtl8188eu_xmitframe_complete(adapt));
}

97
drivers/staging/r8188eu/include/Hal8188EPhyCfg.h
View File

@ -1,97 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __INC_HAL8188EPHYCFG_H__
#define __INC_HAL8188EPHYCFG_H__
#define MAX_AGGR_NUM 0x07
enum rf_radio_path {
RF_PATH_A = 0, /* Radio Path A */
RF_PATH_B = 1, /* Radio Path B */
};
#define MAX_PG_GROUP 13
#define RF_PATH_MAX 3
#define MAX_TX_COUNT 4 /* path numbers */
#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
*ch9~11, ch12~13, CH 14
* total three groups */
struct bb_reg_def {
u32 rfintfs; /* set software control: */
/* 0x870~0x877[8 bytes] */
u32 rfintfi; /* readback data: */
/* 0x8e0~0x8e7[8 bytes] */
u32 rfintfo; /* output data: */
/* 0x860~0x86f [16 bytes] */
u32 rfintfe; /* output enable: */
/* 0x860~0x86f [16 bytes] */
u32 rf3wireOffset; /* LSSI data: */
/* 0x840~0x84f [16 bytes] */
u32 rfLSSI_Select; /* BB Band Select: */
/* 0x878~0x87f [8 bytes] */
u32 rfTxGainStage; /* Tx gain stage: */
/* 0x80c~0x80f [4 bytes] */
u32 rfHSSIPara1; /* wire parameter control1 : */
/* 0x820~0x823,0x828~0x82b,
* 0x830~0x833, 0x838~0x83b [16 bytes] */
u32 rfHSSIPara2; /* wire parameter control2 : */
/* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
* 0x83c~0x83f [16 bytes] */
u32 rfSwitchControl; /* Tx Rx antenna control : */
/* 0x858~0x85f [16 bytes] */
u32 rfAGCControl1; /* AGC parameter control1 : */
/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
* 0xc68~0xc6b [16 bytes] */
u32 rfAGCControl2; /* AGC parameter control2 : */
/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
* 0xc6c~0xc6f [16 bytes] */
u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
* 0xc2c~0xc2f [16 bytes] */
u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
* Rx DC notch filter : */
/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
* 0xc28~0xc2b [16 bytes] */
u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
* 0xc98~0xc9b [16 bytes] */
u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
* 0xc9c~0xc9f [16 bytes] */
u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
/* 0x8a0~0x8af [16 bytes] */
u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
* Path A and B */
};
/* BB and RF register read/write */
u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
u32 mask, u32 data);
u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, u32 regaddr, u32 mask);
void rtl8188e_PHY_SetRFReg(struct adapter *adapter, u32 regaddr, u32 mask, u32 data);
/* Initialization related function */
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(struct adapter *adapter);
int PHY_BBConfig8188E(struct adapter *adapter);
/* BB TX Power R/W */
void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
/* Switch bandwidth for 8192S */
void PHY_SetBWMode8188E(struct adapter *adapter,
enum ht_channel_width chnlwidth, unsigned char offset);
/* channel switch related funciton */
void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
u32 mask, u32 data);
#endif

1072
drivers/staging/r8188eu/include/Hal8188EPhyReg.h
View File

File diff suppressed because it is too large Load Diff

49
drivers/staging/r8188eu/include/Hal8188ERateAdaptive.h
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@ -1,49 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright (c) 2011 Realtek Semiconductor Corp. */
#ifndef __INC_RA_H
#define __INC_RA_H
/* Module Name: RateAdaptive.h
* Abstract: Prototype of RA and related data structure.
*/
#include <linux/bitfield.h>
/* Rate adaptive define */
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
/* TX report 2 format in Rx desc */
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__rxstatusdesc) \
le32_get_bits(*(__le32 *)__rxstatusdesc, GENMASK(8, 0))
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__rxstatusdesc) \
le32_to_cpu((*(__le32 *)(__rxstatusdesc + 16))
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__rxstatusdesc) \
le32_to_cpu((*(__le32 *)(__rxstatusdesc + 20))
/* End rate adaptive define */
int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm);
int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 MacID);
u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 MacID,
u8 RateID, u32 RateMask,
u8 SGIEnable);
void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid,
u8 rssi);
void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm,
u8 *txrpt_buf, u16 txrpt_len,
u32 validentry0, u32 validentry1);
void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime);
#endif

27
drivers/staging/r8188eu/include/HalHWImg8188E_BB.h
View File

@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H
/* static bool CheckCondition(const u32 Condition, const u32 Hex); */
/******************************************************************************
* AGC_TAB_1T.TXT
******************************************************************************/
int ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *odm);
/******************************************************************************
* PHY_REG_1T.TXT
******************************************************************************/
int ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *odm);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm);
#endif

12
drivers/staging/r8188eu/include/HalHWImg8188E_MAC.h
View File

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
int ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *pDM_Odm);
#endif /* end of HWIMG_SUPPORT */

13
drivers/staging/r8188eu/include/HalHWImg8188E_RF.h
View File

@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
int ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *odm);
#endif /* end of HWIMG_SUPPORT */

36
drivers/staging/r8188eu/include/HalPhyRf_8188e.h
View File

@ -1,36 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
void ODM_TxPwrTrackAdjust88E(struct odm_dm_struct *pDM_Odm,
u8 Type, /* 0 = OFDM, 1 = CCK */
u8 *pDirection,/* 1 = +(incr) 2 = -(decr) */
u32 *pOutWriteVal); /* Tx tracking CCK/OFDM BB
* swing index adjust */
void odm_TXPowerTrackingCallback_ThermalMeter_8188E(struct adapter *Adapter);
/* 1 7. IQK */
void PHY_IQCalibrate_8188E(struct adapter *Adapter, bool ReCovery);
/* LC calibrate */
void PHY_LCCalibrate_8188E(struct adapter *pAdapter);
/* AP calibrate */
void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter);
void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg,
u32 *ADDABackup, u32 RegisterNum);
void _PHY_MACSettingCalibration(struct adapter *pAdapter, u32 *MACReg,
u32 *MACBackup);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

18
drivers/staging/r8188eu/include/HalPwrSeqCmd.h
View File

@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include "drv_types.h"
enum r8188eu_pwr_seq {
PWR_ON_FLOW,
DISABLE_FLOW,
LPS_ENTER_FLOW,
};
/* Prototype of protected function. */
u8 HalPwrSeqCmdParsing(struct adapter *padapter, enum r8188eu_pwr_seq seq);
#endif

42
drivers/staging/r8188eu/include/HalVerDef.h
View File

@ -1,42 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __HAL_VERSION_DEF_H__
#define __HAL_VERSION_DEF_H__
enum HAL_CHIP_TYPE {
TEST_CHIP = 0,
NORMAL_CHIP = 1,
};
enum HAL_CUT_VERSION {
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
};
enum HAL_VENDOR {
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
};
struct HAL_VERSION {
enum HAL_CHIP_TYPE ChipType;
enum HAL_CUT_VERSION CUTVersion;
enum HAL_VENDOR VendorType;
};
/* Get element */
#define GET_CVID_CHIP_TYPE(version) (((version).ChipType))
#define GET_CVID_MANUFACTUER(version) (((version).VendorType))
/* HAL_CHIP_TYPE_E */
#define IS_NORMAL_CHIP(version) \
(GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP)
/* HAL_VENDOR_E */
#define IS_CHIP_VENDOR_TSMC(version) \
(GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)
#endif

224
drivers/staging/r8188eu/include/drv_types.h
View File

@ -1,224 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
/*-----------------------------------------------------------------------------
For type defines and data structure defines
------------------------------------------------------------------------------*/
#ifndef __DRV_TYPES_H__
#define __DRV_TYPES_H__
#include "osdep_service.h"
#include "wlan_bssdef.h"
#include "rtw_ht.h"
#include "rtw_cmd.h"
#include "rtw_xmit.h"
#include "rtw_recv.h"
#include "hal_intf.h"
#include "hal_com.h"
#include "rtw_security.h"
#include "rtw_pwrctrl.h"
#include "rtw_io.h"
#include "rtw_eeprom.h"
#include "sta_info.h"
#include "rtw_mlme.h"
#include "rtw_rf.h"
#include "rtw_event.h"
#include "rtw_led.h"
#include "rtw_mlme_ext.h"
#include "rtw_p2p.h"
#include "rtw_ap.h"
#include "rtw_br_ext.h"
#include "rtl8188e_hal.h"
#include "rtw_fw.h"
#define FW_RTL8188EU "rtlwifi/rtl8188eufw.bin"
struct registry_priv {
u8 rfintfs;
u8 lbkmode;
u8 hci;
struct ndis_802_11_ssid ssid;
u8 network_mode; /* infra, ad-hoc, auto */
u8 channel;/* ad-hoc support requirement */
u8 wireless_mode;/* A, B, G, auto */
u8 scan_mode;/* active, passive */
u8 radio_enable;
u8 preamble;/* long, short, auto */
u8 vrtl_carrier_sense;/* Enable, Disable, Auto */
u8 vcs_type;/* RTS/CTS, CTS-to-self */
u16 rts_thresh;
u16 frag_thresh;
u8 adhoc_tx_pwr;
u8 soft_ap;
u8 power_mgnt;
u8 ips_mode;
u8 smart_ps;
u8 long_retry_lmt;
u8 short_retry_lmt;
u16 busy_thresh;
u8 ack_policy;
u8 software_encrypt;
u8 software_decrypt;
u8 acm_method;
/* UAPSD */
u8 wmm_enable;
u8 uapsd_enable;
u8 uapsd_max_sp;
u8 uapsd_acbk_en;
u8 uapsd_acbe_en;
u8 uapsd_acvi_en;
u8 uapsd_acvo_en;
u8 led_enable;
struct wlan_bssid_ex dev_network;
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;/* for tx */
u8 rx_stbc;
u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */
u8 lowrate_two_xmit;
u8 low_power;
u8 wifi_spec;/* !turbo_mode */
u8 channel_plan;
bool bAcceptAddbaReq;
u8 antdiv_cfg;
u8 antdiv_type;
u8 usbss_enable;/* 0:disable,1:enable */
u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
u8 hwpwrp_detect;/* 0:disable,1:enable */
u8 hw_wps_pbc;/* 0:disable,1:enable */
u8 max_roaming_times; /* the max number driver will try */
u8 fw_iol; /* enable iol without other concern */
u8 enable80211d;
u8 ifname[16];
u8 if2name[16];
u8 notch_filter;
};
#define MAX_CONTINUAL_URB_ERR 4
struct dvobj_priv {
struct adapter *if1;
/* For 92D, DMDP have 2 interface. */
u8 InterfaceNumber;
u8 NumInterfaces;
/* In /Out Pipe information */
int RtInPipe;
int RtOutPipe[3];
u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
struct rt_firmware firmware;
/*-------- below is for USB INTERFACE --------*/
u8 RtNumOutPipes;
struct usb_interface *pusbintf;
struct usb_device *pusbdev;
atomic_t continual_urb_error;
};
static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
{
/* todo: get interface type from dvobj and the return
* the dev accordingly */
return &dvobj->pusbintf->dev;
};
struct adapter {
int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
struct dvobj_priv *dvobj;
struct mlme_priv mlmepriv;
struct mlme_ext_priv mlmeextpriv;
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
struct registry_priv registrypriv;
struct pwrctrl_priv pwrctrlpriv;
struct eeprom_priv eeprompriv;
struct led_priv ledpriv;
struct wifidirect_info wdinfo;
struct hal_data_8188e haldata;
s32 bDriverStopped;
s32 bSurpriseRemoved;
u8 hw_init_completed;
s8 signal_strength;
void *cmdThread;
struct net_device *pnetdev;
/* used by rtw_rereg_nd_name related function */
struct rereg_nd_name_data {
struct net_device *old_pnetdev;
char old_ifname[IFNAMSIZ];
u8 old_ips_mode;
u8 old_bRegUseLed;
} rereg_nd_name_priv;
int bup;
struct net_device_stats stats;
struct iw_statistics iwstats;
int net_closed;
u8 bFWReady;
u8 bReadPortCancel;
u8 bWritePortCancel;
u8 bRxRSSIDisplay;
/* The driver will show up the desired channel number
* when this flag is 1. */
u8 bNotifyChannelChange;
/* The driver will show the current P2P status when the
* upper application reads it. */
u8 bShowGetP2PState;
struct adapter *pbuddy_adapter;
struct mutex *hw_init_mutex;
spinlock_t br_ext_lock;
struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
int pppoe_connection_in_progress;
unsigned char pppoe_addr[ETH_ALEN];
unsigned char scdb_mac[ETH_ALEN];
unsigned char scdb_ip[4];
struct nat25_network_db_entry *scdb_entry;
unsigned char br_mac[ETH_ALEN];
unsigned char br_ip[4];
struct br_ext_info ethBrExtInfo;
};
#define adapter_to_dvobj(adapter) (adapter->dvobj)
void rtw_handle_dualmac(struct adapter *adapter, bool init);
static inline u8 *myid(struct eeprom_priv *peepriv)
{
return peepriv->mac_addr;
}
#endif /* __DRV_TYPES_H__ */

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drivers/staging/r8188eu/include/hal_com.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __HAL_COMMON_H__
#define __HAL_COMMON_H__
/* */
/* Rate Definition */
/* */
/* CCK */
#define RATR_1M 0x00000001
#define RATR_2M 0x00000002
#define RATR_55M 0x00000004
#define RATR_11M 0x00000008
/* OFDM */
#define RATR_6M 0x00000010
#define RATR_9M 0x00000020
#define RATR_12M 0x00000040
#define RATR_18M 0x00000080
#define RATR_24M 0x00000100
#define RATR_36M 0x00000200
#define RATR_48M 0x00000400
#define RATR_54M 0x00000800
/* MCS 1 Spatial Stream */
#define RATR_MCS0 0x00001000
#define RATR_MCS1 0x00002000
#define RATR_MCS2 0x00004000
#define RATR_MCS3 0x00008000
#define RATR_MCS4 0x00010000
#define RATR_MCS5 0x00020000
#define RATR_MCS6 0x00040000
#define RATR_MCS7 0x00080000
/* MCS 2 Spatial Stream */
#define RATR_MCS8 0x00100000
#define RATR_MCS9 0x00200000
#define RATR_MCS10 0x00400000
#define RATR_MCS11 0x00800000
#define RATR_MCS12 0x01000000
#define RATR_MCS13 0x02000000
#define RATR_MCS14 0x04000000
#define RATR_MCS15 0x08000000
/* CCK */
#define RATE_1M BIT(0)
#define RATE_2M BIT(1)
#define RATE_5_5M BIT(2)
#define RATE_11M BIT(3)
/* OFDM */
#define RATE_6M BIT(4)
#define RATE_9M BIT(5)
#define RATE_12M BIT(6)
#define RATE_18M BIT(7)
#define RATE_24M BIT(8)
#define RATE_36M BIT(9)
#define RATE_48M BIT(10)
#define RATE_54M BIT(11)
/* MCS 1 Spatial Stream */
#define RATE_MCS0 BIT(12)
#define RATE_MCS1 BIT(13)
#define RATE_MCS2 BIT(14)
#define RATE_MCS3 BIT(15)
#define RATE_MCS4 BIT(16)
#define RATE_MCS5 BIT(17)
#define RATE_MCS6 BIT(18)
#define RATE_MCS7 BIT(19)
/* MCS 2 Spatial Stream */
#define RATE_MCS8 BIT(20)
#define RATE_MCS9 BIT(21)
#define RATE_MCS10 BIT(22)
#define RATE_MCS11 BIT(23)
#define RATE_MCS12 BIT(24)
#define RATE_MCS13 BIT(25)
#define RATE_MCS14 BIT(26)
#define RATE_MCS15 BIT(27)
/* ALL CCK Rate */
#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
RATR_24M | RATR_36M | RATR_48M | RATR_54M)
#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
RATR_MCS3 | RATR_MCS4 | RATR_MCS5|RATR_MCS6 | \
RATR_MCS7)
#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
RATR_MCS14 | RATR_MCS15)
/*------------------------------ Tx Desc definition Macro --------------------*/
/* pragma mark -- Tx Desc related definition. -- */
/* Rate */
/* CCK Rates, TxHT = 0 */
#define DESC_RATE1M 0x00
#define DESC_RATE2M 0x01
#define DESC_RATE5_5M 0x02
#define DESC_RATE11M 0x03
/* OFDM Rates, TxHT = 0 */
#define DESC_RATE6M 0x04
#define DESC_RATE9M 0x05
#define DESC_RATE12M 0x06
#define DESC_RATE18M 0x07
#define DESC_RATE24M 0x08
#define DESC_RATE36M 0x09
#define DESC_RATE48M 0x0a
#define DESC_RATE54M 0x0b
/* MCS Rates, TxHT = 1 */
#define DESC_RATEMCS0 0x0c
#define DESC_RATEMCS1 0x0d
#define DESC_RATEMCS2 0x0e
#define DESC_RATEMCS3 0x0f
#define DESC_RATEMCS4 0x10
#define DESC_RATEMCS5 0x11
#define DESC_RATEMCS6 0x12
#define DESC_RATEMCS7 0x13
#define DESC_RATEMCS8 0x14
#define DESC_RATEMCS9 0x15
#define DESC_RATEMCS10 0x16
#define DESC_RATEMCS11 0x17
#define DESC_RATEMCS12 0x18
#define DESC_RATEMCS13 0x19
#define DESC_RATEMCS14 0x1a
#define DESC_RATEMCS15 0x1b
#define DESC_RATEMCS15_SG 0x1c
#define DESC_RATEMCS32 0x20
/* 1 Byte long (in unit of TU) */
#define REG_P2P_CTWIN 0x0572
#define REG_NOA_DESC_SEL 0x05CF
#define REG_NOA_DESC_DURATION 0x05E0
#define REG_NOA_DESC_INTERVAL 0x05E4
#define REG_NOA_DESC_START 0x05E8
#define REG_NOA_DESC_COUNT 0x05EC
/* return the final channel plan decision */
u8 hal_com_get_channel_plan(struct adapter *padapter,
u8 hw_channel_plan,
u8 sw_channel_plan,
u8 def_channel_plan,
bool AutoLoadFail
);
u8 MRateToHwRate(u8 rate);
void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg);
#endif /* __HAL_COMMON_H__ */

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drivers/staging/r8188eu/include/hal_intf.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#ifndef __HAL_INTF_H__
#define __HAL_INTF_H__
#include "osdep_service.h"
#include "drv_types.h"
#include "Hal8188EPhyCfg.h"
typedef s32 (*c2h_id_filter)(u8 id);
int rtl8188eu_interface_configure(struct adapter *adapt);
int ReadAdapterInfo8188EU(struct adapter *Adapter);
void rtl8188eu_init_default_value(struct adapter *adapt);
void rtl8188e_SetHalODMVar(struct adapter *Adapter, void *pValue1, bool bSet);
u32 rtl8188eu_InitPowerOn(struct adapter *adapt);
void rtl8188e_EfusePowerSwitch(struct adapter *pAdapter, u8 PwrState);
void rtl8188e_ReadEFuse(struct adapter *Adapter, u16 _size_byte, u8 *pbuf);
void hal_notch_filter_8188e(struct adapter *adapter, bool enable);
void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt);
void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level);
int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter,
struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
int rtl8188eu_inirp_init(struct adapter *Adapter);
uint rtw_hal_init(struct adapter *padapter);
uint rtw_hal_deinit(struct adapter *padapter);
void rtw_hal_stop(struct adapter *padapter);
u32 rtl8188eu_hal_init(struct adapter *Adapter);
u32 rtl8188eu_hal_deinit(struct adapter *Adapter);
void rtw_hal_update_ra_mask(struct adapter *padapter, u32 mac_id, u8 level);
void rtw_hal_clone_data(struct adapter *dst_adapt,
struct adapter *src_adapt);
u8 rtw_do_join(struct adapter *padapter);
#endif /* __HAL_INTF_H__ */

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drivers/staging/r8188eu/include/ieee80211.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __IEEE80211_H
#define __IEEE80211_H
#include "osdep_service.h"
#include "drv_types.h"
#include "wifi.h"
#include <linux/wireless.h>
#define MGMT_QUEUE_NUM 5
#define ETH_TYPE_LEN 2
#define PAYLOAD_TYPE_LEN 1
#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28)
/* STA flags */
#define WLAN_STA_AUTH BIT(0)
#define WLAN_STA_ASSOC BIT(1)
#define WLAN_STA_PS BIT(2)
#define WLAN_STA_TIM BIT(3)
#define WLAN_STA_PERM BIT(4)
#define WLAN_STA_AUTHORIZED BIT(5)
#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
#define WLAN_STA_SHORT_PREAMBLE BIT(7)
#define WLAN_STA_PREAUTH BIT(8)
#define WLAN_STA_WME BIT(9)
#define WLAN_STA_MFP BIT(10)
#define WLAN_STA_HT BIT(11)
#define WLAN_STA_WPS BIT(12)
#define WLAN_STA_MAYBE_WPS BIT(13)
#define WLAN_STA_NONERP BIT(31)
#define IEEE_CMD_SET_WPA_PARAM 1
#define IEEE_CMD_SET_WPA_IE 2
#define IEEE_CMD_SET_ENCRYPTION 3
#define IEEE_CMD_MLME 4
#define IEEE_PARAM_WPA_ENABLED 1
#define IEEE_PARAM_TKIP_COUNTERMEASURES 2
#define IEEE_PARAM_DROP_UNENCRYPTED 3
#define IEEE_PARAM_PRIVACY_INVOKED 4
#define IEEE_PARAM_AUTH_ALGS 5
#define IEEE_PARAM_IEEE_802_1X 6
#define IEEE_PARAM_WPAX_SELECT 7
#define AUTH_ALG_OPEN_SYSTEM 0x1
#define AUTH_ALG_SHARED_KEY 0x2
#define AUTH_ALG_LEAP 0x00000004
#define IEEE_MLME_STA_DEAUTH 1
#define IEEE_MLME_STA_DISASSOC 2
#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2
#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3
#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4
#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5
#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6
#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7
#define IEEE_CRYPT_ALG_NAME_LEN 16
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_WEP104 BIT(2)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
#define WPA_SELECTOR_LEN 4
extern u8 RTW_WPA_OUI_TYPE[];
extern u16 RTW_WPA_VERSION;
extern u8 WPA_AUTH_KEY_MGMT_NONE[];
extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[];
extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
extern u8 WPA_CIPHER_SUITE_NONE[];
extern u8 WPA_CIPHER_SUITE_WEP40[];
extern u8 WPA_CIPHER_SUITE_TKIP[];
extern u8 WPA_CIPHER_SUITE_WRAP[];
extern u8 WPA_CIPHER_SUITE_CCMP[];
extern u8 WPA_CIPHER_SUITE_WEP104[];
#define RSN_HEADER_LEN 4
#define RSN_SELECTOR_LEN 4
extern u16 RSN_VERSION_BSD;
extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[];
extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
extern u8 RSN_CIPHER_SUITE_NONE[];
extern u8 RSN_CIPHER_SUITE_WEP40[];
extern u8 RSN_CIPHER_SUITE_TKIP[];
extern u8 RSN_CIPHER_SUITE_WRAP[];
extern u8 RSN_CIPHER_SUITE_CCMP[];
extern u8 RSN_CIPHER_SUITE_WEP104[];
enum ratr_table_mode {
RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
RATR_INX_WIRELESS_NG = 1, /* GN or N */
RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
RATR_INX_WIRELESS_N = 3,
RATR_INX_WIRELESS_GB = 4,
RATR_INX_WIRELESS_G = 5,
RATR_INX_WIRELESS_B = 6,
RATR_INX_WIRELESS_MC = 7,
RATR_INX_WIRELESS_AC_N = 8,
};
enum NETWORK_TYPE {
WIRELESS_INVALID = 0,
/* Sub-Element */
WIRELESS_11B = BIT(0), /* tx:cck only, rx:cck only, hw: cck */
WIRELESS_11G = BIT(1), /* tx:ofdm only, rx:ofdm & cck, hw:cck & ofdm*/
WIRELESS_11_24N = BIT(3), /* tx:MCS only, rx:MCS & cck, hw:MCS & cck */
/* Combination */
/* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */
WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G),
/* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */
WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N),
/* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N),
};
struct ieee_param {
u32 cmd;
u8 sta_addr[ETH_ALEN];
union {
struct {
u8 name;
u32 value;
} wpa_param;
struct {
u32 len;
u8 reserved[32];
u8 data[];
} wpa_ie;
struct {
int command;
int reason_code;
} mlme;
struct {
u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
u8 set_tx;
u32 err;
u8 idx;
u8 seq[8]; /* sequence counter (set: RX, get: TX) */
u16 key_len;
u8 key[];
} crypt;
struct {
u16 aid;
u16 capability;
int flags;
u8 tx_supp_rates[16];
struct ieee80211_ht_cap ht_cap;
} add_sta;
struct {
u8 reserved[2];/* for set max_num_sta */
u8 buf[];
} bcn_ie;
} u;
};
#define IEEE80211_DATA_LEN 2304
/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
6.2.1.1.2.
The figure in section 7.1.2 suggests a body size of up to 2312
bytes is allowed, which is a bit confusing, I suspect this
represents the 2304 bytes of real data, plus a possible 8 bytes of
WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
#define IEEE80211_HLEN 30
#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
/* this is stolen from ipw2200 driver */
#define IEEE_IBSS_MAC_HASH_SIZE 31
#define IEEE80211_3ADDR_LEN 24
#define IEEE80211_4ADDR_LEN 30
#define IEEE80211_FCS_LEN 4
#define MIN_FRAG_THRESHOLD 256U
#define MAX_FRAG_THRESHOLD 2346U
/* Frame control field constants */
#define RTW_IEEE80211_FCTL_VERS 0x0003
#define RTW_IEEE80211_FCTL_FTYPE 0x000c
#define RTW_IEEE80211_FCTL_STYPE 0x00f0
#define RTW_IEEE80211_FCTL_TODS 0x0100
#define RTW_IEEE80211_FCTL_FROMDS 0x0200
#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400
#define RTW_IEEE80211_FCTL_RETRY 0x0800
#define RTW_IEEE80211_FCTL_PM 0x1000
#define RTW_IEEE80211_FCTL_MOREDATA 0x2000
#define RTW_IEEE80211_FCTL_PROTECTED 0x4000
#define RTW_IEEE80211_FCTL_ORDER 0x8000
#define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00
#define RTW_IEEE80211_FTYPE_MGMT 0x0000
#define RTW_IEEE80211_FTYPE_CTL 0x0004
#define RTW_IEEE80211_FTYPE_DATA 0x0008
#define RTW_IEEE80211_FTYPE_EXT 0x000c
/* management */
#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020
#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030
#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040
#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050
#define RTW_IEEE80211_STYPE_BEACON 0x0080
#define RTW_IEEE80211_STYPE_ATIM 0x0090
#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0
#define RTW_IEEE80211_STYPE_AUTH 0x00B0
#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0
#define RTW_IEEE80211_STYPE_ACTION 0x00D0
/* control */
#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060
#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080
#define RTW_IEEE80211_STYPE_BACK 0x0090
#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0
#define RTW_IEEE80211_STYPE_RTS 0x00B0
#define RTW_IEEE80211_STYPE_CTS 0x00C0
#define RTW_IEEE80211_STYPE_ACK 0x00D0
#define RTW_IEEE80211_STYPE_CFEND 0x00E0
#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0
/* data */
#define RTW_IEEE80211_STYPE_DATA 0x0000
#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010
#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020
#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030
#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040
#define RTW_IEEE80211_STYPE_CFACK 0x0050
#define RTW_IEEE80211_STYPE_CFPOLL 0x0060
#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070
#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080
#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090
#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0
#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0
#define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0
#define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0
#define RTW_IEEE80211_STYPE_QOS_CFPOLL 0x00E0
#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0
/* sequence control field */
#define RTW_IEEE80211_SCTL_FRAG 0x000F
#define RTW_IEEE80211_SCTL_SEQ 0xFFF0
#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0)
#define RTW_ERP_INFO_USE_PROTECTION BIT(1)
#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)
/* QoS, QOS */
#define NORMAL_ACK 0
#define NO_ACK 1
#define NON_EXPLICIT_ACK 2
#define BLOCK_ACK 3
#ifndef ETH_P_PAE
#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
#endif /* ETH_P_PAE */
#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
#define ETH_P_ECONET 0x0018
#ifndef ETH_P_80211_RAW
#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
#endif
/* IEEE 802.11 defines */
#define P80211_OUI_LEN 3
struct ieee80211_snap_hdr {
u8 dsap; /* always 0xAA */
u8 ssap; /* always 0xAA */
u8 ctrl; /* always 0x03 */
u8 oui[P80211_OUI_LEN]; /* organizational universal id */
} __packed;
#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)
#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE)
#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)
#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)
#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ)
/* Authentication algorithms */
#define WLAN_AUTH_OPEN 0
#define WLAN_AUTH_SHARED_KEY 1
#define WLAN_AUTH_CHALLENGE_LEN 128
#define WLAN_CAPABILITY_BSS (1<<0)
#define WLAN_CAPABILITY_IBSS (1<<1)
#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
#define WLAN_CAPABILITY_PRIVACY (1<<4)
#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
#define WLAN_CAPABILITY_PBCC (1<<6)
#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
/* Status codes */
#define WLAN_STATUS_SUCCESS 0
#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
#define WLAN_STATUS_CAPS_UNSUPPORTED 10
#define WLAN_STATUS_REASSOC_NO_ASSOC 11
#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
#define WLAN_STATUS_CHALLENGE_FAIL 15
#define WLAN_STATUS_AUTH_TIMEOUT 16
#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
#define WLAN_STATUS_ASSOC_DENIED_RATES 18
/* 802.11b */
#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
/* Reason codes */
#define WLAN_REASON_UNSPECIFIED 1
#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
#define WLAN_REASON_DEAUTH_LEAVING 3
#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
#define WLAN_REASON_DISASSOC_AP_BUSY 5
#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534
#define WLAN_REASON_EXPIRATION_CHK 65535
/* Information Element IDs */
#define WLAN_EID_SSID 0
#define WLAN_EID_SUPP_RATES 1
#define WLAN_EID_FH_PARAMS 2
#define WLAN_EID_DS_PARAMS 3
#define WLAN_EID_CF_PARAMS 4
#define WLAN_EID_TIM 5
#define WLAN_EID_IBSS_PARAMS 6
#define WLAN_EID_CHALLENGE 16
/* EIDs defined by IEEE 802.11h - START */
#define WLAN_EID_PWR_CONSTRAINT 32
#define WLAN_EID_PWR_CAPABILITY 33
#define WLAN_EID_TPC_REQUEST 34
#define WLAN_EID_TPC_REPORT 35
#define WLAN_EID_SUPPORTED_CHANNELS 36
#define WLAN_EID_CHANNEL_SWITCH 37
#define WLAN_EID_MEASURE_REQUEST 38
#define WLAN_EID_MEASURE_REPORT 39
#define WLAN_EID_QUITE 40
#define WLAN_EID_IBSS_DFS 41
/* EIDs defined by IEEE 802.11h - END */
#define WLAN_EID_ERP_INFO 42
#define WLAN_EID_HT_CAP 45
#define WLAN_EID_RSN 48
#define WLAN_EID_EXT_SUPP_RATES 50
#define WLAN_EID_MOBILITY_DOMAIN 54
#define WLAN_EID_FAST_BSS_TRANSITION 55
#define WLAN_EID_TIMEOUT_INTERVAL 56
#define WLAN_EID_RIC_DATA 57
#define WLAN_EID_HT_OPERATION 61
#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62
#define WLAN_EID_20_40_BSS_COEXISTENCE 72
#define WLAN_EID_20_40_BSS_INTOLERANT 73
#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74
#define WLAN_EID_MMIE 76
#define WLAN_EID_VENDOR_SPECIFIC 221
#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC)
#define IEEE80211_MGMT_HDR_LEN 24
#define IEEE80211_DATA_HDR3_LEN 24
#define IEEE80211_DATA_HDR4_LEN 30
#define IEEE80211_STATMASK_SIGNAL (1<<0)
#define IEEE80211_STATMASK_RSSI (1<<1)
#define IEEE80211_STATMASK_NOISE (1<<2)
#define IEEE80211_STATMASK_RATE (1<<3)
#define IEEE80211_STATMASK_WEMASK 0x7
#define IEEE80211_CCK_MODULATION (1<<0)
#define IEEE80211_OFDM_MODULATION (1<<1)
#define IEEE80211_24GHZ_BAND (1<<0)
#define IEEE80211_52GHZ_BAND (1<<1)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_NUM_OFDM_RATESLEN 8
#define IEEE80211_CCK_RATE_1MB 0x02
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
#define IEEE80211_OFDM_RATE_18MB 0x24
#define IEEE80211_OFDM_RATE_24MB 0x30
#define IEEE80211_OFDM_RATE_36MB 0x48
#define IEEE80211_OFDM_RATE_48MB 0x60
#define IEEE80211_OFDM_RATE_54MB 0x6C
#define IEEE80211_BASIC_RATE_MASK 0x80
#define IEEE80211_CCK_RATE_1MB_MASK (1<<0)
#define IEEE80211_CCK_RATE_2MB_MASK (1<<1)
#define IEEE80211_CCK_RATE_5MB_MASK (1<<2)
#define IEEE80211_CCK_RATE_11MB_MASK (1<<3)
#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4)
#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5)
#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6)
#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7)
#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8)
#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9)
#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10)
#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
#define IEEE80211_CCK_RATES_MASK 0x0000000F
#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \
IEEE80211_CCK_RATE_2MB_MASK)
#define IEEE80211_CCK_DEFAULT_RATES_MASK \
(IEEE80211_CCK_BASIC_RATES_MASK | \
IEEE80211_CCK_RATE_5MB_MASK | \
IEEE80211_CCK_RATE_11MB_MASK)
#define IEEE80211_OFDM_RATES_MASK 0x00000FF0
#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
IEEE80211_OFDM_RATE_12MB_MASK | \
IEEE80211_OFDM_RATE_24MB_MASK)
#define IEEE80211_OFDM_DEFAULT_RATES_MASK \
(IEEE80211_OFDM_BASIC_RATES_MASK | \
IEEE80211_OFDM_RATE_9MB_MASK | \
IEEE80211_OFDM_RATE_18MB_MASK | \
IEEE80211_OFDM_RATE_36MB_MASK | \
IEEE80211_OFDM_RATE_48MB_MASK | \
IEEE80211_OFDM_RATE_54MB_MASK)
#define IEEE80211_DEFAULT_RATES_MASK \
(IEEE80211_OFDM_DEFAULT_RATES_MASK | \
IEEE80211_CCK_DEFAULT_RATES_MASK)
#define IEEE80211_NUM_OFDM_RATES 8
#define IEEE80211_NUM_CCK_RATES 4
#define IEEE80211_OFDM_SHIFT_MASK_A 4
/* IEEE 802.11 requires that STA supports concurrent reception of at least
* three fragmented frames. This define can be increased to support more
* concurrent frames, but it should be noted that each entry can consume about
* 2 kB of RAM and increasing cache size will slow down frame reassembly. */
#define IEEE80211_FRAG_CACHE_LEN 4
#define SEC_KEY_1 (1<<0)
#define SEC_KEY_2 (1<<1)
#define SEC_KEY_3 (1<<2)
#define SEC_KEY_4 (1<<3)
#define SEC_ACTIVE_KEY (1<<4)
#define SEC_AUTH_MODE (1<<5)
#define SEC_UNICAST_GROUP (1<<6)
#define SEC_LEVEL (1<<7)
#define SEC_ENABLED (1<<8)
#define SEC_LEVEL_0 0 /* None */
#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */
#define SEC_LEVEL_2 2 /* Level 1 + TKIP */
#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
#define SEC_LEVEL_3 4 /* Level 2 + CCMP */
#define WEP_KEYS 4
#define WEP_KEY_LEN 13
/*
802.11 data frame from AP
,-------------------------------------------------------------------.
Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
|------|------|---------|---------|---------|------|---------|------|
Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs |
| | tion | (BSSID) | | | ence | data | |
`-------------------------------------------------------------------'
Total: 28-2340 bytes
*/
#define BEACON_PROBE_SSID_ID_POSITION 12
/* Management Frame Information Element Types */
#define MFIE_TYPE_SSID 0
#define MFIE_TYPE_RATES 1
#define MFIE_TYPE_FH_SET 2
#define MFIE_TYPE_DS_SET 3
#define MFIE_TYPE_CF_SET 4
#define MFIE_TYPE_TIM 5
#define MFIE_TYPE_IBSS_SET 6
#define MFIE_TYPE_CHALLENGE 16
#define MFIE_TYPE_ERP 42
#define MFIE_TYPE_RSN 48
#define MFIE_TYPE_RATES_EX 50
#define MFIE_TYPE_GENERIC 221
/*
* These are the data types that can make up management packets
*
u16 auth_algorithm;
u16 auth_sequence;
u16 beacon_interval;
u16 capability;
u8 current_ap[ETH_ALEN];
u16 listen_interval;
struct {
u16 association_id:14, reserved:2;
} __packed;
u32 time_stamp[2];
u16 reason;
u16 status;
*/
#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
#define IEEE80211_DEFAULT_BASIC_RATE 10
/* SWEEP TABLE ENTRIES NUMBER*/
#define MAX_SWEEP_TAB_ENTRIES 42
#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7
/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
* only use 8, and then use extended rates for the remaining supported
* rates. Other APs, however, stick all of their supported rates on the
* main rates information element... */
#define MAX_RATES_LENGTH ((u8)12)
#define MAX_RATES_EX_LENGTH ((u8)16)
#define MAX_NETWORK_COUNT 128
#define MAX_CHANNEL_NUMBER 161
#define IEEE80211_SOFTMAC_SCAN_TIME 400
/* HZ / 2) */
#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
#define CRC_LENGTH 4U
#define MAX_WPA_IE_LEN (256)
#define MAX_WPS_IE_LEN (512)
#define MAX_P2P_IE_LEN (256)
#define MAX_WFD_IE_LEN (128)
#define NETWORK_EMPTY_ESSID (1<<0)
#define NETWORK_HAS_OFDM (1<<1)
#define NETWORK_HAS_CCK (1<<2)
#define IEEE80211_DTIM_MBCAST 4
#define IEEE80211_DTIM_UCAST 2
#define IEEE80211_DTIM_VALID 1
#define IEEE80211_DTIM_INVALID 0
#define IEEE80211_PS_DISABLED 0
#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
#define IW_ESSID_MAX_SIZE 32
/*
join_res:
-1: authentication fail
-2: association fail
> 0: TID
*/
#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
#define DEFAULT_FTS 2346
static inline int is_multicast_mac_addr(const u8 *addr)
{
return ((addr[0] != 0xff) && (0x01 & addr[0]));
}
static inline int is_broadcast_mac_addr(const u8 *addr)
{
return (addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) &&
(addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff);
}
#define CFG_IEEE80211_RESERVE_FCS (1<<0)
#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
#define MAXTID 16
/* Action category code */
enum rtw_ieee80211_category {
RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */
};
/* SPECTRUM_MGMT action code */
enum rtw_ieee80211_spectrum_mgmt_actioncode {
RTW_WLAN_ACTION_SPCT_MSR_REQ = 0,
RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1,
RTW_WLAN_ACTION_SPCT_TPC_REQ = 2,
RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3,
RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4,
RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
};
enum _PUBLIC_ACTION {
ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */
ACT_PUBLIC_DSE_ENABLE = 1,
ACT_PUBLIC_DSE_DEENABLE = 2,
ACT_PUBLIC_DSE_REG_LOCATION = 3,
ACT_PUBLIC_EXT_CHL_SWITCH = 4,
ACT_PUBLIC_DSE_MSR_REQ = 5,
ACT_PUBLIC_DSE_MSR_RPRT = 6,
ACT_PUBLIC_MP = 7, /* Measurement Pilot */
ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */
ACT_PUBLIC_GAS_INITIAL_REQ = 10,
ACT_PUBLIC_GAS_INITIAL_RSP = 11,
ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
ACT_PUBLIC_GAS_COMEBACK_RSP = 13,
ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,
ACT_PUBLIC_LOCATION_TRACK = 15,
ACT_PUBLIC_MAX
};
#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)
* 00:50:F2 */
#define WME_OUI_TYPE 2
#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WME_VERSION 1
#define WME_ACTION_CODE_SETUP_REQUEST 0
#define WME_ACTION_CODE_SETUP_RESPONSE 1
#define WME_ACTION_CODE_TEARDOWN 2
#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0
#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1
#define WME_SETUP_RESPONSE_STATUS_REFUSED 3
#define WME_TSPEC_DIRECTION_UPLINK 0
#define WME_TSPEC_DIRECTION_DOWNLINK 1
#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3
#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
/**
* enum rtw_ieee80211_channel_flags - channel flags
*
* Channel flags set by the regulatory control code.
*
* @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled.
* @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
* on this channel.
* @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
* @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
* @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
* is not permitted.
* @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel
* is not permitted.
*/
enum rtw_ieee80211_channel_flags {
RTW_IEEE80211_CHAN_DISABLED = 1<<0,
RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1<<1,
RTW_IEEE80211_CHAN_NO_IBSS = 1<<2,
RTW_IEEE80211_CHAN_RADAR = 1<<3,
RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
};
#define RTW_IEEE80211_CHAN_NO_HT40 \
(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
/* Represent channel details, subset of ieee80211_channel */
struct rtw_ieee80211_channel {
u16 hw_value;
u32 flags;
};
#define CHAN_FMT \
"hw_value:%u, " \
"flags:0x%08x" \
#define CHAN_ARG(channel) \
(channel)->hw_value \
, (channel)->flags \
/* Parsed Information Elements */
struct rtw_ieee802_11_elems {
u8 *ssid;
u8 ssid_len;
u8 *supp_rates;
u8 supp_rates_len;
u8 *fh_params;
u8 fh_params_len;
u8 *ds_params;
u8 ds_params_len;
u8 *cf_params;
u8 cf_params_len;
u8 *tim;
u8 tim_len;
u8 *ibss_params;
u8 ibss_params_len;
u8 *challenge;
u8 challenge_len;
u8 *erp_info;
u8 erp_info_len;
u8 *ext_supp_rates;
u8 ext_supp_rates_len;
u8 *wpa_ie;
u8 wpa_ie_len;
u8 *rsn_ie;
u8 rsn_ie_len;
u8 *wme;
u8 wme_len;
u8 *wme_tspec;
u8 wme_tspec_len;
u8 *wps_ie;
u8 wps_ie_len;
u8 *power_cap;
u8 power_cap_len;
u8 *supp_channels;
u8 supp_channels_len;
u8 *mdie;
u8 mdie_len;
u8 *ftie;
u8 ftie_len;
u8 *timeout_int;
u8 timeout_int_len;
u8 *ht_capabilities;
u8 ht_capabilities_len;
u8 *ht_operation;
u8 ht_operation_len;
u8 *vendor_ht_cap;
u8 vendor_ht_cap_len;
};
enum parse_res {
ParseOK = 0,
ParseUnknown = 1,
ParseFailed = -1
};
enum parse_res rtw_ieee802_11_parse_elems(u8 *start, uint len,
struct rtw_ieee802_11_elems *elems,
int show_errors);
u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len,
unsigned char *source, unsigned int *frlen);
u8 *rtw_set_ie(u8 *pbuf, int index, uint len, u8 *source, uint *frlen);
u8 *rtw_get_ie(u8 *pbuf, int index, int *len, int limit);
void rtw_set_supported_rate(u8 *SupportedRates, uint mode);
unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit);
unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);
int rtw_get_wpa_cipher_suite(u8 *s);
int rtw_get_wpa2_cipher_suite(u8 *s);
int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len);
int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
int *pairwise_cipher, int *is_8021x);
int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
int *pairwise_cipher, int *is_8021x);
int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len,
u8 *wpa_ie, u16 *wpa_len);
u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen);
u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id,
u8 *buf_attr, u32 *len_attr);
u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id,
u8 *buf_content, uint *len_content);
/**
* for_each_ie - iterate over continuous IEs
* @ie:
* @buf:
* @buf_len:
*/
#define for_each_ie(ie, buf, buf_len) \
for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; \
ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2))
u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id,
u8 *buf_attr, u32 *len_attr);
u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id,
u8 *buf_content, uint *len_content);
u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len,
u8 *pdata_attr);
void rtw_wlan_bssid_ex_remove_p2p_attr(struct wlan_bssid_ex *bss_ex,
u8 attr_id);
uint rtw_get_rateset_len(u8 *rateset);
struct registry_priv;
int rtw_generate_ie(struct registry_priv *pregistrypriv);
int rtw_get_bit_value_from_ieee_value(u8 val);
bool rtw_is_cckrates_included(u8 *rate);
bool rtw_is_cckratesonly_included(u8 *rate);
int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
void rtw_get_bcn_info(struct wlan_network *pnetwork);
void rtw_macaddr_cfg(u8 *mac_addr);
u16 rtw_mcs_rate(u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char *MCS_rate);
#endif /* IEEE80211_H */

416
drivers/staging/r8188eu/include/odm.h
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@ -1,416 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __HALDMOUTSRC_H__
#define __HALDMOUTSRC_H__
struct rtw_dig {
u8 PreIGValue;
u8 CurIGValue;
u8 BackupIGValue;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
u8 CurCCK_CCAThres;
u8 LargeFAHit;
u8 ForbiddenIGI;
u32 Recover_cnt;
u8 DIG_Dynamic_MIN_0;
bool bMediaConnect_0;
u32 AntDiv_RSSI_max;
u32 RSSI_max;
};
struct rtl_ps {
u8 pre_rf_state;
u8 cur_rf_state;
u8 initialize;
u32 reg_874;
u32 reg_c70;
u32 reg_85c;
u32 reg_a74;
};
struct false_alarm_stats {
u32 Cnt_Parity_Fail;
u32 Cnt_Rate_Illegal;
u32 Cnt_Crc8_fail;
u32 Cnt_Mcs_fail;
u32 Cnt_Ofdm_fail;
u32 Cnt_Cck_fail;
u32 Cnt_all;
u32 Cnt_Fast_Fsync;
u32 Cnt_SB_Search_fail;
u32 Cnt_OFDM_CCA;
u32 Cnt_CCK_CCA;
u32 Cnt_CCA_all;
u32 Cnt_BW_USC; /* Gary */
u32 Cnt_BW_LSC; /* Gary */
};
#define ODM_ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
struct sw_ant_switch {
u8 CurAntenna;
u8 SWAS_NoLink_State; /* Before link Antenna Switch check */
u8 RxIdleAnt;
};
struct edca_turbo {
bool bCurrentTurboEDCA;
bool bIsCurRDLState;
u32 prv_traffic_idx; /* edca turbo */
};
struct odm_rate_adapt {
u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
u32 LastRATR; /* RATR Register Content */
};
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#define AVG_THERMAL_NUM 8
struct odm_phy_dbg_info {
/* ODM Write,debug info */
s8 RxSNRdB[MAX_PATH_NUM_92CS];
u64 NumQryPhyStatus;
/* Others */
s32 RxEVM[MAX_PATH_NUM_92CS];
};
struct odm_per_pkt_info {
s8 Rate;
u8 StationID;
bool bPacketMatchBSSID;
bool bPacketToSelf;
bool bPacketBeacon;
};
/* 2011/10/20 MH Define Common info enum for all team. */
enum odm_common_info_def {
/* Fixed value: */
/* HOOK BEFORE REG INIT----------- */
ODM_CMNINFO_MP_TEST_CHIP,
/* HOOK BEFORE REG INIT----------- */
/* CALL BY VALUE------------- */
ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
/* CALL BY VALUE-------------*/
};
enum odm_ability_def {
/* BB ODM section BIT 0-15 */
ODM_BB_RSSI_MONITOR = BIT(4),
ODM_BB_ANT_DIV = BIT(6),
ODM_BB_PWR_TRA = BIT(8),
};
#define ODM_ITRF_USB 0x2
#define ODM_CE 0x04
/* ODM_CMNINFO_WM_MODE */
enum odm_wireless_mode {
ODM_WM_UNKNOW = 0x0,
ODM_WM_B = BIT(0),
ODM_WM_G = BIT(1),
ODM_WM_N24G = BIT(3),
ODM_WM_AUTO = BIT(5),
};
struct odm_ra_info {
u8 RateID;
u32 RateMask;
u32 RAUseRate;
u8 RateSGI;
u8 RssiStaRA;
u8 PreRssiStaRA;
u8 SGIEnable;
u8 DecisionRate;
u8 PreRate;
u8 HighestRate;
u8 LowestRate;
u32 NscUp;
u32 NscDown;
u16 RTY[5];
u32 TOTAL;
u16 DROP;
u8 Active;
u16 RptTime;
u8 RAWaitingCounter;
u8 RAPendingCounter;
u8 PTActive; /* on or off */
u8 PTTryState; /* 0 trying state, 1 for decision state */
u8 PTStage; /* 0~6 */
u8 PTStopCount; /* Stop PT counter */
u8 PTPreRate; /* if rate change do PT */
u8 PTPreRssi; /* if RSSI change 5% do PT */
u8 PTModeSS; /* decide whitch rate should do PT */
u8 RAstage; /* StageRA, decide how many times RA will be done
* between PT */
u8 PTSmoothFactor;
};
struct odm_rf_cal {
/* for tx power tracking */
u32 RegA24; /* for TempCCK */
s32 RegE94;
s32 RegE9C;
s32 RegEB4;
s32 RegEBC;
u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
* as default */
u8 TM_Trigger;
u8 InternalPA5G[2]; /* pathA / pathB */
u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
* and 1 for RFIC1 */
u8 ThermalValue;
u8 ThermalValue_LCK;
u8 ThermalValue_IQK;
u8 ThermalValue_DPK;
u8 ThermalValue_AVG[AVG_THERMAL_NUM];
u8 ThermalValue_AVG_index;
u8 ThermalValue_RxGain;
u8 ThermalValue_Crystal;
u8 ThermalValue_DPKstore;
u8 ThermalValue_DPKtrack;
bool TxPowerTrackingInProgress;
bool bDPKenable;
bool bReloadtxpowerindex;
u8 bRfPiEnable;
u8 CCK_index;
u8 OFDM_index;
bool bDoneTxpower;
u8 ThermalValue_HP[HP_THERMAL_NUM];
u8 ThermalValue_HP_index;
u8 Delta_IQK;
u8 Delta_LCK;
/* for IQK */
u32 RegC04;
u32 Reg874;
u32 RegC08;
u32 RegB68;
u32 RegB6C;
u32 Reg870;
u32 Reg860;
u32 Reg864;
bool bIQKInitialized;
bool bAntennaDetected;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
/* for APK */
u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
};
/* ODM Dynamic common info value definition */
struct fast_ant_train {
u8 antsel_rx_keep_0;
u8 antsel_rx_keep_1;
u8 antsel_rx_keep_2;
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u8 RxIdleAnt;
bool bBecomeLinked;
};
enum ant_div_type {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
};
/* Copy from SD4 defined structure. We use to support PHY DM integration. */
struct odm_dm_struct {
struct adapter *Adapter; /* For CE/NIC team */
/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
bool bCckHighPower;
u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
u8 ControlChannel;
/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
/* 1 COMMON INFORMATION */
/* Init Value */
/* HOOK BEFORE REG INIT----------- */
/* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ <20>K<EFBFBD>K = 1/2/3/<2F>K */
u32 SupportAbility;
u32 BK_SupportAbility;
u8 AntDivType;
/* HOOK BEFORE REG INIT----------- */
/* Dynamic Value */
/* POINTER REFERENCE----------- */
/* Wireless mode B/G/A/N = BIT(0)/BIT(1)/BIT(2)/BIT(3) */
u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
/* Secondary channel offset don't_care/below/above = 0/1/2 */
u8 *pSecChOffset;
/* BW info 20M/40M/80M = 0/1/2 */
enum ht_channel_width *pBandWidth;
/* Central channel location Ch1/Ch2/.... */
u8 *pChannel; /* central channel number */
/* Common info for Status */
bool *pbScanInProcess;
bool *pbPowerSaving;
/* POINTER REFERENCE----------- */
/* */
/* CALL BY VALUE------------- */
bool bLinked;
u8 RSSI_Min;
bool bIsMPChip;
bool bOneEntryOnly;
/* CALL BY VALUE------------- */
/* 2 Define STA info. */
/* _ODM_STA_INFO */
/* For MP, we need to reduce one array pointer for default port.?? */
struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
u16 CurrminRptTime;
struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
* array index. STA MacID=0,
* VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
/* Latest packet phy info (ODM write) */
struct odm_phy_dbg_info PhyDbgInfo;
/* ODM Structure */
struct fast_ant_train DM_FatTable;
struct rtw_dig DM_DigTable;
struct rtl_ps DM_PSTable;
struct false_alarm_stats FalseAlmCnt;
struct sw_ant_switch DM_SWAT_Table;
struct edca_turbo DM_EDCA_Table;
/* PSD */
bool bDMInitialGainEnable;
struct odm_rate_adapt RateAdaptive;
struct odm_rf_cal RFCalibrateInfo;
/* TX power tracking */
u8 BbSwingIdxOfdm;
u8 BbSwingIdxOfdmCurrent;
u8 BbSwingIdxOfdmBase;
bool BbSwingFlagOfdm;
u8 BbSwingIdxCck;
u8 BbSwingIdxCckCurrent;
u8 BbSwingIdxCckBase;
bool BbSwingFlagCck;
};
enum odm_bb_config_type {
CONFIG_BB_PHY_REG,
CONFIG_BB_AGC_TAB,
CONFIG_BB_AGC_TAB_2G,
CONFIG_BB_PHY_REG_PG,
};
#define DM_DIG_MAX_NIC 0x4e
#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
#define DM_DIG_MAX_AP 0x32
/* vivi 92c&92d has different definition, 20110504 */
/* this is for 92c */
#define DM_DIG_FA_TH0 0x200/* 0x20 */
#define DM_DIG_FA_TH1 0x300/* 0x100 */
#define DM_DIG_FA_TH2 0x400/* 0x200 */
/* 3=========================================================== */
/* 3 Rate Adaptive */
/* 3=========================================================== */
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
/* 3=========================================================== */
/* 3 BB Power Save */
/* 3=========================================================== */
enum dm_rf {
RF_Save = 0,
RF_Normal = 1,
RF_MAX = 2,
};
/* 3=========================================================== */
/* 3 Antenna Diversity */
/* 3=========================================================== */
enum dm_swas {
Antenna_A = 1,
Antenna_B = 2,
Antenna_MAX = 3,
};
/* Extern Global Variables. */
#define OFDM_TABLE_SIZE_92D 43
#define CCK_TABLE_SIZE 33
extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
extern u8 cck_swing_table[CCK_TABLE_SIZE][8];
/* check Sta pointer valid or not */
#define IS_STA_VALID(pSta) (pSta)
void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
bool bForceUpdate, u8 *pRATRState);
u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
u32 ra_mask, u8 rssi_level);
void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
enum odm_common_info_def CmnInfo, u32 Value);
#endif

69
drivers/staging/r8188eu/include/odm_HWConfig.h
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@ -1,69 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/* CCK Rates, TxHT = 0 */
#define DESC92C_RATE1M 0x00
#define DESC92C_RATE11M 0x03
/* MCS Rates, TxHT = 1 */
#define DESC92C_RATEMCS8 0x14
#define DESC92C_RATEMCS15 0x1b
/* structure and define */
struct phy_rx_agc_info {
#ifdef __LITTLE_ENDIAN
u8 gain:7, trsw:1;
#else
u8 trsw:1, gain:7;
#endif
};
struct phy_status_rpt {
struct phy_rx_agc_info path_agc[3];
u8 ch_corr[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;/* ch_corr_msb; */
u8 noise_power_db_msb;
u8 path_cfotail[2];
u8 pcts_mask[2];
s8 stream_rxevm[2];
u8 path_rxsnr[3];
u8 noise_power_db_lsb;
u8 rsvd_2[3];
u8 stream_csi[2];
u8 stream_target_csi[2];
s8 sig_evm;
u8 rsvd_3;
#ifdef __LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 ant_sel_b:1;
u8 ant_sel:1;
#else /* _BIG_ENDIAN_ */
u8 ant_sel:1;
u8 ant_sel_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
#endif
};
void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm,
struct phy_info *pPhyInfo,
u8 *pPhyStatus,
struct odm_per_pkt_info *pPktinfo,
struct adapter *adapt);
#endif

35
drivers/staging/r8188eu/include/odm_RTL8188E.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#define MAIN_ANT 0
#define AUX_ANT 1
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
#define SET_TX_DESC_ANTSEL_A_88E(__ptxdesc, __value) \
le32p_replace_bits((__le32 *)(__ptxdesc + 8), __value, BIT(24))
#define SET_TX_DESC_ANTSEL_B_88E(__ptxdesc, __value) \
le32p_replace_bits((__le32 *)(__ptxdesc + 8), __value, BIT(25))
#define SET_TX_DESC_ANTSEL_C_88E(__ptxdesc, __value) \
le32p_replace_bits((__le32 *)(__ptxdesc + 28), __value, BIT(29))
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm);
void ODM_AntennaDiversity_88E(struct odm_dm_struct *pDM_Odm);
void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm, u8 *pDesc,
u8 macId);
void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u8 Ant);
void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, u8 antsel_tr_mux,
u32 MacId, u8 RxPWDBAll);
void odm_FastAntTraining(struct odm_dm_struct *pDM_Odm);
#endif

47
drivers/staging/r8188eu/include/odm_RegDefine11N.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
/* 2 BB REG LIST */
/* PAGE 8 */
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_SC_CNT_11N 0x8C4
/* PAGE 9 */
#define ODM_REG_ANT_MAPPING1_11N 0x914
/* PAGE A */
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
/* PAGE B */
#define ODM_REG_LNA_SWITCH_11N 0xB2C
/* PAGE C */
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
/* PAGE D */
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
/* 2 MAC REG LIST */
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_RESP_TX_11N 0x6D8
/* DIG Related */
#define ODM_BIT_IGI_11N 0x0000007F
#endif

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drivers/staging/r8188eu/include/osdep_intf.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __OSDEP_INTF_H_
#define __OSDEP_INTF_H_
#include "osdep_service.h"
#include "drv_types.h"
int netdev_open(struct net_device *pnetdev);
int netdev_close(struct net_device *pnetdev);
u8 rtw_init_drv_sw(struct adapter *padapter);
void rtw_free_drv_sw(struct adapter *padapter);
void rtw_reset_drv_sw(struct adapter *padapter);
int rtw_start_drv_threads(struct adapter *padapter);
void rtw_stop_drv_threads (struct adapter *padapter);
void rtw_cancel_all_timer(struct adapter *padapter);
int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
struct net_device *rtw_init_netdev(struct adapter *padapter);
u16 rtw_recv_select_queue(struct sk_buff *skb);
void rtw_ips_dev_unload(struct adapter *padapter);
int rtw_ips_pwr_up(struct adapter *padapter);
void rtw_ips_pwr_down(struct adapter *padapter);
#endif /* _OSDEP_INTF_H_ */

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drivers/staging/r8188eu/include/osdep_service.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __OSDEP_SERVICE_H_
#define __OSDEP_SERVICE_H_
#include <linux/sched/signal.h>
#define _FAIL 0
#define _SUCCESS 1
#define RTW_RX_HANDLED 2
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kref.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/circ_buf.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
#include <asm/atomic.h>
#include <linux/io.h>
#include <linux/semaphore.h>
#include <linux/sem.h>
#include <linux/sched.h>
#include <linux/etherdevice.h>
#include <linux/wireless.h>
#include <net/iw_handler.h>
#include <linux/if_arp.h>
#include <linux/rtnetlink.h>
#include <linux/delay.h>
#include <linux/proc_fs.h> /* Necessary because we use the proc fs */
#include <linux/interrupt.h> /* for struct tasklet_struct */
#include <linux/ip.h>
#include <linux/kthread.h>
#include <linux/vmalloc.h>
#include <linux/usb.h>
#include <linux/usb/ch9.h>
struct __queue {
struct list_head queue;
spinlock_t lock;
};
static inline struct list_head *get_list_head(struct __queue *queue)
{
return (&(queue->queue));
}
static inline void _set_timer(struct timer_list *ptimer, u32 delay_time)
{
mod_timer(ptimer, jiffies + msecs_to_jiffies(delay_time));
}
static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
{
return netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3));
}
int RTW_STATUS_CODE(int error_code);
void *rtw_malloc2d(int h, int w, int size);
#define rtw_init_queue(q) \
do { \
INIT_LIST_HEAD(&((q)->queue)); \
spin_lock_init(&((q)->lock)); \
} while (0)
static inline unsigned char _cancel_timer_ex(struct timer_list *ptimer)
{
return del_timer_sync(ptimer);
}
static inline void flush_signals_thread(void)
{
if (signal_pending (current))
flush_signals(current);
}
struct rtw_netdev_priv_indicator {
void *priv;
u32 sizeof_priv;
};
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv,
void *old_priv);
struct net_device *rtw_alloc_etherdev(int sizeof_priv);
#define rtw_netdev_priv(netdev) \
(((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv)
void rtw_free_netdev(struct net_device *netdev);
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ndev->name
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) adapter->pnetdev->name
#define FUNC_NDEV_FMT "%s(%s)"
#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
#define FUNC_ADPT_FMT "%s(%s)"
#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name
#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1)
/* Macros for handling unaligned memory accesses */
#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
#define RTW_PUT_BE16(a, val) \
do { \
(a)[0] = ((u16) (val)) >> 8; \
(a)[1] = ((u16) (val)) & 0xff; \
} while (0)
#define RTW_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
((u32) (a)[2]))
#define RTW_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
struct rtw_cbuf {
u32 write;
u32 read;
u32 size;
void *bufs[];
};
bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
int wifirate2_ratetbl_inx(unsigned char rate);
#endif

90
drivers/staging/r8188eu/include/rtl8188e_cmd.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTL8188E_CMD_H__
#define __RTL8188E_CMD_H__
enum RTL8188E_H2C_CMD_ID {
/* Class Common */
H2C_COM_RSVD_PAGE = 0x00,
H2C_COM_MEDIA_STATUS_RPT = 0x01,
H2C_COM_SCAN = 0x02,
H2C_COM_KEEP_ALIVE = 0x03,
H2C_COM_DISCNT_DECISION = 0x04,
H2C_COM_INIT_OFFLOAD = 0x06,
H2C_COM_REMOTE_WAKE_CTL = 0x07,
H2C_COM_AP_OFFLOAD = 0x08,
H2C_COM_BCN_RSVD_PAGE = 0x09,
H2C_COM_PROB_RSP_RSVD_PAGE = 0x0A,
/* Class PS */
H2C_PS_PWR_MODE = 0x20,
H2C_PS_TUNE_PARA = 0x21,
H2C_PS_TUNE_PARA_2 = 0x22,
H2C_PS_LPS_PARA = 0x23,
H2C_PS_P2P_OFFLOAD = 0x24,
/* Class DM */
H2C_DM_MACID_CFG = 0x40,
H2C_DM_TXBF = 0x41,
};
struct cmd_msg_parm {
u8 eid; /* element id */
u8 sz; /* sz */
u8 buf[6];
};
struct setpwrmode_parm {
u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
u8 SmartPS_RLBM;/* LPS= 0:PS_Poll,1:PS_Poll,2:NullData,WMM= 0:PS_Poll,1:NullData */
u8 AwakeInterval; /* unit: beacon interval */
u8 bAllQueueUAPSD;
u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
};
struct H2C_SS_RFOFF_PARAM {
u8 ROFOn; /* 1: on, 0:off */
u16 gpio_period; /* unit: 1024 us */
} __packed;
struct joinbssrpt_parm {
u8 OpMode; /* RT_MEDIA_STATUS */
};
struct rsvdpage_loc {
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
u8 LocQosNull;
u8 LocBTQosNull;
};
struct P2P_PS_Offload_t {
u8 Offload_En:1;
u8 role:1; /* 1: Owner, 0: Client */
u8 CTWindow_En:1;
u8 NoA0_En:1;
u8 NoA1_En:1;
u8 AllStaSleep:1; /* Only valid in Owner */
u8 discovery:1;
u8 rsvd:1;
};
struct P2P_PS_CTWPeriod_t {
u8 CTWPeriod; /* TU */
};
/* host message to firmware cmd */
void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode);
void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus);
u8 rtl8188e_set_raid_cmd(struct adapter *padapter, u32 mask);
void rtl8188e_Add_RateATid(struct adapter *padapter, u32 bitmap, u8 arg,
u8 rssi_level);
void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state);
void CheckFwRsvdPageContent(struct adapter *adapt);
void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, u16 mstatus_rpt);
#endif/* __RTL8188E_CMD_H__ */

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drivers/staging/r8188eu/include/rtl8188e_dm.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTL8188E_DM_H__
#define __RTL8188E_DM_H__
enum{
UP_LINK,
DOWN_LINK,
};
struct dm_priv {
u32 InitODMFlag;
/* Lower Signal threshold for Rate Adaptive */
int EntryMinUndecoratedSmoothedPWDB;
int MinUndecoratedPWDBForDM;
};
void rtl8188e_init_dm_priv(struct adapter *adapt);
void rtl8188e_InitHalDm(struct adapter *adapt);
void rtl8188e_HalDmWatchDog(struct adapter *adapt);
void AntDivCompare8188E(struct adapter *adapt, struct wlan_bssid_ex *dst,
struct wlan_bssid_ex *src);
u8 AntDivBeforeLink8188E(struct adapter *adapt);
#endif

181
drivers/staging/r8188eu/include/rtl8188e_hal.h
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@ -1,181 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTL8188E_HAL_H__
#define __RTL8188E_HAL_H__
/* include HAL Related header after HAL Related compiling flags */
#include "rtl8188e_spec.h"
#include "Hal8188EPhyReg.h"
#include "Hal8188EPhyCfg.h"
#include "rtl8188e_rf.h"
#include "rtl8188e_dm.h"
#include "rtl8188e_recv.h"
#include "rtl8188e_xmit.h"
#include "rtl8188e_cmd.h"
#include "rtw_efuse.h"
#include "odm.h"
#include "odm_HWConfig.h"
#include "odm_RegDefine11N.h"
#include "HalPhyRf_8188e.h"
#include "Hal8188ERateAdaptive.h"
#include "HalHWImg8188E_MAC.h"
#include "HalHWImg8188E_RF.h"
#include "HalHWImg8188E_BB.h"
#include "odm_RTL8188E.h"
#define DRVINFO_SZ 4 /* unit is 8bytes */
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
#define DRIVER_EARLY_INT_TIME 0x05
#define BCN_DMA_ATIME_INT_TIME 0x02
#define MAX_RX_DMA_BUFFER_SIZE_88E \
0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
* WOLPattern(16*24)) */
#define TX_SELE_LQ BIT(1) /* Low Queue */
#define TX_SELE_NQ BIT(2) /* Normal Queue */
/* Note: We will divide number of page equally for each queue other
* than public queue! */
/* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */
/* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */
/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
* null-data */
#define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */
#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
#include "HalVerDef.h"
#include "hal_com.h"
/* Channel Plan */
enum ChannelPlan {
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPA = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,
CHPL_ISRAEL = 7,
CHPL_TELEC = 8,
CHPL_GLOBAL = 9,
CHPL_WORLD = 10,
};
struct txpowerinfo24g {
u8 IndexCCK_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
u8 IndexBW40_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
/* If only one tx, only BW20 and OFDM are used. */
s8 CCK_Diff[RF_PATH_MAX][MAX_TX_COUNT];
s8 OFDM_Diff[RF_PATH_MAX][MAX_TX_COUNT];
s8 BW20_Diff[RF_PATH_MAX][MAX_TX_COUNT];
s8 BW40_Diff[RF_PATH_MAX][MAX_TX_COUNT];
};
#define EFUSE_REAL_CONTENT_LEN 512
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
#define EFUSE_REAL_CONTENT_LEN_88E 256
#define EFUSE_MAP_LEN_88E 512
#define EFUSE_MAX_SECTION_88E 64
/* To prevent out of boundary programming case, leave 1byte and program
* full section */
/* 9bytes + 1byt + 5bytes and pre 1byte. */
/* For worst case: */
/* | 2byte|----8bytes----|1byte|--7bytes--| 92D */
/* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
#define EFUSE_OOB_PROTECT_BYTES_88E 18
#define EFUSE_PROTECT_BYTES_BANK 16
#define USB_RXAGG_PAGE_COUNT 48
#define USB_RXAGG_PAGE_TIMEOUT 0x4
struct hal_data_8188e {
struct HAL_VERSION VersionID;
/* current WIFI_PHY values */
enum ht_channel_width CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
u8 EEPROMRegulatory;
u8 EEPROMThermalMeter;
u8 Index24G_CCK_Base[CHANNEL_MAX_NUMBER];
u8 Index24G_BW40_Base[CHANNEL_MAX_NUMBER];
/* If only one tx, only BW20 and OFDM are used. */
s8 OFDM_24G_Diff[MAX_TX_COUNT];
s8 BW20_24G_Diff[MAX_TX_COUNT];
/* HT 20<->40 Pwr diff */
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
/* For HT<->legacy pwr diff */
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
/* For power group */
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
/* Read/write are allow for following hardware information variables */
u8 pwrGroupCnt;
u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
u8 CrystalCap;
u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
struct bb_reg_def PHYRegDef;
u32 RfRegChnlVal;
/* for host message to fw */
u8 LastHMEBoxNum;
u8 fw_ractrl;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 RegCR_1;
struct dm_priv dmpriv;
struct odm_dm_struct odmpriv;
u8 CurAntenna;
u8 AntDivCfg;
u8 TRxAntDivType;
u8 out_ep_extra_queues;
struct P2P_PS_Offload_t p2p_ps_offload;
/* Auto FSM to Turn On, include clock, isolation, power control
* for MAC only */
u8 bMacPwrCtrlOn;
};
s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
/* EFuse */
void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
bool AutoLoadFail);
void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
bool AutoLoadFail);
void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
bool AutoLoadFail);
void Hal_ReadThermalMeter_88E(struct adapter *padapter, u8 *PROMContent,
bool AutoloadFail);
void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
bool AutoLoadFail);
void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
bool AutoLoadFail);
void rtl8188e_read_chip_version(struct adapter *padapter);
s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
void rtw_cancel_all_timer(struct adapter *padapter);
#endif /* __RTL8188E_HAL_H__ */

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drivers/staging/r8188eu/include/rtl8188e_recv.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTL8188E_RECV_H__
#define __RTL8188E_RECV_H__
#define TX_RPT1_PKT_LEN 8
#define NR_PREALLOC_RECV_SKB (8)
#define NR_RECVBUFF (4)
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
struct phy_stat {
unsigned int phydw0;
unsigned int phydw1;
unsigned int phydw2;
unsigned int phydw3;
unsigned int phydw4;
unsigned int phydw5;
unsigned int phydw6;
unsigned int phydw7;
};
/* Rx smooth factor */
#define Rx_Smooth_Factor (20)
enum rx_packet_type {
NORMAL_RX,/* Normal rx packet */
TX_REPORT1,/* CCX */
TX_REPORT2,/* TX RPT */
HIS_REPORT,/* USB HISR RPT */
};
void rtl8188eu_recv_tasklet(unsigned long priv);
void update_recvframe_phyinfo_88e(struct recv_frame *fra, struct phy_stat *phy);
void update_recvframe_attrib_88e(struct recv_frame *fra, struct recv_stat *stat);
#endif

18
drivers/staging/r8188eu/include/rtl8188e_rf.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTL8188E_RF_H__
#define __RTL8188E_RF_H__
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
int phy_RF6052_Config_ParaFile(struct adapter *Adapter);
void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
enum ht_channel_width Bandwidth);
void rtl8188e_PHY_RF6052SetCckTxPower(struct adapter *Adapter, u8 *level);
void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *ofdm,
u8 *pwrbw20, u8 *pwrbw40, u8 channel);
#endif/* __RTL8188E_RF_H__ */

1142
drivers/staging/r8188eu/include/rtl8188e_spec.h
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130
drivers/staging/r8188eu/include/rtl8188e_xmit.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTL8188E_XMIT_H__
#define __RTL8188E_XMIT_H__
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
#define QSLT_MGNT 0x12
/* For 88e early mode */
#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0))
#define SET_EARLYMODE_LEN0(__pAddr, __Value) \
le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4))
#define SET_EARLYMODE_LEN1(__paddr, __value) \
le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16))
#define SET_EARLYMODE_LEN2_1(__pdr, __vValue) \
le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28))
#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0))
#define SET_EARLYMODE_LEN3(__pAddr, __Value) \
le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8))
#define SET_EARLYMODE_LEN4(__paAddr, __vValue) \
le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20))
/* defined for TX DESC Operation */
#define MAX_TID (15)
/* OFFSET 0 */
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
/* OFFSET 4 */
#define PKT_OFFSET_SZ 0
#define QSEL_SHT 8
#define RATE_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define SEC_TYPE_SHT 22
#define PKT_OFFSET_SHT 26
/* OFFSET 8 */
#define AGG_EN BIT(12)
#define AGG_BK BIT(16)
#define AMPDU_DENSITY_SHT 20
#define ANTSEL_A BIT(24)
#define ANTSEL_B BIT(25)
#define TX_ANT_CCK_SHT 26
#define TX_ANTL_SHT 28
#define TX_ANT_HT_SHT 30
/* OFFSET 12 */
#define SEQ_SHT 16
#define EN_HWSEQ BIT(31)
/* OFFSET 16 */
#define QOS BIT(6)
#define HW_SSN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define CTS_2_SELF BIT(11)
#define RTS_EN BIT(12)
#define HW_RTS_EN BIT(13)
#define DATA_SHORT BIT(24)
#define PWR_STATUS_SHT 15
#define DATA_SC_SHT 20
#define DATA_BW BIT(25)
/* OFFSET 20 */
#define RTY_LMT_EN BIT(17)
/* OFFSET 20 */
#define SGI BIT(6)
#define USB_TXAGG_NUM_SHT 24
#define USB_TXAGG_DESC_NUM 0x6
#define txdesc_set_ccx_sw_88e(txdesc, value) \
do { \
((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
} while (0)
struct txrpt_ccx_88e {
/* offset 0 */
u8 tag1:1;
u8 pkt_num:3;
u8 txdma_underflow:1;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:6;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc,
u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *frame);
s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *frame);
s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
void rtl8188eu_xmit_tasklet(unsigned long priv);
bool rtl8188eu_xmitframe_complete(struct adapter *padapter);
#endif /* __RTL8188E_XMIT_H__ */

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drivers/staging/r8188eu/include/rtw_ap.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#ifndef __RTW_AP_H_
#define __RTW_AP_H_
#include "osdep_service.h"
#include "drv_types.h"
/* external function */
void rtw_indicate_sta_assoc_event(struct adapter *padapter,
struct sta_info *psta);
void init_mlme_ap_info(struct adapter *padapter);
void free_mlme_ap_info(struct adapter *padapter);
void update_beacon(struct adapter *padapter, u8 ie_id,
u8 *oui, u8 tx);
void add_RATid(struct adapter *padapter, struct sta_info *psta,
u8 rssi_level);
void expire_timeout_chk(struct adapter *padapter);
void update_sta_info_apmode(struct adapter *padapter, struct sta_info *psta);
void rtw_ap_restore_network(struct adapter *padapter);
void associated_clients_update(struct adapter *padapter, u8 updated);
void bss_cap_update_on_sta_join(struct adapter *padapter, struct sta_info *psta);
u8 bss_cap_update_on_sta_leave(struct adapter *padapter, struct sta_info *psta);
void sta_info_update(struct adapter *padapter, struct sta_info *psta);
u8 ap_free_sta(struct adapter *padapter, struct sta_info *psta,
bool active, u16 reason);
void rtw_sta_flush(struct adapter *padapter);
void start_ap_mode(struct adapter *padapter);
void stop_ap_mode(struct adapter *padapter);
void update_bmc_sta(struct adapter *padapter);
#endif

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drivers/staging/r8188eu/include/rtw_br_ext.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef _RTW_BR_EXT_H_
#define _RTW_BR_EXT_H_
#define GET_MY_HWADDR(padapter) ((padapter)->eeprompriv.mac_addr)
#define NAT25_HASH_BITS 4
#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS)
#define NAT25_AGEING_TIME 300
#define MAX_NETWORK_ADDR_LEN 17
struct nat25_network_db_entry {
struct nat25_network_db_entry *next_hash;
struct nat25_network_db_entry **pprev_hash;
atomic_t use_count;
unsigned char macAddr[6];
unsigned long ageing_timer;
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
};
enum NAT25_METHOD {
NAT25_MIN,
NAT25_CHECK,
NAT25_INSERT,
NAT25_PARSE,
NAT25_MAX
};
struct br_ext_info {
unsigned int nat25_disable;
unsigned int macclone_enable;
unsigned int dhcp_bcst_disable;
int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */
unsigned char nat25_dmzMac[ETH_ALEN];
unsigned int nat25sc_disable;
};
void nat25_db_cleanup(struct adapter *priv);
#endif /* _RTW_BR_EXT_H_ */

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drivers/staging/r8188eu/include/rtw_cmd.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_CMD_H_
#define __RTW_CMD_H_
#include "wlan_bssdef.h"
#include "rtw_rf.h"
#include "osdep_service.h"
#include "ieee80211.h" /* <ieee80211/ieee80211.h> */
#define MAX_CMDSZ 1024
#define MAX_RSPSZ 512
#define MAX_EVTSZ 1024
#define CMDBUFF_ALIGN_SZ 512
struct cmd_obj {
struct adapter *padapter;
u16 cmdcode;
u8 res;
u8 *parmbuf;
u32 cmdsz;
u8 *rsp;
u32 rspsz;
struct list_head list;
};
struct cmd_priv {
struct completion enqueue_cmd;
struct completion start_cmd_thread;
struct completion stop_cmd_thread;
struct __queue cmd_queue;
u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *cmd_allocated_buf;
u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *rsp_allocated_buf;
u32 cmd_done_cnt;
u32 rsp_cnt;
u8 cmdthd_running;
struct adapter *padapter;
};
struct evt_priv {
struct work_struct c2h_wk;
bool c2h_wk_alive;
struct rtw_cbuf *c2h_queue;
#define C2H_QUEUE_MAX_LEN 10
atomic_t event_seq;
u8 *evt_buf; /* shall be non-paged, and 4 bytes aligned */
};
#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \
do {\
INIT_LIST_HEAD(&pcmd->list);\
pcmd->cmdcode = code;\
pcmd->parmbuf = (u8 *)(pparm);\
pcmd->cmdsz = sizeof(*pparm);\
pcmd->rsp = NULL;\
pcmd->rspsz = 0;\
} while (0)
struct c2h_evt_hdr {
u8 id:4;
u8 plen:4;
u8 seq;
u8 payload[];
};
#define c2h_evt_exist(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen)
u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);
struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv);
void rtw_free_cmd_obj(struct cmd_obj *pcmd);
int rtw_cmd_thread(void *context);
int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv);
void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv);
int rtw_init_evt_priv(struct evt_priv *pevtpriv);
void rtw_free_evt_priv(struct evt_priv *pevtpriv);
void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
u8 p2p_protocol_wk_cmd(struct adapter *padapter, int intCmdType);
enum rtw_drvextra_cmd_id {
NONE_WK_CID,
DYNAMIC_CHK_WK_CID,
DM_CTRL_WK_CID,
PBC_POLLING_WK_CID,
POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */
LPS_CTRL_WK_CID,
ANT_SELECT_WK_CID,
P2P_PS_WK_CID,
P2P_PROTO_WK_CID,
CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */
INTEl_WIDI_WK_CID,
C2H_WK_CID,
RTP_TIMER_CFG_WK_CID,
MAX_WK_CID
};
enum LPS_CTRL_TYPE {
LPS_CTRL_SCAN = 0,
LPS_CTRL_JOINBSS = 1,
LPS_CTRL_CONNECT = 2,
LPS_CTRL_DISCONNECT = 3,
LPS_CTRL_SPECIAL_PACKET = 4,
LPS_CTRL_LEAVE = 5,
};
enum RFINTFS {
SWSI,
HWSI,
HWPI,
};
/*
Caller Mode: Infra, Ad-HoC
Notes: To join a known BSS.
Command-Event Mode
*/
/*
Caller Mode: Infra, Ad-Hoc
Notes: To join the specified bss
Command Event Mode
*/
struct joinbss_parm {
struct wlan_bssid_ex network;
};
/*
Caller Mode: Infra, Ad-HoC(C)
Notes: To disconnect the current associated BSS
Command Mode
*/
struct disconnect_parm {
u32 deauth_timeout_ms;
};
/*
Caller Mode: AP, Ad-HoC(M)
Notes: To create a BSS
Command Mode
*/
struct createbss_parm {
struct wlan_bssid_ex network;
};
struct setopmode_parm {
u8 mode;
u8 rsvd[3];
};
/*
Caller Mode: AP, Ad-HoC, Infra
Notes: To ask RTL8711 performing site-survey
Command-Event Mode
*/
#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */
#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
struct sitesurvey_parm {
int scan_mode; /* active: 1, passive: 0 */
u8 ssid_num;
u8 ch_num;
struct ndis_802_11_ssid ssid[RTW_SSID_SCAN_AMOUNT];
struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
};
/*
Caller Mode: Any
Notes: To set the auth type of RTL8711. open/shared/802.1x
Command Mode
*/
struct setauth_parm {
u8 mode; /* 0: legacy open, 1: legacy shared 2: 802.1x */
u8 _1x; /* 0: PSK, 1: TLS */
u8 rsvd[2];
};
/*
Caller Mode: Infra
a. algorithm: wep40, wep104, tkip & aes
b. keytype: grp key/unicast key
c. key contents
when shared key ==> keyid is the camid
when 802.1x ==> keyid [0:1] ==> grp key
when 802.1x ==> keyid > 2 ==> unicast key
*/
struct setkey_parm {
u8 algorithm; /* could be none, wep40, TKIP, CCMP, wep104 */
u8 keyid;
u8 grpkey; /* 1: this is the grpkey for 802.1x.
* 0: this is the unicast key for 802.1x */
u8 set_tx; /* 1: main tx key for wep. 0: other key. */
u8 key[16]; /* this could be 40 or 104 */
};
/*
When in AP or Ad-Hoc mode, this is used to
allocate an sw/hw entry for a newly associated sta.
Command
when shared key ==> algorithm/keyid
*/
struct set_stakey_parm {
u8 addr[ETH_ALEN];
u8 algorithm;
u8 id;/* currently for erasing cam entry if
* algorithm == _NO_PRIVACY_ */
u8 key[16];
};
struct set_stakey_rsp {
u8 addr[ETH_ALEN];
u8 keyid;
u8 rsvd;
};
/*
Caller Ad-Hoc/AP
Command -Rsp(AID == CAMID) mode
This is to force fw to add an sta_data entry per driver's request.
FW will write an cam entry associated with it.
*/
struct set_assocsta_parm {
u8 addr[ETH_ALEN];
};
struct set_assocsta_rsp {
u8 cam_id;
u8 rsvd[3];
};
/*
Caller Ad-Hoc/AP
Command mode
This is to force fw to del an sta_data entry per driver's request
FW will invalidate the cam entry associated with it.
*/
struct del_assocsta_parm {
u8 addr[ETH_ALEN];
};
/*
Caller Mode: AP/Ad-HoC(M)
Notes: To notify fw that given staid has changed its power state
Command Mode
*/
struct setstapwrstate_parm {
u8 staid;
u8 status;
u8 hwaddr[6];
};
/*
Caller Mode: Any
Notes: To setup the basic rate of RTL8711
Command Mode
*/
struct setbasicrate_parm {
u8 basicrates[NumRates];
};
/*
Caller Mode: Any
Notes: To read the current basic rate
Command-Rsp Mode
*/
struct getbasicrate_parm {
u32 rsvd;
};
struct getbasicrate_rsp {
u8 basicrates[NumRates];
};
/*
Caller Mode: Any
Notes: To setup the data rate of RTL8711
Command Mode
*/
struct setdatarate_parm {
u8 mac_id;
u8 datarates[NumRates];
};
/*
Caller Mode: Any
Notes: To read the current data rate
Command-Rsp Mode
*/
struct getdatarate_parm {
u32 rsvd;
};
struct getdatarate_rsp {
u8 datarates[NumRates];
};
/*
Caller Mode: Any
AP: AP can use the info for the contents of beacon frame
Infra: STA can use the info when sitesurveying
Ad-HoC(M): Like AP
Ad-HoC(C): Like STA
Notes: To set the phy capability of the NIC
Command Mode
*/
struct setphyinfo_parm {
struct regulatory_class class_sets[NUM_REGULATORYS];
u8 status;
};
struct getphyinfo_parm {
u32 rsvd;
};
struct getphyinfo_rsp {
struct regulatory_class class_sets[NUM_REGULATORYS];
u8 status;
};
/*
Caller Mode: Any
Notes: To set the channel/modem/band
This command will be used when channel/modem/band is changed.
Command Mode
*/
struct setphy_parm {
u8 rfchannel;
u8 modem;
};
/*
Caller Mode: Any
Notes: To get the current setting of channel/modem/band
Command-Rsp Mode
*/
struct getphy_parm {
u32 rsvd;
};
struct getphy_rsp {
u8 rfchannel;
u8 modem;
};
struct readBB_parm {
u8 offset;
};
struct readBB_rsp {
u8 value;
};
struct readTSSI_parm {
u8 offset;
};
struct readTSSI_rsp {
u8 value;
};
struct writeBB_parm {
u8 offset;
u8 value;
};
struct readRF_parm {
u8 offset;
};
struct readRF_rsp {
u32 value;
};
struct writeRF_parm {
u32 offset;
u32 value;
};
struct getrfintfs_parm {
u8 rfintfs;
};
struct Tx_Beacon_param {
struct wlan_bssid_ex network;
};
/*
Notes: This command is used for H2C/C2H loopback testing
mac[0] == 0
==> CMD mode, return H2C_SUCCESS.
The following condition must be true under CMD mode
mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;
s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;
s2 == (b1 << 8 | b0);
mac[0] == 1
==> CMD_RSP mode, return H2C_SUCCESS_RSP
The rsp layout shall be:
rsp: parm:
mac[0] = mac[5];
mac[1] = mac[4];
mac[2] = mac[3];
mac[3] = mac[2];
mac[4] = mac[1];
mac[5] = mac[0];
s0 = s1;
s1 = swap16(s0);
w0 = swap32(w1);
b0 = b1
s2 = s0 + s1
b1 = b0
w1 = w0
mac[0] == 2
==> CMD_EVENT mode, return H2C_SUCCESS
The event layout shall be:
event: parm:
mac[0] = mac[5];
mac[1] = mac[4];
mac[2] = event's seq no, starting from 1 to parm's marc[3]
mac[3] = mac[2];
mac[4] = mac[1];
mac[5] = mac[0];
s0 = swap16(s0) - event.mac[2];
s1 = s1 + event.mac[2];
w0 = swap32(w0);
b0 = b1
s2 = s0 + event.mac[2]
b1 = b0
w1 = swap32(w1) - event.mac[2];
parm->mac[3] is the total event counts that host requested.
event will be the same with the cmd's param.
*/
/* CMD param Format for driver extra cmd handler */
struct drvextra_cmd_parm {
int ec_id; /* extra cmd id */
int type_size; /* Can use this field as the type id or command size */
unsigned char *pbuf;
};
/*------------------- Below are used for RF/BB tuning ---------------------*/
struct setantenna_parm {
u8 tx_antset;
u8 rx_antset;
u8 tx_antenna;
u8 rx_antenna;
};
struct enrateadaptive_parm {
u32 en;
};
struct settxagctbl_parm {
u32 txagc[MAX_RATES_LENGTH];
};
struct gettxagctbl_parm {
u32 rsvd;
};
struct gettxagctbl_rsp {
u32 txagc[MAX_RATES_LENGTH];
};
struct setagcctrl_parm {
u32 agcctrl; /* 0: pure hw, 1: fw */
};
struct setssup_parm {
u32 ss_ForceUp[MAX_RATES_LENGTH];
};
struct getssup_parm {
u32 rsvd;
};
struct getssup_rsp {
u8 ss_ForceUp[MAX_RATES_LENGTH];
};
struct setssdlevel_parm {
u8 ss_DLevel[MAX_RATES_LENGTH];
};
struct getssdlevel_parm {
u32 rsvd;
};
struct getssdlevel_rsp {
u8 ss_DLevel[MAX_RATES_LENGTH];
};
struct setssulevel_parm {
u8 ss_ULevel[MAX_RATES_LENGTH];
};
struct getssulevel_parm {
u32 rsvd;
};
struct getssulevel_rsp {
u8 ss_ULevel[MAX_RATES_LENGTH];
};
struct setcountjudge_parm {
u8 count_judge[MAX_RATES_LENGTH];
};
struct getcountjudge_parm {
u32 rsvd;
};
struct getcountjudge_rsp {
u8 count_judge[MAX_RATES_LENGTH];
};
struct setratable_parm {
u8 ss_ForceUp[NumRates];
u8 ss_ULevel[NumRates];
u8 ss_DLevel[NumRates];
u8 count_judge[NumRates];
};
struct getratable_parm {
uint rsvd;
};
struct getratable_rsp {
u8 ss_ForceUp[NumRates];
u8 ss_ULevel[NumRates];
u8 ss_DLevel[NumRates];
u8 count_judge[NumRates];
};
/* to get TX,RX retry count */
struct gettxretrycnt_parm {
unsigned int rsvd;
};
struct gettxretrycnt_rsp {
unsigned long tx_retrycnt;
};
struct getrxretrycnt_parm {
unsigned int rsvd;
};
struct getrxretrycnt_rsp {
unsigned long rx_retrycnt;
};
/* to get BCNOK,BCNERR count */
struct getbcnokcnt_parm {
unsigned int rsvd;
};
struct getbcnokcnt_rsp {
unsigned long bcnokcnt;
};
struct getbcnerrcnt_parm {
unsigned int rsvd;
};
struct getbcnerrcnt_rsp {
unsigned long bcnerrcnt;
};
/* to get current TX power level */
struct getcurtxpwrlevel_parm {
unsigned int rsvd;
};
struct getcurtxpwrlevel_rspi {
unsigned short tx_power;
};
struct setprobereqextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[];
};
struct setassocreqextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[];
};
struct setproberspextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[];
};
struct setassocrspextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[];
};
struct addBaReq_parm {
unsigned int tid;
u8 addr[ETH_ALEN];
};
/*H2C Handler index: 46 */
struct set_ch_parm {
u8 ch;
u8 bw;
u8 ch_offset;
};
/*H2C Handler index: 59 */
struct SetChannelPlan_param {
u8 channel_plan;
};
/*H2C Handler index: 60 */
struct LedBlink_param {
struct LED_871x *pLed;
};
/*H2C Handler index: 61 */
struct SetChannelSwitch_param {
u8 new_ch_no;
};
/*H2C Handler index: 62 */
struct TDLSoption_param {
u8 addr[ETH_ALEN];
u8 option;
};
#define GEN_CMD_CODE(cmd) cmd ## _CMD_
/*
Result:
0x00: success
0x01: success, and check Response.
0x02: cmd ignored due to duplicated sequcne number
0x03: cmd dropped due to invalid cmd code
0x04: reserved.
*/
#define H2C_RSP_OFFSET 512
#define H2C_SUCCESS 0x00
#define H2C_SUCCESS_RSP 0x01
#define H2C_DUPLICATED 0x02
#define H2C_DROPPED 0x03
#define H2C_PARAMETERS_ERROR 0x04
#define H2C_REJECTED 0x05
#define H2C_CMD_OVERFLOW 0x06
#define H2C_RESERVED 0x07
u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, int ssid_num);
u8 rtw_createbss_cmd(struct adapter *padapter);
u8 rtw_setstakey_cmd(struct adapter *padapter, u8 *psta, u8 unicast_key);
u8 rtw_clearstakey_cmd(struct adapter *padapter, u8 *psta, u8 entry, u8 enqueue);
u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork);
u8 rtw_disassoc_cmd(struct adapter *padapter, u32 deauth_timeout_ms, bool enqueue);
u8 rtw_setopmode_cmd(struct adapter *padapter, enum ndis_802_11_network_infra networktype);
int rtw_setdatarate_cmd(struct adapter *padapter, u8 *rateset);
u8 rtw_setrfintfs_cmd(struct adapter *padapter, u8 mode);
u8 rtw_gettssi_cmd(struct adapter *padapter, u8 offset, u8 *pval);
u8 rtw_setfwdig_cmd(struct adapter *padapter, u8 type);
u8 rtw_setfwra_cmd(struct adapter *padapter, u8 type);
u8 rtw_addbareq_cmd(struct adapter *padapter, u8 tid, u8 *addr);
u8 rtw_dynamic_chk_wk_cmd(struct adapter *adapter);
u8 rtw_lps_ctrl_wk_cmd(struct adapter *padapter, u8 lps_ctrl_type, u8 enqueue);
u8 rtw_rpt_timer_cfg_cmd(struct adapter *padapter, u16 minRptTime);
u8 rtw_antenna_select_cmd(struct adapter *padapter, u8 antenna, u8 enqueue);
u8 rtw_ps_cmd(struct adapter *padapter);
void rtw_chk_hi_queue_cmd(struct adapter *padapter);
u8 rtw_set_chplan_cmd(struct adapter *padapter, u8 chplan);
u8 rtw_c2h_wk_cmd(struct adapter *padapter, u8 *c2h_evt);
u8 rtw_drvextra_cmd_hdl(struct adapter *padapter, unsigned char *pbuf);
void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
void rtw_disassoc_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
void rtw_createbss_cmd_callback(struct adapter *adapt, struct cmd_obj *pcmd);
void rtw_getbbrfreg_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd);
void rtw_setstaKey_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd);
void rtw_setassocsta_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cm);
void rtw_getrttbl_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd);
struct _cmd_callback {
u32 cmd_code;
void (*callback)(struct adapter *padapter, struct cmd_obj *cmd);
};
enum rtw_h2c_cmd {
GEN_CMD_CODE(_Read_MACREG), /*0*/
GEN_CMD_CODE(_Write_MACREG),
GEN_CMD_CODE(_Read_BBREG),
GEN_CMD_CODE(_Write_BBREG),
GEN_CMD_CODE(_Read_RFREG),
GEN_CMD_CODE(_Write_RFREG), /*5*/
GEN_CMD_CODE(_Read_EEPROM),
GEN_CMD_CODE(_Write_EEPROM),
GEN_CMD_CODE(_Read_EFUSE),
GEN_CMD_CODE(_Write_EFUSE),
GEN_CMD_CODE(_Read_CAM), /*10*/
GEN_CMD_CODE(_Write_CAM),
GEN_CMD_CODE(_setBCNITV),
GEN_CMD_CODE(_setMBIDCFG),
GEN_CMD_CODE(_JoinBss), /*14*/
GEN_CMD_CODE(_DisConnect), /*15*/
GEN_CMD_CODE(_CreateBss),
GEN_CMD_CODE(_SetOpMode),
GEN_CMD_CODE(_SiteSurvey), /*18*/
GEN_CMD_CODE(_SetAuth),
GEN_CMD_CODE(_SetKey), /*20*/
GEN_CMD_CODE(_SetStaKey),
GEN_CMD_CODE(_SetAssocSta),
GEN_CMD_CODE(_DelAssocSta),
GEN_CMD_CODE(_SetStaPwrState),
GEN_CMD_CODE(_SetBasicRate), /*25*/
GEN_CMD_CODE(_GetBasicRate),
GEN_CMD_CODE(_SetDataRate),
GEN_CMD_CODE(_GetDataRate),
GEN_CMD_CODE(_SetPhyInfo),
GEN_CMD_CODE(_GetPhyInfo), /*30*/
GEN_CMD_CODE(_SetPhy),
GEN_CMD_CODE(_GetPhy),
GEN_CMD_CODE(_readRssi),
GEN_CMD_CODE(_readGain),
GEN_CMD_CODE(_SetAtim), /*35*/
GEN_CMD_CODE(_SetPwrMode),
GEN_CMD_CODE(_JoinbssRpt),
GEN_CMD_CODE(_SetRaTable),
GEN_CMD_CODE(_GetRaTable),
GEN_CMD_CODE(_GetCCXReport), /*40*/
GEN_CMD_CODE(_GetDTMReport),
GEN_CMD_CODE(_GetTXRateStatistics),
GEN_CMD_CODE(_SetUsbSuspend),
GEN_CMD_CODE(_SetH2cLbk),
GEN_CMD_CODE(_AddBAReq), /*45*/
GEN_CMD_CODE(_SetChannel), /*46*/
GEN_CMD_CODE(_SetTxPower),
GEN_CMD_CODE(_SwitchAntenna),
GEN_CMD_CODE(_SetCrystalCap),
GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/
GEN_CMD_CODE(_SetSingleToneTx),/*51*/
GEN_CMD_CODE(_SetCarrierSuppressionTx),
GEN_CMD_CODE(_SetContinuousTx),
GEN_CMD_CODE(_SwitchBandwidth), /*54*/
GEN_CMD_CODE(_TX_Beacon), /*55*/
GEN_CMD_CODE(_Set_MLME_EVT), /*56*/
GEN_CMD_CODE(_Set_Drv_Extra), /*57*/
GEN_CMD_CODE(_Set_H2C_MSG), /*58*/
GEN_CMD_CODE(_SetChannelPlan), /*59*/
GEN_CMD_CODE(_LedBlink), /*60*/
GEN_CMD_CODE(_SetChannelSwitch), /*61*/
GEN_CMD_CODE(_TDLS), /*62*/
MAX_H2CCMD
};
#define _GetBBReg_CMD_ _Read_BBREG_CMD_
#define _SetBBReg_CMD_ _Write_BBREG_CMD_
#define _GetRFReg_CMD_ _Read_RFREG_CMD_
#define _SetRFReg_CMD_ _Write_RFREG_CMD_
#ifdef _RTW_CMD_C_
static struct _cmd_callback rtw_cmd_callback[] = {
{GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/
{GEN_CMD_CODE(_Write_MACREG), NULL},
{GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback},
{GEN_CMD_CODE(_Write_BBREG), NULL},
{GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback},
{GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/
{GEN_CMD_CODE(_Read_EEPROM), NULL},
{GEN_CMD_CODE(_Write_EEPROM), NULL},
{GEN_CMD_CODE(_Read_EFUSE), NULL},
{GEN_CMD_CODE(_Write_EFUSE), NULL},
{GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/
{GEN_CMD_CODE(_Write_CAM), NULL},
{GEN_CMD_CODE(_setBCNITV), NULL},
{GEN_CMD_CODE(_setMBIDCFG), NULL},
{GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/
{GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/
{GEN_CMD_CODE(_CreateBss), &rtw_createbss_cmd_callback},
{GEN_CMD_CODE(_SetOpMode), NULL},
{GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/
{GEN_CMD_CODE(_SetAuth), NULL},
{GEN_CMD_CODE(_SetKey), NULL}, /*20*/
{GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback},
{GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback},
{GEN_CMD_CODE(_DelAssocSta), NULL},
{GEN_CMD_CODE(_SetStaPwrState), NULL},
{GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/
{GEN_CMD_CODE(_GetBasicRate), NULL},
{GEN_CMD_CODE(_SetDataRate), NULL},
{GEN_CMD_CODE(_GetDataRate), NULL},
{GEN_CMD_CODE(_SetPhyInfo), NULL},
{GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/
{GEN_CMD_CODE(_SetPhy), NULL},
{GEN_CMD_CODE(_GetPhy), NULL},
{GEN_CMD_CODE(_readRssi), NULL},
{GEN_CMD_CODE(_readGain), NULL},
{GEN_CMD_CODE(_SetAtim), NULL}, /*35*/
{GEN_CMD_CODE(_SetPwrMode), NULL},
{GEN_CMD_CODE(_JoinbssRpt), NULL},
{GEN_CMD_CODE(_SetRaTable), NULL},
{GEN_CMD_CODE(_GetRaTable), NULL},
{GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/
{GEN_CMD_CODE(_GetDTMReport), NULL},
{GEN_CMD_CODE(_GetTXRateStatistics), NULL},
{GEN_CMD_CODE(_SetUsbSuspend), NULL},
{GEN_CMD_CODE(_SetH2cLbk), NULL},
{GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/
{GEN_CMD_CODE(_SetChannel), NULL}, /*46*/
{GEN_CMD_CODE(_SetTxPower), NULL},
{GEN_CMD_CODE(_SwitchAntenna), NULL},
{GEN_CMD_CODE(_SetCrystalCap), NULL},
{GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/
{GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/
{GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL},
{GEN_CMD_CODE(_SetContinuousTx), NULL},
{GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/
{GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/
{GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/
{GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/
{GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/
{GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/
{GEN_CMD_CODE(_LedBlink), NULL},/*60*/
{GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/
{GEN_CMD_CODE(_TDLS), NULL},/*62*/
};
#endif
#endif /* _CMD_H_ */

15
drivers/staging/r8188eu/include/rtw_eeprom.h
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@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_EEPROM_H__
#define __RTW_EEPROM_H__
#include "osdep_service.h"
#include "drv_types.h"
struct eeprom_priv {
u8 bautoload_fail_flag;
u8 mac_addr[ETH_ALEN] __aligned(2); /* PermanentAddress */
};
#endif /* __RTL871X_EEPROM_H__ */

11
drivers/staging/r8188eu/include/rtw_efuse.h
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_EFUSE_H__
#define __RTW_EFUSE_H__
#define EFUSE_MAX_WORD_UNIT 4
void ReadEFuseByte(struct adapter *adapter, u16 _offset, u8 *pbuf);
#endif

97
drivers/staging/r8188eu/include/rtw_event.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef _RTW_EVENT_H_
#define _RTW_EVENT_H_
#include "osdep_service.h"
#include "wlan_bssdef.h"
#include <linux/semaphore.h>
#include <linux/sem.h>
/*
Used to report a bss has been scanned
*/
struct survey_event {
struct wlan_bssid_ex bss;
};
/*
Used to report that the requested site survey has been done.
bss_cnt indicates the number of bss that has been reported.
*/
struct surveydone_event {
unsigned int bss_cnt;
};
/*
Used to report the link result of joinning the given bss
join_res:
-1: authentication fail
-2: association fail
> 0: TID
*/
struct joinbss_event {
struct wlan_network network;
};
/*
Used to report a given STA has joinned the created BSS.
It is used in AP/Ad-HoC(M) mode.
*/
struct stassoc_event {
unsigned char macaddr[6];
unsigned char rsvd[2];
int cam_id;
};
struct stadel_event {
unsigned char macaddr[6];
unsigned char rsvd[2]; /* for reason */
int mac_id;
};
struct addba_event {
unsigned int tid;
};
#define GEN_EVT_CODE(event) event ## _EVT_
struct fwevent {
u32 parmsize;
void (*event_callback)(struct adapter *dev, u8 *pbuf);
};
#define C2HEVENT_SZ 32
struct event_node {
unsigned char *node;
unsigned char evt_code;
unsigned short evt_sz;
int *caller_ff_tail;
int caller_ff_sz;
};
struct c2hevent_queue {
int head;
int tail;
struct event_node nodes[C2HEVENT_SZ];
unsigned char seq;
};
#define NETWORK_QUEUE_SZ 4
struct network_queue {
int head;
int tail;
struct wlan_bssid_ex networks[NETWORK_QUEUE_SZ];
};
#endif /* _WLANEVENT_H_ */

17
drivers/staging/r8188eu/include/rtw_fw.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_FW_H__
#define __RTW_FW_H__
struct rt_firmware {
u8 *data;
u32 size;
};
#include "drv_types.h"
int rtl8188e_firmware_download(struct adapter *padapter);
void rtw_reset_8051(struct adapter *padapter);
#endif

28
drivers/staging/r8188eu/include/rtw_ht.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef _RTW_HT_H_
#define _RTW_HT_H_
#include "osdep_service.h"
#include "wifi.h"
struct ht_priv {
u32 ht_option;
u32 ampdu_enable;/* for enable Tx A-MPDU */
u32 tx_amsdu_enable;/* for enable Tx A-MSDU */
u32 tx_amdsu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
u32 rx_ampdu_maxlen; /* for rx reordering ctrl win_sz,
* updated when join_callback. */
u8 bwmode;/* */
u8 ch_offset;/* PRIME_CHNL_OFFSET */
u8 sgi;/* short GI */
/* for processing Tx A-MPDU */
u8 agg_enable_bitmap;
u8 candidate_tid_bitmap;
struct ieee80211_ht_cap ht_cap;
};
#endif /* _RTL871X_HT_H_ */

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drivers/staging/r8188eu/include/rtw_io.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef _RTW_IO_H_
#define _RTW_IO_H_
#include "osdep_service.h"
#include "osdep_intf.h"
#include <asm/byteorder.h>
#include <linux/semaphore.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <asm/atomic.h>
#include <linux/usb.h>
#include <linux/usb/ch9.h>
int __must_check rtw_read8(struct adapter *adapter, u32 addr, u8 *data);
int __must_check rtw_read16(struct adapter *adapter, u32 addr, u16 *data);
int __must_check rtw_read32(struct adapter *adapter, u32 addr, u32 *data);
int rtw_read_port(struct adapter *adapter, struct recv_buf *precvbuf);
void rtw_read_port_cancel(struct adapter *adapter);
int rtw_write8(struct adapter *adapter, u32 addr, u8 val);
int rtw_write16(struct adapter *adapter, u32 addr, u16 val);
int rtw_write32(struct adapter *adapter, u32 addr, u32 val);
int rtw_writeN(struct adapter *adapter, u32 addr, u32 length, u8 *pdata);
u32 rtw_write_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
void rtw_write_port_cancel(struct adapter *adapter);
#endif /* _RTL8711_IO_H_ */

13
drivers/staging/r8188eu/include/rtw_ioctl.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef _RTW_IOCTL_H_
#define _RTW_IOCTL_H_
#include "osdep_service.h"
#include "drv_types.h"
extern struct iw_handler_def rtw_handlers_def;
extern int ui_pid[3];
#endif /* #ifndef __INC_CEINFO_ */

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drivers/staging/r8188eu/include/rtw_ioctl_set.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_IOCTL_SET_H_
#define __RTW_IOCTL_SET_H_
#include "drv_types.h"
typedef u8 NDIS_802_11_PMKID_VALUE[16];
u8 rtw_set_802_11_authentication_mode(struct adapter *adapt,
enum ndis_802_11_auth_mode authmode);
u8 rtw_set_802_11_bssid(struct adapter *adapter, u8 *bssid);
u8 rtw_set_802_11_add_wep(struct adapter *adapter, struct ndis_802_11_wep *wep);
void rtw_set_802_11_disassociate(struct adapter *adapter);
u8 rtw_set_802_11_bssid_list_scan(struct adapter *adapter,
struct ndis_802_11_ssid *pssid,
int ssid_max_num);
u8 rtw_set_802_11_infrastructure_mode(struct adapter *adapter,
enum ndis_802_11_network_infra type);
u8 rtw_set_802_11_ssid(struct adapter *adapt, struct ndis_802_11_ssid *ssid);
u16 rtw_get_cur_max_rate(struct adapter *adapter);
int rtw_change_ifname(struct adapter *padapter, const char *ifname);
#endif

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drivers/staging/r8188eu/include/rtw_iol.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_IOL_H_
#define __RTW_IOL_H_
#include "osdep_service.h"
#include "drv_types.h"
#define IOREG_CMD_END_LEN 4
struct ioreg_cfg {
u8 length;
u8 cmd_id;
__le16 address;
__le32 data;
__le32 mask;
};
enum ioreg_cmd {
IOREG_CMD_LLT = 0x01,
IOREG_CMD_REFUSE = 0x02,
IOREG_CMD_EFUSE_PATH = 0x03,
IOREG_CMD_WB_REG = 0x04,
IOREG_CMD_WW_REG = 0x05,
IOREG_CMD_WD_REG = 0x06,
IOREG_CMD_W_RF = 0x07,
IOREG_CMD_DELAY_US = 0x10,
IOREG_CMD_DELAY_MS = 0x11,
IOREG_CMD_END = 0xFF,
};
struct xmit_frame *rtw_IOL_accquire_xmit_frame(struct adapter *adapter);
int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds,
u32 cmd_len);
bool rtw_IOL_applied(struct adapter *adapter);
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
void read_efuse_from_txpktbuf(struct adapter *adapter, int bcnhead,
u8 *content, u16 *size);
int rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr,
u8 value, u8 mask);
int rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr,
u16 value, u16 mask);
int rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr,
u32 value, u32 mask);
int rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path,
u16 addr, u32 value, u32 mask);
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
#endif /* __RTW_IOL_H_ */

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drivers/staging/r8188eu/include/rtw_led.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_LED_H_
#define __RTW_LED_H_
#include "osdep_service.h"
#include "drv_types.h"
enum LED_CTL_MODE {
LED_CTL_LINK = 2,
LED_CTL_NO_LINK = 3,
LED_CTL_TX = 4,
LED_CTL_RX = 5,
LED_CTL_SITE_SURVEY = 6,
LED_CTL_POWER_OFF = 7,
LED_CTL_START_TO_LINK = 8,
LED_CTL_START_WPS = 9,
LED_CTL_STOP_WPS = 10,
LED_CTL_STOP_WPS_FAIL = 12,
};
enum LED_STATE_871x {
RTW_LED_OFF = 2,
LED_BLINK_NORMAL = 3,
LED_BLINK_SLOWLY = 4,
LED_BLINK_SCAN = 6, /* LED is blinking during scanning period,
* the # of times to blink is depend on time
* for scanning. */
LED_BLINK_TXRX = 9,
LED_BLINK_WPS = 10, /* LED is blinkg during WPS communication */
LED_BLINK_WPS_STOP = 11,
};
struct led_priv {
bool bRegUseLed;
enum LED_STATE_871x CurrLedState; /* Current LED state. */
bool bLedOn; /* true if LED is ON, false if LED is OFF. */
bool bLedBlinkInProgress; /* true if it is blinking, false o.w.. */
bool bLedWPSBlinkInProgress;
u32 BlinkTimes; /* Number of times to toggle led state for blinking. */
bool bLedScanBlinkInProgress;
struct delayed_work blink_work;
};
void rtl8188eu_InitSwLeds(struct adapter *padapter);
void rtl8188eu_DeInitSwLeds(struct adapter *padapter);
void rtw_led_control(struct adapter *padapter, enum LED_CTL_MODE LedAction);
#endif /* __RTW_LED_H_ */

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drivers/staging/r8188eu/include/rtw_mlme.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_MLME_H_
#define __RTW_MLME_H_
#include "osdep_service.h"
#include "drv_types.h"
#include "wlan_bssdef.h"
#define MAX_BSS_CNT 128
#define MAX_JOIN_TIMEOUT 6500
/* Increase the scanning timeout because of increasing the SURVEY_TO value. */
#define SCANNING_TIMEOUT 8000
#define SCAN_INTERVAL (30) /* unit:2sec, 30*2=60sec */
#define SCANQUEUE_LIFETIME 20 /* unit:sec */
#define WIFI_NULL_STATE 0x00000000
#define WIFI_ASOC_STATE 0x00000001 /* Under Linked state */
#define WIFI_REASOC_STATE 0x00000002
#define WIFI_SLEEP_STATE 0x00000004
#define WIFI_STATION_STATE 0x00000008
#define WIFI_AP_STATE 0x00000010
#define WIFI_ADHOC_STATE 0x00000020
#define WIFI_ADHOC_MASTER_STATE 0x00000040
#define WIFI_UNDER_LINKING 0x00000080
#define WIFI_UNDER_WPS 0x00000100
#define WIFI_STA_ALIVE_CHK_STATE 0x00000400
#define WIFI_SITE_MONITOR 0x00000800 /* to indicate the station is under site surveying */
#define WIFI_MP_STATE 0x00010000
#define WIFI_MP_CTX_BACKGROUND 0x00020000 /* in continuous tx background */
#define WIFI_MP_CTX_ST 0x00040000 /* in continuous tx with single-tone */
#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 /* pending in continuous tx background due to out of skb */
#define WIFI_MP_CTX_CCK_HW 0x00100000 /* in continuous tx */
#define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continuous tx with carrier suppression */
#define WIFI_MP_LPBK_STATE 0x00400000
#define _FW_UNDER_LINKING WIFI_UNDER_LINKING
#define _FW_LINKED WIFI_ASOC_STATE
#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR
enum dot11AuthAlgrthmNum {
dot11AuthAlgrthm_Open = 0,
dot11AuthAlgrthm_Shared,
dot11AuthAlgrthm_8021X,
dot11AuthAlgrthm_Auto,
dot11AuthAlgrthm_WAPI,
dot11AuthAlgrthm_MaxNum
};
/* Scan type including active and passive scan. */
enum rt_scan_type {
SCAN_PASSIVE,
SCAN_ACTIVE,
SCAN_MIX,
};
/*
there are several "locks" in mlme_priv,
since mlme_priv is a shared resource between many threads,
like ISR/Call-Back functions, the OID handlers, and even timer functions.
Each _queue has its own locks, already.
Other items are protected by mlme_priv.lock.
To avoid possible dead lock, any thread trying to modifiying mlme_priv
SHALL not lock up more than one lock at a time!
*/
#define traffic_threshold 10
#define traffic_scan_period 500
struct sitesurvey_ctrl {
u64 last_tx_pkts;
uint last_rx_pkts;
int traffic_busy;
struct timer_list sitesurvey_ctrl_timer;
};
struct rt_link_detect {
u32 NumTxOkInPeriod;
u32 NumRxOkInPeriod;
u32 NumRxUnicastOkInPeriod;
bool bBusyTraffic;
bool bTxBusyTraffic;
bool bRxBusyTraffic;
bool bHigherBusyTraffic; /* For interrupt migration purpose. */
bool bHigherBusyRxTraffic; /* We may disable Tx interrupt according
* to Rx traffic. */
bool bHigherBusyTxTraffic; /* We may disable Tx interrupt according
* to Tx traffic. */
};
struct profile_info {
u8 ssidlen;
u8 ssid[WLAN_SSID_MAXLEN];
u8 peermac[ETH_ALEN];
};
struct tx_invite_req_info {
u8 token;
u8 benable;
u8 go_ssid[WLAN_SSID_MAXLEN];
u8 ssidlen;
u8 go_bssid[ETH_ALEN];
u8 peer_macaddr[ETH_ALEN];
u8 operating_ch; /* This information will be set by using the
* p2p_set op_ch=x */
u8 peer_ch; /* The listen channel for peer P2P device */
};
struct tx_invite_resp_info {
u8 token; /* Used to record the dialog token of p2p invitation
* request frame. */
};
struct tx_provdisc_req_info {
u16 wps_config_method_request; /* Used when sending the
* provisioning request frame*/
u16 peer_channel_num[2]; /* The channel number which the
* receiver stands. */
struct ndis_802_11_ssid ssid;
u8 peerDevAddr[ETH_ALEN]; /* Peer device address */
u8 peerIFAddr[ETH_ALEN]; /* Peer interface address */
u8 benable; /* This provision discovery
* request frame is trigger
* to send or not */
};
/* When peer device issue prov_disc_req first, we should store the following
* information */
/* The UI must know this information to know which config method the
* remote p2p device needs. */
struct rx_provdisc_req_info {
u8 peerDevAddr[ETH_ALEN]; /* Peer device address */
u8 strconfig_method_desc_of_prov_disc_req[4]; /* description
* for the config method located in the provisioning
* discovery request frame. */
};
struct tx_nego_req_info {
u16 peer_channel_num[2]; /* The channel number. */
u8 peerDevAddr[ETH_ALEN]; /* Peer device address */
u8 benable; /* This negotiation request frame is
* trigger to send or not */
};
struct group_id_info {
u8 go_device_addr[ETH_ALEN]; /* The GO's device address of
* this P2P group */
u8 ssid[WLAN_SSID_MAXLEN]; /* The SSID of this P2P group */
};
struct scan_limit_info {
u8 scan_op_ch_only; /* When this flag is set, the driver
* should only scan the op. channel */
u8 operation_ch[2]; /* Store the op. chan of invitation */
};
struct wifidirect_info {
struct adapter *padapter;
struct timer_list find_phase_timer;
struct timer_list restore_p2p_state_timer;
/* Used to do the scanning. After confirming the peer is availalble,
* the driver transmits the P2P frame to peer. */
struct timer_list pre_tx_scan_timer;
struct timer_list reset_ch_sitesurvey;
struct timer_list reset_ch_sitesurvey2; /* Just for resetting the scan
* limit function by using p2p nego */
struct tx_provdisc_req_info tx_prov_disc_info;
struct rx_provdisc_req_info rx_prov_disc_info;
struct tx_invite_req_info invitereq_info;
/* Store the profile information of persistent group */
struct profile_info profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM];
struct tx_invite_resp_info inviteresp_info;
struct tx_nego_req_info nego_req_info;
/* Store the group id info when doing the group negot handshake. */
struct group_id_info groupid_info;
/* Used for get the limit scan channel from the Invitation procedure */
struct scan_limit_info rx_invitereq_info;
/* Used for get the limit scan chan from the P2P negotiation handshake*/
struct scan_limit_info p2p_info;
enum P2P_ROLE role;
enum P2P_STATE pre_p2p_state;
enum P2P_STATE p2p_state;
/* The device address should be the mac address of this device. */
u8 device_addr[ETH_ALEN];
u8 interface_addr[ETH_ALEN];
u8 social_chan[4];
u8 listen_channel;
u8 operating_channel;
u8 listen_dwell; /* This value should be between 1 and 3 */
u8 support_rate[8];
u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
u8 intent; /* should only include the intent value. */
u8 p2p_peer_interface_addr[ETH_ALEN];
u8 p2p_peer_device_addr[ETH_ALEN];
u8 peer_intent; /* Included the intent value and tie breaker value. */
/* Device name for displaying on searching device screen */
u8 device_name[WPS_MAX_DEVICE_NAME_LEN];
u8 device_name_len;
u8 profileindex; /* Used to point to the index of profileinfo array */
u8 peer_operating_ch;
u8 find_phase_state_exchange_cnt;
/* The device password ID for group negotiation */
u16 device_password_id_for_nego;
u8 negotiation_dialog_token;
/* SSID information for group negotitation */
u8 nego_ssid[WLAN_SSID_MAXLEN];
u8 nego_ssidlen;
u8 p2p_group_ssid[WLAN_SSID_MAXLEN];
u8 p2p_group_ssid_len;
/* Flag to know if the persistent function should be supported or not.*/
u8 persistent_supported;
/* In the Sigma test, the Sigma will provide this enable from the
* sta_set_p2p CAPI. */
/* 0: disable */
/* 1: enable */
u8 session_available; /* Flag to set the WFD session available to
* enable or disable "by Sigma" */
/* In the Sigma test, the Sigma will disable the session available
* by using the sta_preset CAPI. */
/* 0: disable */
/* 1: enable */
/* This field will store the WPS value (PIN value or PBC) that UI had
* got from the user. */
enum P2P_WPSINFO ui_got_wps_info;
u16 supported_wps_cm; /* This field describes the WPS config method
* which this driver supported. */
/* The value should be the combination of config
* method defined in page104 of WPS v2.0 spec.*/
/* This field will contain the length of body of P2P Channel List
* attribute of group negotiation response frame. */
uint channel_list_attr_len;
/* This field will contain the body of P2P Channel List attribute of
* group negotitation response frame. */
/* We will use the channel_cnt and channel_list fields when constructing
* the group negotiation confirm frame. */
u8 channel_list_attr[100];
enum P2P_PS_MODE p2p_ps_mode; /* indicate p2p ps mode */
enum P2P_PS_STATE p2p_ps_state; /* indicate p2p ps state */
u8 noa_index; /* Identifies and instance of Notice of Absence timing. */
u8 ctwindow; /* Client traffic window. A period of time in TU after TBTT. */
u8 opp_ps; /* opportunistic power save. */
u8 noa_num; /* number of NoA descriptor in P2P IE. */
u8 noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */
/* Max duration for owner, preferred or min acceptable duration for
* client. */
u32 noa_duration[P2P_MAX_NOA_NUM];
/* Length of interval for owner, preferred or max acceptable interval
* of client. */
u32 noa_interval[P2P_MAX_NOA_NUM];
/* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
u32 noa_start_time[P2P_MAX_NOA_NUM];
};
struct tdls_ss_record { /* signal strength record */
u8 macaddr[ETH_ALEN];
u8 RxPWDBAll;
u8 is_tdls_sta; /* true: direct link sta, false: else */
};
struct tdls_info {
u8 ap_prohibited;
uint setup_state;
u8 sta_cnt;
u8 sta_maximum; /* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */
struct tdls_ss_record ss_record;
u8 macid_index; /* macid entry that is ready to write */
u8 clear_cam; /* cam entry that is trying to clear, using it in direct link teardown */
u8 ch_sensing;
u8 cur_channel;
u8 candidate_ch;
u8 collect_pkt_num[MAX_CHANNEL_NUM];
spinlock_t cmd_lock;
spinlock_t hdl_lock;
u8 watchdog_count;
u8 dev_discovered; /* WFD_TDLS: for sigma test */
u8 enable;
};
struct qos_priv {
/* bit mask option: u-apsd,
* s-apsd, ts, block ack... */
unsigned int qos_option;
};
struct mlme_priv {
spinlock_t lock;
int fw_state; /* shall we protect this variable? maybe not necessarily... */
bool bScanInProcess;
u8 to_join; /* flag */
u8 to_roaming; /* roaming trying times */
u8 *nic_hdl;
struct list_head *pscanned;
struct __queue free_bss_pool;
struct __queue scanned_queue;
u8 *free_bss_buf;
u8 key_mask; /* use to restore wep key after hal_init */
u32 num_of_scanned;
struct ndis_802_11_ssid assoc_ssid;
u8 assoc_bssid[6];
struct wlan_network cur_network;
struct wlan_network *cur_network_scanned;
u32 scan_interval;
struct timer_list assoc_timer;
uint assoc_by_bssid;
uint assoc_by_rssi;
struct timer_list scan_to_timer; /* driver itself handles scan_timeout status. */
u32 scan_start_time; /* used to evaluate the time spent in scanning */
struct qos_priv qospriv;
/* Number of non-HT AP/stations */
int num_sta_no_ht;
/* Number of HT AP/stations 20 MHz */
/* int num_sta_ht_20mhz; */
int num_FortyMHzIntolerant;
struct ht_priv htpriv;
struct rt_link_detect LinkDetectInfo;
struct timer_list dynamic_chk_timer; /* dynamic/periodic check timer */
u8 acm_mask; /* for wmm acm mask */
u8 ChannelPlan;
enum rt_scan_type scan_mode; /* active: 1, passive: 0 */
/* u8 probereq_wpsie[MAX_WPS_IE_LEN];added in probe req */
/* int probereq_wpsie_len; */
u8 *wps_probe_req_ie;
u32 wps_probe_req_ie_len;
u8 *assoc_req;
u32 assoc_req_len;
/* Number of associated Non-ERP stations (i.e., stations using 802.11b
* in 802.11g BSS) */
int num_sta_non_erp;
/* Number of associated stations that do not support Short Slot Time */
int num_sta_no_short_slot_time;
/* Number of associated stations that do not support Short Preamble */
int num_sta_no_short_preamble;
int olbc; /* Overlapping Legacy BSS Condition */
/* Number of HT assoc sta that do not support greenfield */
int num_sta_ht_no_gf;
/* Number of associated non-HT stations */
/* int num_sta_no_ht; */
/* Number of HT associated stations 20 MHz */
int num_sta_ht_20mhz;
/* Overlapping BSS information */
int olbc_ht;
u16 ht_op_mode;
u8 *wps_beacon_ie;
/* u8 *wps_probe_req_ie; */
u8 *wps_probe_resp_ie;
u8 *wps_assoc_resp_ie;
u32 wps_beacon_ie_len;
u32 wps_probe_resp_ie_len;
u32 wps_assoc_resp_ie_len;
u8 *p2p_beacon_ie;
u8 *p2p_probe_req_ie;
u8 *p2p_probe_resp_ie;
u8 *p2p_go_probe_resp_ie; /* for GO */
u8 *p2p_assoc_req_ie;
u32 p2p_beacon_ie_len;
u32 p2p_probe_req_ie_len;
u32 p2p_probe_resp_ie_len;
u32 p2p_go_probe_resp_ie_len; /* for GO */
u32 p2p_assoc_req_ie_len;
spinlock_t bcn_update_lock;
u8 update_bcn;
};
int hostapd_mode_init(struct adapter *padapter);
void hostapd_mode_unload(struct adapter *padapter);
extern unsigned char WPA_TKIP_CIPHER[4];
extern unsigned char RSN_TKIP_CIPHER[4];
extern unsigned char REALTEK_96B_IE[];
extern unsigned char MCS_rate_2R[16];
extern unsigned char MCS_rate_1R[16];
void rtw_joinbss_event_prehandle(struct adapter *adapter, u8 *pbuf);
void rtw_survey_event_callback(struct adapter *adapter, u8 *pbuf);
void rtw_surveydone_event_callback(struct adapter *adapter, u8 *pbuf);
void rtw_joinbss_event_callback(struct adapter *adapter, u8 *pbuf);
void rtw_stassoc_event_callback(struct adapter *adapter, u8 *pbuf);
void rtw_stadel_event_callback(struct adapter *adapter, u8 *pbuf);
void indicate_wx_scan_complete_event(struct adapter *padapter);
void rtw_indicate_wx_assoc_event(struct adapter *padapter);
void rtw_indicate_wx_disassoc_event(struct adapter *padapter);
int event_thread(void *context);
void rtw_free_network_queue(struct adapter *adapter, u8 isfreeall);
int rtw_init_mlme_priv(struct adapter *adapter);
void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv);
int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);
int rtw_set_key(struct adapter *adapter, struct security_priv *psecuritypriv,
int keyid, u8 set_tx);
int rtw_set_auth(struct adapter *adapter, struct security_priv *psecuritypriv);
static inline u8 *get_bssid(struct mlme_priv *pmlmepriv)
{ /* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */
/* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */
return pmlmepriv->cur_network.network.MacAddress;
}
static inline bool check_fwstate(struct mlme_priv *pmlmepriv, int state)
{
if (pmlmepriv->fw_state & state)
return true;
return false;
}
/*
* No Limit on the calling context,
* therefore set it to be the critical section...
*
* ### NOTE:#### (!!!!)
* MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
*/
static inline void set_fwstate(struct mlme_priv *pmlmepriv, int state)
{
pmlmepriv->fw_state |= state;
/* FOR HW integration */
if (_FW_UNDER_SURVEY == state)
pmlmepriv->bScanInProcess = true;
}
static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, int state)
{
pmlmepriv->fw_state &= ~state;
/* FOR HW integration */
if (_FW_UNDER_SURVEY == state)
pmlmepriv->bScanInProcess = false;
}
/*
* No Limit on the calling context,
* therefore set it to be the critical section...
*/
static inline void clr_fwstate(struct mlme_priv *pmlmepriv, int state)
{
spin_lock_bh(&pmlmepriv->lock);
if (check_fwstate(pmlmepriv, state))
pmlmepriv->fw_state ^= state;
spin_unlock_bh(&pmlmepriv->lock);
}
static inline void clr_fwstate_ex(struct mlme_priv *pmlmepriv, int state)
{
spin_lock_bh(&pmlmepriv->lock);
_clr_fwstate_(pmlmepriv, state);
spin_unlock_bh(&pmlmepriv->lock);
}
static inline void up_scanned_network(struct mlme_priv *pmlmepriv)
{
spin_lock_bh(&pmlmepriv->lock);
pmlmepriv->num_of_scanned++;
spin_unlock_bh(&pmlmepriv->lock);
}
static inline void down_scanned_network(struct mlme_priv *pmlmepriv)
{
spin_lock_bh(&pmlmepriv->lock);
pmlmepriv->num_of_scanned--;
spin_unlock_bh(&pmlmepriv->lock);
}
static inline void set_scanned_network_val(struct mlme_priv *pmlmepriv, int val)
{
spin_lock_bh(&pmlmepriv->lock);
pmlmepriv->num_of_scanned = val;
spin_unlock_bh(&pmlmepriv->lock);
}
u16 rtw_get_capability(struct wlan_bssid_ex *bss);
void rtw_update_scanned_network(struct adapter *adapter,
struct wlan_bssid_ex *target);
void rtw_disconnect_hdl_under_linked(struct adapter *adapter,
struct sta_info *psta, u8 free_assoc);
void rtw_generate_random_ibss(u8 *pibss);
struct wlan_network *rtw_find_network(struct __queue *scanned_queue, u8 *addr);
struct wlan_network *rtw_get_oldest_wlan_network(struct __queue *scanned_queue);
void rtw_free_assoc_resources(struct adapter *adapter, int lock_scanned_queue);
void rtw_indicate_disconnect(struct adapter *adapter);
void rtw_indicate_connect(struct adapter *adapter);
void rtw_indicate_scan_done(struct adapter *padapter);
int rtw_restruct_sec_ie(struct adapter *adapter, u8 *in_ie, u8 *out_ie,
uint in_len);
int rtw_restruct_wmm_ie(struct adapter *adapter, u8 *in_ie, u8 *out_ie,
uint in_len, uint initial_out_len);
void rtw_init_registrypriv_dev_network(struct adapter *adapter);
void rtw_update_registrypriv_dev_network(struct adapter *adapter);
void _rtw_join_timeout_handler(struct adapter *adapter);
void rtw_scan_timeout_handler(struct adapter *adapter);
void rtw_dynamic_check_timer_handlder(struct adapter *adapter);
void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);
struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv);
void _rtw_free_network(struct mlme_priv *pmlmepriv,
struct wlan_network *pnetwork, u8 isfreeall);
struct wlan_network *_rtw_find_network(struct __queue *scanned_queue, u8 *addr);
void _rtw_free_network_queue(struct adapter *padapter, u8 isfreeall);
int rtw_if_up(struct adapter *padapter);
u8 *rtw_get_capability_from_ie(u8 *ie);
u8 *rtw_get_beacon_interval_from_ie(u8 *ie);
void rtw_joinbss_reset(struct adapter *padapter);
unsigned int rtw_restructure_ht_ie(struct adapter *padapter, u8 *in_ie,
u8 *out_ie, uint in_len, uint *pout_len);
void rtw_update_ht_cap(struct adapter *padapter, u8 *pie, uint ie_len);
void rtw_issue_addbareq_cmd(struct adapter *padapter,
struct xmit_frame *pxmitframe);
int rtw_is_same_ibss(struct adapter *adapter, struct wlan_network *pnetwork);
int is_same_network(struct wlan_bssid_ex *src, struct wlan_bssid_ex *dst);
void rtw_roaming(struct adapter *padapter, struct wlan_network *tgt_network);
void _rtw_roaming(struct adapter *padapter, struct wlan_network *tgt_network);
void rtw_set_roaming(struct adapter *adapter, u8 to_roaming);
u8 rtw_to_roaming(struct adapter *adapter);
void rtw_set_max_rpt_macid(struct adapter *adapter, u8 macid);
void rtw_sta_media_status_rpt(struct adapter *adapter, struct sta_info *psta,
u32 mstatus);
u8 rtw_current_antenna(struct adapter *adapter);
#endif /* __RTL871X_MLME_H_ */

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drivers/staging/r8188eu/include/rtw_mlme_ext.h
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@ -1,753 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_MLME_EXT_H_
#define __RTW_MLME_EXT_H_
#include "osdep_service.h"
#include "drv_types.h"
#include "wlan_bssdef.h"
/* Commented by Albert 20101105 */
/* Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) */
/* The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. */
/* So, this driver tried to extend the dwell time for each scanning channel. */
/* This will increase the chance to receive the probe response from SoftAP. */
#define SURVEY_TO (100)
#define REAUTH_TO (300) /* 50) */
#define REASSOC_TO (300) /* 50) */
/* define DISCONNECT_TO (3000) */
#define ADDBA_TO (2000)
#define LINKED_TO (1) /* unit:2 sec, 1x2=2 sec */
#define REAUTH_LIMIT (4)
#define REASSOC_LIMIT (4)
#define DYNAMIC_FUNC_DISABLE (0x0)
/* ====== ODM_ABILITY_E ======== */
/* BB ODM section BIT 0-15 */
#define DYNAMIC_BB_DIG BIT(0)
#define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF
#define _HW_STATE_NOLINK_ 0x00
#define _HW_STATE_ADHOC_ 0x01
#define _HW_STATE_STATION_ 0x02
#define _HW_STATE_AP_ 0x03
#define _1M_RATE_ 0
#define _2M_RATE_ 1
#define _5M_RATE_ 2
#define _11M_RATE_ 3
#define _6M_RATE_ 4
#define _9M_RATE_ 5
#define _12M_RATE_ 6
#define _18M_RATE_ 7
#define _24M_RATE_ 8
#define _36M_RATE_ 9
#define _48M_RATE_ 10
#define _54M_RATE_ 11
extern unsigned char RTW_WPA_OUI[];
extern unsigned char WMM_OUI[];
extern unsigned char WPS_OUI[];
extern unsigned char WFD_OUI[];
extern unsigned char P2P_OUI[];
extern unsigned char WMM_INFO_OUI[];
extern unsigned char WMM_PARA_OUI[];
/* Channel Plan Type. */
/* Note: */
/* We just add new channel plan when the new channel plan is different
* from any of the following channel plan. */
/* If you just want to customize the actions(scan period or join actions)
* about one of the channel plan, */
/* customize them in struct rt_channel_info in the RT_CHANNEL_LIST. */
enum RT_CHANNEL_DOMAIN {
/* old channel plan mapping ===== */
RT_CHANNEL_DOMAIN_FCC = 0x00,
RT_CHANNEL_DOMAIN_IC = 0x01,
RT_CHANNEL_DOMAIN_ETSI = 0x02,
RT_CHANNEL_DOMAIN_SPAIN = 0x03,
RT_CHANNEL_DOMAIN_FRANCE = 0x04,
RT_CHANNEL_DOMAIN_MKK = 0x05,
RT_CHANNEL_DOMAIN_MKK1 = 0x06,
RT_CHANNEL_DOMAIN_ISRAEL = 0x07,
RT_CHANNEL_DOMAIN_TELEC = 0x08,
RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09,
RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A,
RT_CHANNEL_DOMAIN_TAIWAN = 0x0B,
RT_CHANNEL_DOMAIN_CHINA = 0x0C,
RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D,
RT_CHANNEL_DOMAIN_KOREA = 0x0E,
RT_CHANNEL_DOMAIN_TURKEY = 0x0F,
RT_CHANNEL_DOMAIN_JAPAN = 0x10,
RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11,
RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12,
RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14,
/* new channel plan mapping, (2GDOMAIN_5GDOMAIN) ===== */
RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20,
RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21,
RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22,
RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23,
RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24,
RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25,
RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26,
RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27,
RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28,
RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29,
RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30,
RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31,
RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32,
RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33,
RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34,
RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35,
RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36,
RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37,
RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38,
RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39,
RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40,
RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G = 0x41,
/* Add new channel plan above this line=============== */
RT_CHANNEL_DOMAIN_MAX,
RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F,
};
enum RT_CHANNEL_DOMAIN_2G {
RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, /* Worldwide 13 */
RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, /* Europe */
RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, /* US */
RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, /* Japan */
RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, /* France */
RT_CHANNEL_DOMAIN_2G_NULL = 0x05,
/* Add new channel plan above this line=============== */
RT_CHANNEL_DOMAIN_2G_MAX,
};
#define rtw_is_channel_plan_valid(chplan) \
(chplan < RT_CHANNEL_DOMAIN_MAX || \
chplan == RT_CHANNEL_DOMAIN_REALTEK_DEFINE)
struct rt_channel_plan {
unsigned char Channel[MAX_CHANNEL_NUM];
unsigned char Len;
};
struct rt_channel_plan_map {
unsigned char Index2G;
};
enum Associated_AP {
atherosAP = 0,
broadcomAP = 1,
ciscoAP = 2,
marvellAP = 3,
ralinkAP = 4,
realtekAP = 5,
airgocapAP = 6,
unknownAP = 7,
maxAP,
};
enum HT_IOT_PEER {
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
HT_IOT_PEER_REALTEK_92SE = 2,
HT_IOT_PEER_BROADCOM = 3,
HT_IOT_PEER_RALINK = 4,
HT_IOT_PEER_ATHEROS = 5,
HT_IOT_PEER_CISCO = 6,
HT_IOT_PEER_MERU = 7,
HT_IOT_PEER_MARVELL = 8,
HT_IOT_PEER_REALTEK_SOFTAP = 9,/* peer is RealTek SOFT_AP */
HT_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
HT_IOT_PEER_AIRGO = 11,
HT_IOT_PEER_INTEL = 12,
HT_IOT_PEER_RTK_APCLIENT = 13,
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_TENDA = 16,
HT_IOT_PEER_MAX = 17
};
enum SCAN_STATE {
SCAN_DISABLE = 0,
SCAN_START = 1,
SCAN_TXNULL = 2,
SCAN_PROCESS = 3,
SCAN_COMPLETE = 4,
SCAN_STATE_MAX,
};
typedef void (*mlme_handler)(struct adapter *adapt, struct recv_frame *frame);
struct ss_res {
int state;
int bss_cnt;
int channel_idx;
int scan_mode;
u8 ssid_num;
u8 ch_num;
struct ndis_802_11_ssid ssid[RTW_SSID_SCAN_AMOUNT];
struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
};
/* define AP_MODE 0x0C */
/* define STATION_MODE 0x08 */
/* define AD_HOC_MODE 0x04 */
/* define NO_LINK_MODE 0x00 */
#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_
#define WIFI_FW_STATION_STATE _HW_STATE_STATION_
#define WIFI_FW_AP_STATE _HW_STATE_AP_
#define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_
#define WIFI_FW_AUTH_NULL 0x00000100
#define WIFI_FW_AUTH_STATE 0x00000200
#define WIFI_FW_AUTH_SUCCESS 0x00000400
#define WIFI_FW_ASSOC_STATE 0x00002000
#define WIFI_FW_ASSOC_SUCCESS 0x00004000
#define WIFI_FW_LINKING_STATE (WIFI_FW_AUTH_NULL | \
WIFI_FW_AUTH_STATE | \
WIFI_FW_AUTH_SUCCESS | \
WIFI_FW_ASSOC_STATE)
struct FW_Sta_Info {
struct sta_info *psta;
u32 status;
u32 rx_pkt;
u32 retry;
unsigned char SupportedRates[NDIS_802_11_LENGTH_RATES_EX];
};
/*
* Usage:
* When one iface acted as AP mode and the other iface is STA mode and scanning,
* it should switch back to AP's operating channel periodically.
* Parameters info:
* When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to
* AP's operating channel for
* RTW_STAY_AP_CH_MILLISECOND * SURVEY_TO milliseconds.
* Example:
* For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
* RTW_SCAN_NUM_OF_CH is 8, RTW_STAY_AP_CH_MS is 3 and SURVEY_TO is 100.
* When it's STA mode gets set_scan command,
* it would
* 1. Doing the scan on channel 1.2.3.4.5.6.7.8
* 2. Back to channel 1 for 300 milliseconds
* 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52
* 4. Back to channel 1 for 300 milliseconds
* 5. ... and so on, till survey done.
*/
struct mlme_ext_info {
u32 state;
u32 reauth_count;
u32 reassoc_count;
u32 link_count;
u32 auth_seq;
u32 auth_algo; /* 802.11 auth, could be open, shared, auto */
u32 authModeToggle;
u32 enc_algo;/* encrypt algorithm; */
u32 key_index; /* this is only valid for legacy wep,
* 0~3 for key id. */
u32 iv;
u8 chg_txt[128];
u16 aid;
u16 bcn_interval;
u16 capability;
u8 assoc_AP_vendor;
u8 slotTime;
u8 preamble_mode;
u8 WMM_enable;
u8 ERP_enable;
u8 ERP_IE;
u8 HT_enable;
u8 HT_caps_enable;
u8 HT_info_enable;
u8 HT_protection;
u8 turboMode_cts2self;
u8 turboMode_rtsen;
u8 SM_PS;
u8 agg_enable_bitmap;
u8 ADDBA_retry_count;
u8 candidate_tid_bitmap;
u8 dialogToken;
/* Accept ADDBA Request */
bool bAcceptAddbaReq;
u8 bwmode_updated;
u8 hidden_ssid_mode;
struct WMM_para_element WMM_param;
struct HT_caps_element HT_caps;
struct HT_info_element HT_info;
struct wlan_bssid_ex network;/* join network or bss_network,
* if in ap mode, it is the same
* as cur_network.network */
struct FW_Sta_Info FW_sta_info[NUM_STA];
};
/* The channel information about this channel including joining,
* scanning, and power constraints. */
struct rt_channel_info {
u8 ChannelNum; /* The channel number. */
enum rt_scan_type ScanType; /* Scan type such as passive
* or active scan. */
u32 rx_count;
};
int rtw_ch_set_search_ch(struct rt_channel_info *ch_set, const u32 ch);
/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */
#define P2P_MAX_REG_CLASSES 10
/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of chan per regulatory class */
#define P2P_MAX_REG_CLASS_CHANNELS 20
/* struct p2p_channels - List of supported channels */
struct p2p_channels {
/* struct p2p_reg_class - Supported regulatory class */
struct p2p_reg_class {
/* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */
u8 reg_class;
/* channel - Supported channels */
u8 channel[P2P_MAX_REG_CLASS_CHANNELS];
/* channels - Number of channel entries in use */
size_t channels;
} reg_class[P2P_MAX_REG_CLASSES];
/* reg_classes - Number of reg_class entries in use */
size_t reg_classes;
};
struct p2p_oper_class_map {
enum hw_mode {IEEE80211G} mode;
u8 op_class;
u8 min_chan;
u8 max_chan;
u8 inc;
enum {BW20, BW40PLUS, BW40MINUS} bw;
};
struct mlme_ext_priv {
struct adapter *padapter;
u8 mlmeext_init;
atomic_t event_seq;
u16 mgnt_seq;
unsigned char cur_channel;
unsigned char cur_bwmode;
unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */
unsigned char cur_wireless_mode; /* NETWORK_TYPE */
unsigned char oper_channel; /* saved chan info when call
* set_channel_bw */
unsigned char oper_bwmode;
unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */
unsigned char max_chan_nums;
struct rt_channel_info channel_set[MAX_CHANNEL_NUM];
struct p2p_channels channel_list;
unsigned char basicrate[NumRates];
unsigned char datarate[NumRates];
struct ss_res sitesurvey_res;
struct mlme_ext_info mlmext_info;/* for sta/adhoc mode, including
* current scan/connecting/connected
* related info. For ap mode,
* network includes ap's cap_info*/
struct timer_list survey_timer;
struct timer_list link_timer;
u16 chan_scan_time;
u8 scan_abort;
u8 tx_rate; /* TXRATE when USERATE is set. */
u32 retry; /* retry for issue probereq */
u64 TSFValue;
unsigned char bstart_bss;
u8 update_channel_plan_by_ap_done;
/* recv_decache check for Action_public frame */
u8 action_public_dialog_token;
u16 action_public_rxseq;
u8 active_keep_alive_check;
};
void init_mlme_ext_priv(struct adapter *adapter);
int init_hw_mlme_ext(struct adapter *padapter);
void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext);
struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);
unsigned char networktype_to_raid(unsigned char network_type);
u8 judge_network_type(struct adapter *padapter, unsigned char *rate, int len);
void get_rate_set(struct adapter *padapter, unsigned char *pbssrate, int *len);
void Save_DM_Func_Flag(struct adapter *padapter);
void Restore_DM_Func_Flag(struct adapter *padapter);
void Set_MSR(struct adapter *padapter, u8 type);
u8 rtw_get_oper_ch(struct adapter *adapter);
void rtw_set_oper_ch(struct adapter *adapter, u8 ch);
void rtw_set_oper_bw(struct adapter *adapter, u8 bw);
void rtw_set_oper_choffset(struct adapter *adapter, u8 offset);
void set_channel_bwmode(struct adapter *padapter, unsigned char channel,
unsigned char channel_offset, unsigned short bwmode);
void SelectChannel(struct adapter *padapter, unsigned char channel);
void SetBWMode(struct adapter *padapter, unsigned short bwmode,
unsigned char channel_offset);
unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval);
void write_cam(struct adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key);
void clear_cam_entry(struct adapter *padapter, u8 entry);
void invalidate_cam_all(struct adapter *padapter);
int allocate_fw_sta_entry(struct adapter *padapter);
void flush_all_cam_entry(struct adapter *padapter);
void rtw_mlme_under_site_survey(struct adapter *adapter);
void rtw_mlme_site_survey_done(struct adapter *adapter);
void site_survey(struct adapter *padapter);
u8 collect_bss_info(struct adapter *padapter, struct recv_frame *precv_frame,
struct wlan_bssid_ex *bssid);
void update_network(struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src,
struct adapter *adapter, bool update_ie);
u8 *get_my_bssid(struct wlan_bssid_ex *pnetwork);
u16 get_beacon_interval(struct wlan_bssid_ex *bss);
bool r8188eu_is_client_associated_to_ap(struct adapter *padapter);
bool r8188eu_is_client_associated_to_ibss(struct adapter *padapter);
bool r8188eu_is_ibss_empty(struct adapter *padapter);
unsigned char check_assoc_AP(u8 *pframe, uint len);
int WMM_param_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE);
void WMMOnAssocRsp(struct adapter *padapter);
void HT_caps_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE);
void HT_info_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE);
void HTOnAssocRsp(struct adapter *padapter);
void ERP_IE_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE);
void VCS_update(struct adapter *padapter, struct sta_info *psta);
void update_beacon_info(struct adapter *padapter, u8 *ie_ptr, uint ie_len, struct sta_info *psta);
int rtw_check_bcn_info(struct adapter *Adapter, u8 *pframe, u32 packet_len);
void update_IOT_info(struct adapter *padapter);
void update_capinfo(struct adapter *adapter, u16 updatecap);
void update_wireless_mode(struct adapter *padapter);
void rtw_set_basic_rate(struct adapter *adapter, u8 *rates);
void update_tx_basic_rate(struct adapter *padapter, u8 modulation);
void update_bmc_sta_support_rate(struct adapter *padapter, u32 mac_id);
int update_sta_support_rate(struct adapter *padapter, u8 *pvar_ie,
uint var_ie_len, int cam_idx);
/* for sta/adhoc mode */
void update_sta_info(struct adapter *padapter, struct sta_info *psta);
unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);
unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);
unsigned int update_MSC_rate(struct HT_caps_element *pHT_caps);
void Update_RA_Entry(struct adapter *padapter, u32 mac_id);
void set_sta_rate(struct adapter *padapter, struct sta_info *psta);
void receive_disconnect(struct adapter *padapter, unsigned char *macaddr, unsigned short reason);
unsigned char get_highest_rate_idx(u32 mask);
int support_short_GI(struct adapter *padapter, struct HT_caps_element *caps);
bool is_ap_in_tkip(struct adapter *padapter);
void report_join_res(struct adapter *padapter, int res);
void report_survey_event(struct adapter *padapter, struct recv_frame *precv_frame);
void report_surveydone_event(struct adapter *padapter);
void report_del_sta_event(struct adapter *padapter,
unsigned char *addr, unsigned short reason);
void report_add_sta_event(struct adapter *padapter, unsigned char *addr,
int cam_idx);
void beacon_timing_control(struct adapter *padapter);
u8 set_tx_beacon_cmd(struct adapter *padapter);
unsigned int setup_beacon_frame(struct adapter *padapter,
unsigned char *beacon_frame);
void update_mgnt_tx_rate(struct adapter *padapter, u8 rate);
void update_mgntframe_attrib(struct adapter *padapter,
struct pkt_attrib *pattrib);
void dump_mgntframe(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 dump_mgntframe_and_wait(struct adapter *padapter,
struct xmit_frame *pmgntframe, int timeout_ms);
s32 dump_mgntframe_and_wait_ack(struct adapter *padapter,
struct xmit_frame *pmgntframe);
void issue_probersp_p2p(struct adapter *padapter, unsigned char *da);
void issue_p2p_provision_request(struct adapter *padapter, u8 *pssid,
u8 ussidlen, u8 *pdev_raddr);
void issue_p2p_GO_request(struct adapter *padapter, u8 *raddr);
void issue_probereq_p2p(struct adapter *padapter);
void issue_p2p_invitation_response(struct adapter *padapter, u8 *raddr,
u8 dialogToken, u8 success);
void issue_p2p_invitation_request(struct adapter *padapter, u8 *raddr);
void issue_beacon(struct adapter *padapter, int timeout_ms);
void issue_probersp(struct adapter *padapter, unsigned char *da,
u8 is_valid_p2p_probereq);
void issue_assocreq(struct adapter *padapter);
void issue_asocrsp(struct adapter *padapter, unsigned short status,
struct sta_info *pstat, int pkt_type);
void issue_auth(struct adapter *padapter, struct sta_info *psta,
unsigned short status);
void issue_probereq(struct adapter *padapter, struct ndis_802_11_ssid *pssid,
u8 *da);
void issue_probereq_ex(struct adapter *padapter, struct ndis_802_11_ssid *pssid, u8 *da);
int issue_nulldata(struct adapter *padapter, unsigned char *da,
unsigned int power_mode, int try_cnt, int wait_ms);
int issue_qos_nulldata(struct adapter *padapter, unsigned char *da,
u16 tid, int try_cnt, int wait_ms);
int issue_deauth(struct adapter *padapter, unsigned char *da,
unsigned short reason);
int issue_deauth_ex(struct adapter *padapter, u8 *da, unsigned short reason,
int try_cnt, int wait_ms);
void issue_action_BA(struct adapter *padapter, unsigned char *raddr, u8 action,
u16 status, struct ieee80211_mgmt *mgmt_req);
unsigned int send_delba(struct adapter *padapter, u8 initiator, u8 *addr);
unsigned int send_beacon(struct adapter *padapter);
bool get_beacon_valid_bit(struct adapter *adapter);
void clear_beacon_valid_bit(struct adapter *adapter);
void rtw_resume_tx_beacon(struct adapter *adapt);
void rtw_stop_tx_beacon(struct adapter *adapt);
void start_clnt_assoc(struct adapter *padapter);
void start_clnt_auth(struct adapter *padapter);
void start_clnt_join(struct adapter *padapter);
void start_create_ibss(struct adapter *padapter);
void mlmeext_joinbss_event_callback(struct adapter *padapter, int join_res);
void mlmeext_sta_del_event_callback(struct adapter *padapter);
void mlmeext_sta_add_event_callback(struct adapter *padapter,
struct sta_info *psta);
void linked_status_chk(struct adapter *padapter);
void survey_timer_hdl (struct adapter *padapter);
void link_timer_hdl (struct adapter *padapter);
void addba_timer_hdl(struct sta_info *psta);
#define set_survey_timer(mlmeext, ms) \
do { \
_set_timer(&(mlmeext)->survey_timer, (ms)); \
} while (0)
#define set_link_timer(mlmeext, ms) \
do { \
_set_timer(&(mlmeext)->link_timer, (ms)); \
} while (0)
bool cckrates_included(unsigned char *rate, int ratelen);
bool cckratesonly_included(unsigned char *rate, int ratelen);
struct cmd_hdl {
uint parmsize;
u8 (*h2cfuns)(struct adapter *padapter, u8 *pbuf);
};
u8 read_macreg_hdl(struct adapter *padapter, u8 *pbuf);
u8 write_macreg_hdl(struct adapter *padapter, u8 *pbuf);
u8 read_bbreg_hdl(struct adapter *padapter, u8 *pbuf);
u8 write_bbreg_hdl(struct adapter *padapter, u8 *pbuf);
u8 read_rfreg_hdl(struct adapter *padapter, u8 *pbuf);
u8 write_rfreg_hdl(struct adapter *padapter, u8 *pbuf);
u8 NULL_hdl(struct adapter *padapter, u8 *pbuf);
u8 join_cmd_hdl(struct adapter *padapter, u8 *pbuf);
u8 disconnect_hdl(struct adapter *padapter, u8 *pbuf);
u8 createbss_hdl(struct adapter *padapter, u8 *pbuf);
u8 setopmode_hdl(struct adapter *padapter, u8 *pbuf);
u8 sitesurvey_cmd_hdl(struct adapter *padapter, u8 *pbuf);
u8 setauth_hdl(struct adapter *padapter, u8 *pbuf);
u8 setkey_hdl(struct adapter *padapter, u8 *pbuf);
u8 set_stakey_hdl(struct adapter *padapter, u8 *pbuf);
u8 set_assocsta_hdl(struct adapter *padapter, u8 *pbuf);
u8 del_assocsta_hdl(struct adapter *padapter, u8 *pbuf);
u8 add_ba_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 mlme_evt_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 h2c_msg_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 tx_beacon_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 set_ch_hdl(struct adapter *padapter, u8 *pbuf);
u8 set_chplan_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 led_blink_hdl(struct adapter *padapter, unsigned char *pbuf);
/* Handling DFS channel switch announcement ie. */
u8 set_csa_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 tdls_hdl(struct adapter *padapter, unsigned char *pbuf);
#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl},
#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd},
#ifdef _RTW_CMD_C_
static struct cmd_hdl wlancmds[] = {
GEN_DRV_CMD_HANDLER(0, NULL) /*0*/
GEN_DRV_CMD_HANDLER(0, NULL)
GEN_DRV_CMD_HANDLER(0, NULL)
GEN_DRV_CMD_HANDLER(0, NULL)
GEN_DRV_CMD_HANDLER(0, NULL)
GEN_DRV_CMD_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL) /*10*/
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/
GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl)
GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl)
GEN_MLME_EXT_HANDLER(sizeof (struct setopmode_parm), setopmode_hdl)
GEN_MLME_EXT_HANDLER(sizeof (struct sitesurvey_parm),
sitesurvey_cmd_hdl) /*18*/
GEN_MLME_EXT_HANDLER(sizeof (struct setauth_parm), setauth_hdl)
GEN_MLME_EXT_HANDLER(sizeof (struct setkey_parm), setkey_hdl) /*20*/
GEN_MLME_EXT_HANDLER(sizeof (struct set_stakey_parm), set_stakey_hdl)
GEN_MLME_EXT_HANDLER(sizeof (struct set_assocsta_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct del_assocsta_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct setstapwrstate_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct setbasicrate_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct getbasicrate_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct setdatarate_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct getdatarate_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct setphyinfo_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct getphyinfo_parm), NULL) /*30*/
GEN_MLME_EXT_HANDLER(sizeof (struct setphy_parm), NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct getphy_parm), NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL) /*40*/
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl)
GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL) /*50*/
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param),
tx_beacon_hdl) /*55*/
GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/
GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/
GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/
GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param),
set_chplan_hdl) /*59*/
GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param),
led_blink_hdl) /*60*/
GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param),
set_csa_hdl) /*61*/
GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param),
tdls_hdl) /*62*/
};
#endif
struct C2HEvent_Header {
#ifdef __LITTLE_ENDIAN
unsigned int len:16;
unsigned int ID:8;
unsigned int seq:8;
#elif defined(__BIG_ENDIAN)
unsigned int seq:8;
unsigned int ID:8;
unsigned int len:16;
#endif
unsigned int rsvd;
};
enum rtw_c2h_event {
GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/
GEN_EVT_CODE(_Read_BBREG),
GEN_EVT_CODE(_Read_RFREG),
GEN_EVT_CODE(_Read_EEPROM),
GEN_EVT_CODE(_Read_EFUSE),
GEN_EVT_CODE(_Read_CAM), /*5*/
GEN_EVT_CODE(_Get_BasicRate),
GEN_EVT_CODE(_Get_DataRate),
GEN_EVT_CODE(_Survey), /*8*/
GEN_EVT_CODE(_SurveyDone), /*9*/
GEN_EVT_CODE(_JoinBss), /*10*/
GEN_EVT_CODE(_AddSTA),
GEN_EVT_CODE(_DelSTA),
GEN_EVT_CODE(_AtimDone),
GEN_EVT_CODE(_TX_Report),
GEN_EVT_CODE(_CCX_Report), /*15*/
GEN_EVT_CODE(_DTM_Report),
GEN_EVT_CODE(_TX_Rate_Statistics),
GEN_EVT_CODE(_C2HLBK),
GEN_EVT_CODE(_FWDBG),
GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
GEN_EVT_CODE(_ADDBA),
GEN_EVT_CODE(_C2HBCN),
GEN_EVT_CODE(_ReportPwrState), /* filen: only for PCIE, USB */
GEN_EVT_CODE(_CloseRF), /* filen: only for PCIE,
* work around ASPM */
MAX_C2HEVT
};
#ifdef _RTW_MLME_EXT_C_
static struct fwevent wlanevents[] = {
{0, NULL}, /*0*/
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, &rtw_survey_event_callback}, /*8*/
{sizeof (struct surveydone_event), &rtw_surveydone_event_callback},/*9*/
{0, &rtw_joinbss_event_callback}, /*10*/
{sizeof(struct stassoc_event), &rtw_stassoc_event_callback},
{sizeof(struct stadel_event), &rtw_stadel_event_callback},
{0, NULL},
{0, NULL},
{0, NULL}, /*15*/
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL}, /*20*/
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
};
#endif/* _RTL_MLME_EXT_C_ */
#endif /* __RTW_MLME_EXT_H_ */

118
drivers/staging/r8188eu/include/rtw_p2p.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_P2P_H_
#define __RTW_P2P_H_
#include "drv_types.h"
u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo,
u8 *pbuf, u8 *pssid, u8 ussidlen,
u8 *pdev_raddr);
u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo,
u8 *pbuf, u8 status_code);
u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len, struct sta_info *psta);
u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe);
u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo,
u8 *pframe, uint len);
u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe,
uint len);
void p2p_protocol_wk_hdl(struct adapter *padapter, int intcmdtype);
void process_p2p_ps_ie(struct adapter *padapter, u8 *ies, u32 ielength);
void p2p_ps_wk_hdl(struct adapter *padapter, u8 p2p_ps_state);
u8 p2p_ps_wk_cmd(struct adapter *padapter, u8 p2p_ps_state, u8 enqueue);
void reset_global_wifidirect_info(struct adapter *padapter);
int rtw_init_wifi_display_info(struct adapter *padapter);
void rtw_init_wifidirect_timers(struct adapter *padapter);
void rtw_init_wifidirect_addrs(struct adapter *padapter, u8 *dev_addr,
u8 *iface_addr);
void init_wifidirect_info(struct adapter *padapter, enum P2P_ROLE role);
int rtw_p2p_enable(struct adapter *padapter, enum P2P_ROLE role);
static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo,
enum P2P_STATE state)
{
if (wdinfo->p2p_state != state)
wdinfo->p2p_state = state;
}
static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo,
enum P2P_STATE state)
{
if (wdinfo->pre_p2p_state != state)
wdinfo->pre_p2p_state = state;
}
static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo,
enum P2P_ROLE role)
{
if (wdinfo->role != role)
wdinfo->role = role;
}
static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)
{
return wdinfo->p2p_state;
}
static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo)
{
return wdinfo->pre_p2p_state;
}
static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo)
{
return wdinfo->role;
}
static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo,
enum P2P_STATE state)
{
return wdinfo->p2p_state == state;
}
static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo,
enum P2P_ROLE role)
{
return wdinfo->role == role;
}
#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)
#define rtw_p2p_set_pre_state(wdinfo, state) \
_rtw_p2p_set_pre_state(wdinfo, state)
#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)
#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)
#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)
#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo)
#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state)
#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role)
#define rtw_p2p_findphase_ex_set(wdinfo, value) \
((wdinfo)->find_phase_state_exchange_cnt = (value))
/* is this find phase exchange for social channel scan? */
#define rtw_p2p_findphase_ex_is_social(wdinfo) \
((wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST)
/* should we need find phase exchange anymore? */
#define rtw_p2p_findphase_ex_is_needed(wdinfo) \
((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \
(wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE)
#endif

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drivers/staging/r8188eu/include/rtw_pwrctrl.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#ifndef __RTW_PWRCTRL_H_
#define __RTW_PWRCTRL_H_
#include "osdep_service.h"
#include "drv_types.h"
#define XMIT_ALIVE BIT(0)
#define RECV_ALIVE BIT(1)
#define CMD_ALIVE BIT(2)
#define EVT_ALIVE BIT(3)
enum power_mgnt {
PS_MODE_ACTIVE = 0,
PS_MODE_MIN,
PS_MODE_MAX,
PS_MODE_DTIM,
PS_MODE_VOIP,
PS_MODE_UAPSD_WMM,
PM_Card_Disable,
PS_MODE_NUM
};
#define LPS_DELAY_TIME 1*HZ /* 1 sec */
/* RF state. */
enum rt_rf_power_state {
rf_on, /* RF is on after RFSleep or RFOff */
rf_sleep, /* 802.11 Power Save mode */
rf_off, /* HW/SW Radio OFF or Inactive Power Save */
/* Add the new RF state above this line===== */
rf_max
};
enum { /* for ips_mode */
IPS_NONE = 0,
IPS_NORMAL,
IPS_LEVEL_2,
};
struct pwrctrl_priv {
struct mutex lock; /* Mutex used to protect struct pwrctrl_priv */
u8 pwr_mode;
u8 smart_ps;
u8 bcn_ant_mode;
bool bpower_saving;
uint ips_enter_cnts;
uint ips_leave_cnts;
u8 ips_mode;
u8 ips_mode_req; /* used to accept the mode setting request,
* will update to ipsmode later */
uint bips_processing;
unsigned long ips_deny_time; /* will deny IPS when system time less than this */
u8 ps_processing; /* temp used to mark whether in rtw_ps_processor */
u8 bLeisurePs;
u8 LpsIdleCount;
u8 power_mgnt;
u8 bFwCurrentInPSMode;
u32 DelayLPSLastTimeStamp;
u8 bInSuspend;
u8 bSupportRemoteWakeup;
struct timer_list pwr_state_check_timer;
int pwr_state_check_interval;
enum rt_rf_power_state rf_pwrstate;/* cur power state */
u8 bkeepfwalive;
};
#define rtw_get_ips_mode_req(pwrctrlpriv) \
(pwrctrlpriv)->ips_mode_req
#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
((pwrctrlpriv)->ips_mode_req = (ips_mode))
#define RTW_PWR_STATE_CHK_INTERVAL 2000
#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
do { \
_set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \
} while (0)
#define rtw_set_pwr_state_check_timer(pwrctrl) \
_rtw_set_pwr_state_check_timer((pwrctrl), \
(pwrctrl)->pwr_state_check_interval)
void rtw_init_pwrctrl_priv(struct adapter *adapter);
void rtw_set_firmware_ps_mode(struct adapter *adapter, u8 mode);
void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps,
u8 bcn_ant_mode);
void LeaveAllPowerSaveMode(struct adapter *adapter);
void rtw_ps_processor(struct adapter *padapter);
void LPS_Enter(struct adapter *adapter);
void LPS_Leave(struct adapter *adapter);
int rtw_pwr_wakeup(struct adapter *adapter);
int rtw_pm_set_ips(struct adapter *adapter, u8 mode);
int rtw_pm_set_lps(struct adapter *adapter, u8 mode);
#endif /* __RTL871X_PWRCTRL_H_ */

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drivers/staging/r8188eu/include/rtw_recv.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#ifndef _RTW_RECV_H_
#define _RTW_RECV_H_
#include "osdep_service.h"
#include "drv_types.h"
#define NR_RECVFRAME 256
#define RXFRAME_ALIGN 8
#define RXFRAME_ALIGN_SZ (1<<RXFRAME_ALIGN)
#define MAX_RXFRAME_CNT 512
#define MAX_RX_NUMBLKS (32)
#define RECVFRAME_HDR_ALIGN 128
#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
#define MAX_SUBFRAME_COUNT 64
#define LLC_HEADER_SIZE 6
/* for Rx reordering buffer control */
struct recv_reorder_ctrl {
struct adapter *padapter;
u8 enable;
u16 indicate_seq;/* wstart_b, init_value=0xffff */
u16 wend_b;
u8 wsize_b;
struct __queue pending_recvframe_queue;
struct timer_list reordering_ctrl_timer;
};
struct stainfo_rxcache {
u16 tid_rxseq[16];
/*
unsigned short tid0_rxseq;
unsigned short tid1_rxseq;
unsigned short tid2_rxseq;
unsigned short tid3_rxseq;
unsigned short tid4_rxseq;
unsigned short tid5_rxseq;
unsigned short tid6_rxseq;
unsigned short tid7_rxseq;
unsigned short tid8_rxseq;
unsigned short tid9_rxseq;
unsigned short tid10_rxseq;
unsigned short tid11_rxseq;
unsigned short tid12_rxseq;
unsigned short tid13_rxseq;
unsigned short tid14_rxseq;
unsigned short tid15_rxseq;
*/
};
struct signal_stat {
u8 update_req; /* used to indicate */
u8 avg_val; /* avg of valid elements */
u32 total_num; /* num of valid elements */
u32 total_val; /* sum of valid elements */
};
#define MAX_PATH_NUM_92CS 3
struct phy_info {
u8 RxPWDBAll;
u8 SignalQuality; /* in 0-100 index. */
u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
s8 RxPower; /* in dBm Translate from PWdB */
/* Real power in dBm for this packet, no beautification and aggregation.
* Keep this raw info to be used for the other procedures. */
s8 recvpower;
u8 SignalStrength; /* in 0-100 index. */
u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
};
struct rx_pkt_attrib {
u16 pkt_len;
u8 physt;
u8 drvinfo_sz;
u8 shift_sz;
u8 hdrlen; /* the WLAN Header Len */
u8 amsdu;
bool qos;
u8 priority;
u8 pw_save;
u8 mdata;
u16 seq_num;
u8 frag_num;
u8 mfrag;
u8 order;
u8 privacy; /* in frame_ctrl field */
u8 bdecrypted;
u8 encrypt; /* when 0 indicate no encrypt. when non-zero,
* indicate the encrypt algorithm */
u8 iv_len;
u8 icv_len;
u8 crc_err;
u8 icv_err;
u16 eth_type;
u8 dst[ETH_ALEN] __aligned(2);
u8 src[ETH_ALEN] __aligned(2);
u8 ta[ETH_ALEN] __aligned(2);
u8 ra[ETH_ALEN] __aligned(2);
u8 bssid[ETH_ALEN] __aligned(2);
u8 ack_policy;
u8 key_index;
u8 mcs_rate;
u8 rxht;
u8 sgi;
u8 pkt_rpt_type;
u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */
struct phy_info phy_info;
};
/* These definition is used for Rx packet reordering. */
#define SN_LESS(a, b) (((a - b) & 0x800) != 0)
#define SN_EQUAL(a, b) (a == b)
#define REORDER_WAIT_TIME (50) /* (ms) */
#define RECVBUFF_ALIGN_SZ 8
#define RXDESC_SIZE 24
#define RXDESC_OFFSET RXDESC_SIZE
struct recv_stat {
__le32 rxdw0;
__le32 rxdw1;
__le32 rxdw2;
__le32 rxdw3;
__le32 rxdw4;
__le32 rxdw5;
};
#define EOR BIT(30)
/*
accesser of recv_priv: rtw_recv_entry(dispatch / passive level);
recv_thread(passive) ; returnpkt(dispatch)
; halt(passive) ;
using enter_critical section to protect
*/
struct recv_priv {
spinlock_t lock;
struct __queue free_recv_queue;
struct __queue recv_pending_queue;
struct __queue uc_swdec_pending_queue;
u8 *pallocated_frame_buf;
u8 *precv_frame_buf;
uint free_recvframe_cnt;
struct adapter *adapter;
u32 bIsAnyNonBEPkts;
u64 rx_bytes;
u64 rx_pkts;
u64 rx_drop;
u64 last_rx_bytes;
uint rx_icv_err;
uint rx_largepacket_crcerr;
uint rx_smallpacket_crcerr;
uint rx_middlepacket_crcerr;
u8 rx_pending_cnt;
struct tasklet_struct recv_tasklet;
struct sk_buff_head free_recv_skb_queue;
struct sk_buff_head rx_skb_queue;
u8 *pallocated_recv_buf;
u8 *precv_buf; /* 4 alignment */
struct __queue free_recv_buf_queue;
u32 free_recv_buf_queue_cnt;
/* For display the phy information */
u8 is_signal_dbg; /* for debug */
u8 signal_strength_dbg; /* for debug */
s8 rssi;
s8 rxpwdb;
u8 signal_strength;
u8 signal_qual;
u8 noise;
int RxSNRdB[2];
s8 RxRssi[2];
int FalseAlmCnt_all;
struct timer_list signal_stat_timer;
u32 signal_stat_sampling_interval;
struct signal_stat signal_qual_data;
struct signal_stat signal_strength_data;
};
#define rtw_set_signal_stat_timer(recvpriv) \
_set_timer(&(recvpriv)->signal_stat_timer, \
(recvpriv)->signal_stat_sampling_interval)
struct sta_recv_priv {
spinlock_t lock;
int option;
struct __queue defrag_q; /* keeping the fragment frame until defrag */
struct stainfo_rxcache rxcache;
};
struct recv_buf {
struct adapter *adapter;
struct urb *purb;
struct sk_buff *pskb;
u8 reuse;
};
/*
head ----->
data ----->
payload
tail ----->
end ----->
len = (unsigned int )(tail - data);
*/
struct recv_frame {
struct list_head list;
struct sk_buff *pkt;
struct adapter *adapter;
u8 fragcnt;
int frame_tag;
struct rx_pkt_attrib attrib;
uint len;
u8 *rx_head;
u8 *rx_data;
u8 *rx_tail;
u8 *rx_end;
void *precvbuf;
struct sta_info *psta;
/* for A-MPDU Rx reordering buffer control */
struct recv_reorder_ctrl *preorder_ctrl;
};
int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter);
void _rtw_free_recv_priv(struct recv_priv *precvpriv);
s32 rtw_recv_entry(struct recv_frame *precv_frame);
struct recv_frame *_rtw_alloc_recvframe(struct __queue *pfree_recv_queue);
struct recv_frame *rtw_alloc_recvframe(struct __queue *pfree_recv_queue);
int rtw_free_recvframe(struct recv_frame *precvframe,
struct __queue *pfree_recv_queue);
int _rtw_enqueue_recvframe(struct recv_frame *precvframe, struct __queue *queue);
int rtw_enqueue_recvframe(struct recv_frame *precvframe, struct __queue *queue);
void rtw_free_recvframe_queue(struct __queue *pframequeue,
struct __queue *pfree_recv_queue);
u32 rtw_free_uc_swdec_pending_queue(struct adapter *adapter);
void rtw_reordering_ctrl_timeout_handler(void *pcontext);
static inline u8 *get_rxmem(struct recv_frame *precvframe)
{
/* always return rx_head... */
if (precvframe == NULL)
return NULL;
return precvframe->rx_head;
}
static inline u8 *recvframe_pull(struct recv_frame *precvframe, int sz)
{
/* rx_data += sz; move rx_data sz bytes hereafter */
/* used for extract sz bytes from rx_data, update rx_data and return
* the updated rx_data to the caller */
if (precvframe == NULL)
return NULL;
precvframe->rx_data += sz;
if (precvframe->rx_data > precvframe->rx_tail) {
precvframe->rx_data -= sz;
return NULL;
}
precvframe->len -= sz;
return precvframe->rx_data;
}
static inline u8 *recvframe_put(struct recv_frame *precvframe, int sz)
{
/* used for append sz bytes from ptr to rx_tail, update rx_tail
* and return the updated rx_tail to the caller */
/* after putting, rx_tail must be still larger than rx_end. */
if (precvframe == NULL)
return NULL;
precvframe->rx_tail += sz;
if (precvframe->rx_tail > precvframe->rx_end) {
precvframe->rx_tail -= sz;
return NULL;
}
precvframe->len += sz;
return precvframe->rx_tail;
}
static inline u8 *recvframe_pull_tail(struct recv_frame *precvframe, int sz)
{
/* rmv data from rx_tail (by yitsen) */
/* used for extract sz bytes from rx_end, update rx_end and return
* the updated rx_end to the caller */
/* after pulling, rx_end must be still larger than rx_data. */
if (precvframe == NULL)
return NULL;
precvframe->rx_tail -= sz;
if (precvframe->rx_tail < precvframe->rx_data) {
precvframe->rx_tail += sz;
return NULL;
}
precvframe->len -= sz;
return precvframe->rx_tail;
}
static inline int get_recvframe_len(struct recv_frame *precvframe)
{
return precvframe->len;
}
static inline s32 translate_percentage_to_dbm(u32 sig_stren_index)
{
s32 power; /* in dBm. */
/* Translate to dBm (x=0.5y-95). */
power = (s32)((sig_stren_index + 1) >> 1);
power -= 95;
return power;
}
struct sta_info;
void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);
void mgt_dispatcher(struct adapter *padapter, struct recv_frame *precv_frame);
#endif

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drivers/staging/r8188eu/include/rtw_rf.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_RF_H_
#define __RTW_RF_H_
#include "rtw_cmd.h"
#define NumRates (13)
/* slot time for 11g */
#define SHORT_SLOT_TIME 9
#define NON_SHORT_SLOT_TIME 20
#define MAX_CHANNEL_NUM 14 /* 2.4 GHz only */
#define NUM_REGULATORYS 1
struct regulatory_class {
u32 starting_freq; /* MHz, */
u8 channel_set[MAX_CHANNEL_NUM];
u8 channel_cck_power[MAX_CHANNEL_NUM]; /* dbm */
u8 channel_ofdm_power[MAX_CHANNEL_NUM]; /* dbm */
u8 txpower_limit; /* dbm */
u8 channel_spacing; /* MHz */
u8 modem;
};
enum capability {
cESS = 0x0001,
cIBSS = 0x0002,
cPollable = 0x0004,
cPollReq = 0x0008,
cPrivacy = 0x0010,
cShortPreamble = 0x0020,
cPBCC = 0x0040,
cChannelAgility = 0x0080,
cSpectrumMgnt = 0x0100,
cQos = 0x0200, /* For HCCA, use with CF-Pollable
* and CF-PollReq */
cShortSlotTime = 0x0400,
cAPSD = 0x0800,
cRM = 0x1000, /* RRM (Radio Request Measurement) */
cDSSS_OFDM = 0x2000,
cDelayedBA = 0x4000,
cImmediateBA = 0x8000,
};
enum _REG_PREAMBLE_MODE {
PREAMBLE_LONG = 1,
PREAMBLE_AUTO = 2,
PREAMBLE_SHORT = 3,
};
/* Bandwidth Offset */
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
/* Represent Channel Width in HT Capabilities */
/* */
enum ht_channel_width {
HT_CHANNEL_WIDTH_20 = 0,
HT_CHANNEL_WIDTH_40 = 1,
};
/* */
/* Represent Extension Channel Offset in HT Capabilities */
/* This is available only in 40Mhz mode. */
/* */
enum ht_extchnl_offset {
HT_EXTCHNL_OFFSET_NO_EXT = 0,
HT_EXTCHNL_OFFSET_UPPER = 1,
HT_EXTCHNL_OFFSET_NO_DEF = 2,
HT_EXTCHNL_OFFSET_LOWER = 3,
};
u32 rtw_ch2freq(u32 ch);
#endif /* _RTL8711_RF_H_ */

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drivers/staging/r8188eu/include/rtw_security.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __RTW_SECURITY_H_
#define __RTW_SECURITY_H_
#include "osdep_service.h"
#include "drv_types.h"
#include <crypto/arc4.h>
#define _NO_PRIVACY_ 0x0
#define _WEP40_ 0x1
#define _TKIP_ 0x2
#define _TKIP_WTMIC_ 0x3
#define _AES_ 0x4
#define _WEP104_ 0x5
#define _SMS4_ 0x06
#define _WPA_IE_ID_ 0xdd
#define _WPA2_IE_ID_ 0x30
enum {
ENCRYP_PROTOCOL_OPENSYS, /* open system */
ENCRYP_PROTOCOL_WEP, /* WEP */
ENCRYP_PROTOCOL_WPA, /* WPA */
ENCRYP_PROTOCOL_WPA2, /* WPA2 */
ENCRYP_PROTOCOL_WAPI, /* WAPI: Not support in this version */
ENCRYP_PROTOCOL_MAX
};
#ifndef Ndis802_11AuthModeWPA2
#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)
#endif
#ifndef Ndis802_11AuthModeWPA2PSK
#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
#endif
union pn48 {
u64 val;
#ifdef __LITTLE_ENDIAN
struct {
u8 TSC0;
u8 TSC1;
u8 TSC2;
u8 TSC3;
u8 TSC4;
u8 TSC5;
u8 TSC6;
u8 TSC7;
} _byte_;
#elif defined(__BIG_ENDIAN)
struct {
u8 TSC7;
u8 TSC6;
u8 TSC5;
u8 TSC4;
u8 TSC3;
u8 TSC2;
u8 TSC1;
u8 TSC0;
} _byte_;
#endif
};
union Keytype {
u8 skey[16];
u32 lkey[4];
};
struct rt_pmkid_list {
u8 bUsed;
u8 Bssid[6];
u8 PMKID[16];
u8 SsidBuf[33];
u8 *ssid_octet;
u16 ssid_length;
};
struct security_priv {
u32 dot11AuthAlgrthm; /* 802.11 auth, could be open,
* shared, 8021x and authswitch */
u32 dot11PrivacyAlgrthm; /* This specify the privacy for
* shared auth. algorithm. */
/* WEP */
u32 dot11PrivacyKeyIndex; /* this is only valid for legendary
* wep, 0~3 for key id.(tx key index) */
union Keytype dot11DefKey[4]; /* this is only valid for def. key */
u32 dot11DefKeylen[4];
u32 dot118021XGrpPrivacy; /* This specify the privacy algthm.
* used for Grp key */
u32 dot118021XGrpKeyid; /* key id used for Grp Key
* ( tx key index) */
union Keytype dot118021XGrpKey[4]; /* 802.1x Group Key,
* for inx0 and inx1 */
union Keytype dot118021XGrptxmickey[4];
union Keytype dot118021XGrprxmickey[4];
union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit.*/
union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv.*/
struct arc4_ctx xmit_arc4_ctx;
struct arc4_ctx recv_arc4_ctx;
/* extend security capabilities for AP_MODE */
unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
unsigned int wpa_group_cipher;
unsigned int wpa2_group_cipher;
unsigned int wpa_pairwise_cipher;
unsigned int wpa2_pairwise_cipher;
u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */
int wps_ie_len;
u8 binstallGrpkey;
u8 busetkipkey;
u8 bcheck_grpkey;
u8 bgrpkey_handshake;
s32 sw_encrypt;/* from registry_priv */
s32 sw_decrypt;/* from registry_priv */
s32 hw_decrypted;/* if the rx packets is hw_decrypted==false,i
* it means the hw has not been ready. */
/* keeps the auth_type & enc_status from upper layer
* ioctl(wpa_supplicant or wzc) */
u32 ndisauthtype; /* NDIS_802_11_AUTHENTICATION_MODE */
u32 ndisencryptstatus; /* NDIS_802_11_ENCRYPTION_STATUS */
struct wlan_bssid_ex sec_bss; /* for joinbss (h2c buffer) usage */
struct ndis_802_11_wep ndiswep;
u8 assoc_info[600];
u8 szofcapability[256]; /* for wpa2 usage */
u8 oidassociation[512]; /* for wpa/wpa2 usage */
u8 authenticator_ie[256]; /* store ap security information element */
u8 supplicant_ie[256]; /* store sta security information element */
/* for tkip countermeasure */
u32 last_mic_err_time;
u8 btkip_countermeasure;
u8 btkip_wait_report;
u32 btkip_countermeasure_time;
/* */
/* For WPA2 Pre-Authentication. */
/* */
struct rt_pmkid_list PMKIDList[NUM_PMKID_CACHE];
u8 PMKIDIndex;
u8 bWepDefaultKeyIdxSet;
};
#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst) \
do { \
switch (psecuritypriv->dot11AuthAlgrthm) { \
case dot11AuthAlgrthm_Open: \
case dot11AuthAlgrthm_Shared: \
case dot11AuthAlgrthm_Auto: \
encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm; \
break; \
case dot11AuthAlgrthm_8021X: \
if (bmcst) \
encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\
else \
encry_algo = (u8)psta->dot118021XPrivacy; \
break; \
case dot11AuthAlgrthm_WAPI: \
encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm; \
break; \
} \
} while (0)
#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt) \
do { \
switch (encrypt) { \
case _WEP40_: \
case _WEP104_: \
iv_len = 4; \
icv_len = 4; \
break; \
case _TKIP_: \
iv_len = 8; \
icv_len = 4; \
break; \
case _AES_: \
iv_len = 8; \
icv_len = 8; \
break; \
case _SMS4_: \
iv_len = 18; \
icv_len = 16; \
break; \
default: \
iv_len = 0; \
icv_len = 0; \
break; \
} \
} while (0)
#define GET_TKIP_PN(iv, dot11txpn) \
do { \
dot11txpn._byte_.TSC0 = iv[2]; \
dot11txpn._byte_.TSC1 = iv[0]; \
dot11txpn._byte_.TSC2 = iv[4]; \
dot11txpn._byte_.TSC3 = iv[5]; \
dot11txpn._byte_.TSC4 = iv[6]; \
dot11txpn._byte_.TSC5 = iv[7]; \
} while (0)
#define ROL32(A, n) (((A) << (n)) | (((A)>>(32-(n))) & ((1UL << (n)) - 1)))
#define ROR32(A, n) ROL32((A), 32-(n))
struct mic_data {
u32 K0, K1; /* Key */
u32 L, R; /* Current state */
u32 M; /* Message accumulator (single word) */
u32 nBytesInM; /* # bytes in M */
};
void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key);
void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b);
void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes);
void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst);
void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len,
u8 *Miccode, u8 priority);
u32 rtw_aes_encrypt(struct adapter *padapter, struct xmit_frame *pxmitframe);
u32 rtw_tkip_encrypt(struct adapter *padapter, struct xmit_frame *pxmitframe);
void rtw_wep_encrypt(struct adapter *padapter, struct xmit_frame *pxmitframe);
u32 rtw_aes_decrypt(struct adapter *padapter, struct recv_frame *precvframe);
u32 rtw_tkip_decrypt(struct adapter *padapter, struct recv_frame *precvframe);
void rtw_wep_decrypt(struct adapter *padapter, struct recv_frame *precvframe);
#endif /* __RTL871X_SECURITY_H_ */

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drivers/staging/r8188eu/include/rtw_xmit.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef _RTW_XMIT_H_
#define _RTW_XMIT_H_
#include "osdep_service.h"
#include "drv_types.h"
#define NR_XMITFRAME 256
#define WMM_XMIT_THRESHOLD (NR_XMITFRAME * 2 / 5)
#define MAX_XMITBUF_SZ (20480) /* 20k */
#define NR_XMITBUFF (4)
#define XMITBUF_ALIGN_SZ 4
/* xmit extension buff defination */
#define MAX_XMIT_EXTBUF_SZ (1536)
#define NR_XMIT_EXTBUFF (32)
#define MAX_NUMBLKS (1)
#define XMIT_VO_QUEUE (0)
#define XMIT_VI_QUEUE (1)
#define XMIT_BE_QUEUE (2)
#define XMIT_BK_QUEUE (3)
#define VO_QUEUE_INX 0
#define VI_QUEUE_INX 1
#define BE_QUEUE_INX 2
#define BK_QUEUE_INX 3
#define BCN_QUEUE_INX 4
#define MGT_QUEUE_INX 5
#define HIGH_QUEUE_INX 6
#define TXCMD_QUEUE_INX 7
#define HW_QUEUE_ENTRY 8
#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
do {\
pattrib_iv[0] = dot11txpn._byte_.TSC0;\
pattrib_iv[1] = dot11txpn._byte_.TSC1;\
pattrib_iv[2] = dot11txpn._byte_.TSC2;\
pattrib_iv[3] = ((keyidx & 0x3)<<6);\
dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val+1);\
} while (0)
#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
do {\
pattrib_iv[0] = dot11txpn._byte_.TSC1;\
pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
pattrib_iv[2] = dot11txpn._byte_.TSC0;\
pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
pattrib_iv[4] = dot11txpn._byte_.TSC2;\
pattrib_iv[5] = dot11txpn._byte_.TSC3;\
pattrib_iv[6] = dot11txpn._byte_.TSC4;\
pattrib_iv[7] = dot11txpn._byte_.TSC5;\
dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\
} while (0)
#define AES_IV(pattrib_iv, dot11txpn, keyidx)\
do { \
pattrib_iv[0] = dot11txpn._byte_.TSC0; \
pattrib_iv[1] = dot11txpn._byte_.TSC1; \
pattrib_iv[2] = 0; \
pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6); \
pattrib_iv[4] = dot11txpn._byte_.TSC2; \
pattrib_iv[5] = dot11txpn._byte_.TSC3; \
pattrib_iv[6] = dot11txpn._byte_.TSC4; \
pattrib_iv[7] = dot11txpn._byte_.TSC5; \
dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\
} while (0)
#define HWXMIT_ENTRY 4
#define TXDESC_SIZE 32
#define PACKET_OFFSET_SZ (8)
#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
struct tx_desc {
/* DWORD 0 */
__le32 txdw0;
__le32 txdw1;
__le32 txdw2;
__le32 txdw3;
__le32 txdw4;
__le32 txdw5;
__le32 txdw6;
__le32 txdw7;
};
union txdesc {
struct tx_desc txdesc;
unsigned int value[TXDESC_SIZE>>2];
};
struct hw_xmit {
struct list_head *sta_list;
int accnt;
};
/* reduce size */
struct pkt_attrib {
u8 type;
u8 subtype;
u8 bswenc;
u8 dhcp_pkt;
u16 ether_type;
u16 seqnum;
u16 pkt_hdrlen; /* the original 802.3 pkt header len */
u16 hdrlen; /* the WLAN Header Len */
u32 pktlen; /* the original 802.3 pkt raw_data len (not include
* ether_hdr data) */
u32 last_txcmdsz;
u8 nr_frags;
u8 encrypt; /* when 0 indicate no encrypt. when non-zero,
* indicate the encrypt algorithm */
u8 iv_len;
u8 icv_len;
u8 iv[18];
u8 icv[16];
u8 priority;
u8 ack_policy;
u8 mac_id;
u8 vcs_mode; /* virtual carrier sense method */
u8 dst[ETH_ALEN] __aligned(2);
u8 src[ETH_ALEN] __aligned(2);
u8 ta[ETH_ALEN] __aligned(2);
u8 ra[ETH_ALEN] __aligned(2);
u8 key_idx;
u8 qos_en;
u8 ht_en;
u8 raid;/* rate adpative id */
u8 bwmode;
u8 ch_offset;/* PRIME_CHNL_OFFSET */
u8 sgi;/* short GI */
u8 ampdu_en;/* tx ampdu enable */
u8 mdata;/* more data bit */
u8 pctrl;/* per packet txdesc control enable */
u8 triggered;/* for ap mode handling Power Saving sta */
u8 qsel;
u8 eosp;
u8 rate;
u8 intel_proxim;
u8 retry_ctrl;
struct sta_info *psta;
};
#define WLANHDR_OFFSET 64
#define NULL_FRAMETAG (0x0)
#define DATA_FRAMETAG 0x01
#define MGNT_FRAMETAG 0x03
#define TXAGG_FRAMETAG 0x08
struct submit_ctx {
u32 submit_time; /* */
u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
int status; /* status for operation */
struct completion done;
};
enum {
RTW_SCTX_SUBMITTED = -1,
RTW_SCTX_DONE_SUCCESS = 0,
RTW_SCTX_DONE_UNKNOWN,
RTW_SCTX_DONE_TIMEOUT,
RTW_SCTX_DONE_BUF_ALLOC,
RTW_SCTX_DONE_BUF_FREE,
RTW_SCTX_DONE_WRITE_PORT_ERR,
RTW_SCTX_DONE_TX_DESC_NA,
RTW_SCTX_DONE_TX_DENY,
RTW_SCTX_DONE_CCX_PKT_FAIL,
RTW_SCTX_DONE_DRV_STOP,
RTW_SCTX_DONE_DEV_REMOVE,
};
void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
int rtw_sctx_wait(struct submit_ctx *sctx);
void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
struct xmit_buf {
struct list_head list;
struct adapter *padapter;
u8 *pallocated_buf;
u8 *pbuf;
void *priv_data;
u16 ext_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf. */
bool high_queue;
u32 alloc_sz;
u32 len;
struct submit_ctx *sctx;
struct urb *pxmit_urb;
int last[8];
};
struct xmit_frame {
struct list_head list;
struct pkt_attrib attrib;
struct sk_buff *pkt;
int frame_tag;
struct adapter *padapter;
u8 *buf_addr;
struct xmit_buf *pxmitbuf;
u8 agg_num;
s8 pkt_offset;
u8 ack_report;
};
struct tx_servq {
struct list_head tx_pending;
struct list_head sta_pending;
int qcnt;
};
struct sta_xmit_priv {
spinlock_t lock;
struct tx_servq be_q; /* priority == 0,3 */
struct tx_servq bk_q; /* priority == 1,2 */
struct tx_servq vi_q; /* priority == 4,5 */
struct tx_servq vo_q; /* priority == 6,7 */
u16 txseq_tid[16];
};
struct hw_txqueue {
volatile int head;
volatile int tail;
volatile int free_sz; /* in units of 64 bytes */
volatile int free_cmdsz;
volatile int txsz[8];
uint ff_hwaddr;
uint cmd_hwaddr;
int ac_tag;
};
struct xmit_priv {
spinlock_t lock;
struct list_head be_pending;
struct list_head bk_pending;
struct list_head vi_pending;
struct list_head vo_pending;
u8 *pallocated_frame_buf;
u8 *pxmit_frame_buf;
uint free_xmitframe_cnt;
struct __queue free_xmit_queue;
uint frag_len;
struct adapter *adapter;
u64 tx_bytes;
u64 tx_pkts;
u64 tx_drop;
u64 last_tx_bytes;
u64 last_tx_pkts;
struct hw_xmit *hwxmits;
u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength
* from large to small. it's value is 0->vo,
* 1->vi, 2->be, 3->bk. */
struct tasklet_struct xmit_tasklet;
struct __queue free_xmitbuf_queue;
struct __queue pending_xmitbuf_queue;
u8 *pallocated_xmitbuf;
u8 *pxmitbuf;
uint free_xmitbuf_cnt;
struct __queue free_xmit_extbuf_queue;
u8 *pallocated_xmit_extbuf;
u8 *pxmit_extbuf;
uint free_xmit_extbuf_cnt;
u16 nqos_ssn;
int ack_tx;
struct mutex ack_tx_mutex;
struct submit_ctx ack_tx_ops;
};
struct pkt_file {
struct sk_buff *pkt;
size_t pkt_len; /* the remainder length of the open_file */
unsigned char *cur_buffer;
u8 *buf_start;
u8 *cur_addr;
size_t buf_len;
};
struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);
s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv,
struct xmit_buf *pxmitbuf);
struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv,
struct xmit_buf *pxmitbuf);
void rtw_count_tx_stats(struct adapter *padapter,
struct xmit_frame *pxmitframe, int sz);
s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr,
struct pkt_attrib *pattrib);
s32 rtw_put_snap(u8 *data, u16 h_proto);
struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv);
s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv,
struct xmit_frame *pxmitframe);
void rtw_free_xmitframe_list(struct xmit_priv *pxmitpriv, struct list_head *xframe_list);
struct tx_servq *rtw_get_sta_pending(struct adapter *padapter,
struct sta_info *psta, int up, u8 *ac);
struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv,
struct hw_xmit *phwxmit_i);
s32 rtw_xmit_classifier(struct adapter *padapter,
struct xmit_frame *pxmitframe);
s32 rtw_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt,
struct xmit_frame *pxmitframe);
s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag);
void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
s32 rtw_txframes_pending(struct adapter *padapter);
s32 rtw_txframes_sta_ac_pending(struct adapter *padapter,
struct pkt_attrib *pattrib);
int _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter);
void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);
int rtw_alloc_hwxmits(struct adapter *padapter);
s32 rtw_xmit(struct adapter *padapter, struct sk_buff **pkt);
int xmitframe_enqueue_for_sleeping_sta(struct adapter *padapter, struct xmit_frame *pxmitframe);
void stop_sta_xmit(struct adapter *padapter, struct sta_info *psta);
void wakeup_sta_to_xmit(struct adapter *padapter, struct sta_info *psta);
void xmit_delivery_enabled_frames(struct adapter *padapter, struct sta_info *psta);
u8 qos_acm(u8 acm_mask, u8 priority);
u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe);
int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
void rtw_xmit_complete(struct adapter *padapter, struct xmit_frame *pxframe);
netdev_tx_t rtw_xmit_entry(struct sk_buff *pkt, struct net_device *pnetdev);
#endif /* _RTL871X_XMIT_H_ */

313
drivers/staging/r8188eu/include/sta_info.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __STA_INFO_H_
#define __STA_INFO_H_
#include "osdep_service.h"
#include "drv_types.h"
#include "wifi.h"
#define IBSS_START_MAC_ID 2
#define NUM_STA 32
#define NUM_ACL 16
/* if mode ==0, then the sta is allowed once the addr is hit. */
/* if mode ==1, then the sta is rejected once the addr is non-hit. */
struct rtw_wlan_acl_node {
struct list_head list;
u8 addr[ETH_ALEN];
u8 valid;
};
/* mode=0, disable */
/* mode=1, accept unless in deny list */
/* mode=2, deny unless in accept list */
struct wlan_acl_pool {
int mode;
int num;
struct rtw_wlan_acl_node aclnode[NUM_ACL];
struct __queue acl_node_q;
};
struct rssi_sta {
s32 UndecoratedSmoothedPWDB;
s32 UndecoratedSmoothedCCK;
s32 UndecoratedSmoothedOFDM;
u64 PacketMap;
u8 ValidBit;
};
struct stainfo_stats {
u64 rx_mgnt_pkts;
u64 rx_beacon_pkts;
u64 rx_probereq_pkts;
u64 rx_probersp_pkts;
u64 rx_probersp_bm_pkts;
u64 rx_probersp_uo_pkts;
u64 rx_ctrl_pkts;
u64 rx_data_pkts;
u64 last_rx_beacon_pkts;
u64 last_rx_probereq_pkts;
u64 last_rx_probersp_pkts;
u64 last_rx_probersp_bm_pkts;
u64 last_rx_probersp_uo_pkts;
u64 last_rx_ctrl_pkts;
u64 last_rx_data_pkts;
u64 rx_bytes;
u64 rx_drops;
u64 tx_pkts;
u64 tx_bytes;
u64 tx_drops;
};
struct sta_info {
spinlock_t lock;
struct list_head list; /* free_sta_queue */
struct list_head hash_list; /* sta_hash */
struct sta_xmit_priv sta_xmitpriv;
struct sta_recv_priv sta_recvpriv;
struct __queue sleep_q;
unsigned int sleepq_len;
uint state;
uint aid;
uint mac_id;
uint qos_option;
u8 hwaddr[ETH_ALEN];
uint ieee8021x_blocked; /* 0: allowed, 1:blocked */
uint dot118021XPrivacy; /* aes, tkip... */
union Keytype dot11tkiptxmickey;
union Keytype dot11tkiprxmickey;
union Keytype dot118021x_UncstKey;
union pn48 dot11txpn; /* PN48 used for Unicast xmit. */
union pn48 dot11rxpn; /* PN48 used for Unicast recv. */
u8 bssrateset[16];
u32 bssratelen;
s32 rssi;
s32 signal_quality;
u8 cts2self;
u8 rtsen;
u8 raid;
u8 init_rate;
u32 ra_mask;
u8 wireless_mode; /* NETWORK_TYPE */
struct stainfo_stats sta_stats;
/* for A-MPDU TX, ADDBA timeout check */
struct timer_list addba_retry_timer;
/* for A-MPDU Rx reordering buffer control */
struct recv_reorder_ctrl recvreorder_ctrl[16];
/* for A-MPDU Tx */
/* unsigned char ampdu_txen_bitmap; */
u16 BA_starting_seqctrl[16];
struct ht_priv htpriv;
/* Notes: */
/* STA_Mode: */
/* curr_network(mlme_priv/security_priv/qos/ht) +
* sta_info: (STA & AP) CAP/INFO */
/* scan_q: AP CAP/INFO */
/* AP_Mode: */
/* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */
/* sta_info: (AP & STA) CAP/INFO */
struct list_head asoc_list;
struct list_head auth_list;
unsigned int expire_to;
unsigned int auth_seq;
unsigned int authalg;
unsigned char chg_txt[128];
u16 capability;
int flags;
int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
int wpa_group_cipher;
int wpa2_group_cipher;
int wpa_pairwise_cipher;
int wpa2_pairwise_cipher;
u8 bpairwise_key_installed;
u8 wpa_ie[32];
u8 nonerp_set;
u8 no_short_slot_time_set;
u8 no_short_preamble_set;
u8 no_ht_gf_set;
u8 no_ht_set;
u8 ht_20mhz_set;
unsigned int tx_ra_bitmap;
u8 qos_info;
u8 max_sp_len;
u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */
u8 uapsd_be;
u8 uapsd_vi;
u8 uapsd_vo;
u8 has_legacy_ac;
unsigned int sleepq_ac_len;
/* p2p priv data */
u8 is_p2p_device;
u8 p2p_status_code;
/* p2p client info */
u8 dev_addr[ETH_ALEN];
u8 dev_cap;
u16 config_methods;
u8 primary_dev_type[8];
u8 num_of_secdev_type;
u8 secdev_types_list[32];/* 32/8 == 4; */
u16 dev_name_len;
u8 dev_name[32];
u8 under_exist_checking;
u8 keep_alive_trycnt;
/* for DM */
struct rssi_sta rssi_stat;
/* ================ODM Relative Info======================= */
/* Please be careful, don't declare too much structure here.
* It will cost memory * STA support num. */
/* 2011/10/20 MH Add for ODM STA info. */
/* Driver Write */
u8 bValid; /* record the sta status link or not? */
u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
u8 rssi_level; /* for Refresh RA mask */
/* ODM Write */
/* 1 PHY_STATUS_INFO */
u8 RSSI_Path[4]; /* */
u8 RSSI_Ave;
u8 RXEVM[4];
u8 RXSNR[4];
/* ================ODM Relative Info======================= */
/* */
/* To store the sequence number of received management frame */
u16 RxMgmtFrameSeqNum;
};
#define sta_rx_pkts(sta) \
(sta->sta_stats.rx_mgnt_pkts \
+ sta->sta_stats.rx_ctrl_pkts \
+ sta->sta_stats.rx_data_pkts)
#define sta_rx_data_pkts(sta) \
(sta->sta_stats.rx_data_pkts)
#define sta_last_rx_data_pkts(sta) \
(sta->sta_stats.last_rx_data_pkts)
#define sta_rx_beacon_pkts(sta) \
(sta->sta_stats.rx_beacon_pkts)
#define sta_last_rx_beacon_pkts(sta) \
(sta->sta_stats.last_rx_beacon_pkts)
#define sta_rx_probersp_pkts(sta) \
(sta->sta_stats.rx_probersp_pkts)
#define sta_last_rx_probersp_pkts(sta) \
(sta->sta_stats.last_rx_probersp_pkts)
#define sta_update_last_rx_pkts(sta) \
do { \
sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \
sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \
sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \
sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \
sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \
sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
} while (0)
struct sta_priv {
u8 *pallocated_stainfo_buf;
u8 *pstainfo_buf;
struct __queue free_sta_queue;
spinlock_t sta_hash_lock;
struct list_head sta_hash[NUM_STA];
int asoc_sta_count;
struct __queue sleep_q;
struct __queue wakeup_q;
struct adapter *padapter;
spinlock_t asoc_list_lock;
struct list_head asoc_list;
struct list_head auth_list;
spinlock_t auth_list_lock;
u8 asoc_list_cnt;
u8 auth_list_cnt;
unsigned int auth_to; /* sec, time to expire in authenticating. */
unsigned int assoc_to; /* sec, time to expire before associating. */
unsigned int expire_to; /* sec , time to expire after associated. */
/* pointers to STA info; based on allocated AID or NULL if AID free
* AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
* and so on
*/
struct sta_info *sta_aid[NUM_STA];
u16 sta_dz_bitmap;/* only support 15 stations, station aid bitmap
* for sleeping sta. */
u16 tim_bitmap; /* only support 15 stations, aid=0~15 mapping
* bit0~bit15 */
u16 max_num_sta;
struct wlan_acl_pool acl_list;
};
static inline u32 wifi_mac_hash(u8 *mac)
{
u32 x;
x = mac[0];
x = (x << 2) ^ mac[1];
x = (x << 2) ^ mac[2];
x = (x << 2) ^ mac[3];
x = (x << 2) ^ mac[4];
x = (x << 2) ^ mac[5];
x ^= x >> 8;
x = x & (NUM_STA - 1);
return x;
}
int _rtw_init_sta_priv(struct sta_priv *pstapriv);
void _rtw_free_sta_priv(struct sta_priv *pstapriv);
#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0)
int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta);
struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int off);
struct sta_info *rtw_alloc_stainfo(struct sta_priv *stapriv, u8 *hwaddr);
void rtw_free_stainfo(struct adapter *adapt, struct sta_info *psta);
void rtw_free_all_stainfo(struct adapter *adapt);
struct sta_info *rtw_get_stainfo(struct sta_priv *stapriv, u8 *hwaddr);
u32 rtw_init_bcmc_stainfo(struct adapter *adapt);
struct sta_info *rtw_get_bcmc_stainfo(struct adapter *padapter);
u8 rtw_access_ctrl(struct adapter *padapter, u8 *mac_addr);
#endif /* _STA_INFO_H_ */

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drivers/staging/r8188eu/include/usb_ops.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __USB_OPS_H_
#define __USB_OPS_H_
#include "osdep_service.h"
#include "drv_types.h"
#include "osdep_intf.h"
#define REALTEK_USB_VENQT_READ (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
#define REALTEK_USB_VENQT_WRITE (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
#define REALTEK_USB_VENQT_CMD_REQ 0x05
#define REALTEK_USB_VENQT_CMD_IDX 0x00
#define ALIGNMENT_UNIT 16
#define MAX_VENDOR_REQ_CMD_SIZE 254 /* 8188cu SIE Support */
#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT)
/*
* Increase and check if the continual_urb_error of this @param dvobjprivei
* is larger than MAX_CONTINUAL_URB_ERR
* @return true:
* @return false:
*/
static inline bool rtw_inc_and_chk_continual_urb_error(struct dvobj_priv *dvobj)
{
int value = atomic_inc_return(&dvobj->continual_urb_error);
if (value > MAX_CONTINUAL_URB_ERR)
return true;
return false;
}
/*
* Set the continual_urb_error of this @param dvobjprive to 0
*/
static inline void rtw_reset_continual_urb_error(struct dvobj_priv *dvobj)
{
atomic_set(&dvobj->continual_urb_error, 0);
}
#define USB_HIGH_SPEED_BULK_SIZE 512
#define USB_FULL_SPEED_BULK_SIZE 64
static inline bool rtw_usb_bulk_size_boundary(struct adapter *padapter, int buf_len)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
if (pdvobjpriv->pusbdev->speed == USB_SPEED_HIGH)
return buf_len % USB_HIGH_SPEED_BULK_SIZE == 0;
else
return buf_len % USB_FULL_SPEED_BULK_SIZE == 0;
}
#endif /* __USB_OPS_H_ */

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drivers/staging/r8188eu/include/usb_osintf.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __USB_OSINTF_H
#define __USB_OSINTF_H
#include "osdep_service.h"
#include "drv_types.h"
extern char *rtw_initmac;
extern int rtw_mc2u_disable;
#define USBD_HALTED(Status) ((u32)(Status) >> 30 == 3)
void netdev_br_init(struct net_device *netdev);
void dhcp_flag_bcast(struct adapter *priv, struct sk_buff *skb);
void *scdb_findEntry(struct adapter *priv, unsigned char *ipAddr);
void nat25_db_expire(struct adapter *priv);
int nat25_db_handle(struct adapter *priv, struct sk_buff *skb, int method);
#endif

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drivers/staging/r8188eu/include/wifi.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#ifndef _WIFI_H_
#define _WIFI_H_
#include <linux/bits.h>
#include <linux/ieee80211.h>
#define WLAN_ETHHDR_LEN 14
#define WLAN_HDR_A3_LEN 24
#define WLAN_HDR_A3_QOS_LEN 26
#define WLAN_SSID_MAXLEN 32
enum WIFI_FRAME_SUBTYPE {
/* below is for mgt frame */
WIFI_ASSOCREQ = (0 | IEEE80211_FTYPE_MGMT),
WIFI_ASSOCRSP = (BIT(4) | IEEE80211_FTYPE_MGMT),
WIFI_REASSOCREQ = (BIT(5) | IEEE80211_FTYPE_MGMT),
WIFI_REASSOCRSP = (BIT(5) | BIT(4) | IEEE80211_FTYPE_MGMT),
WIFI_PROBEREQ = (BIT(6) | IEEE80211_FTYPE_MGMT),
WIFI_PROBERSP = (BIT(6) | BIT(4) | IEEE80211_FTYPE_MGMT),
WIFI_BEACON = (BIT(7) | IEEE80211_FTYPE_MGMT),
WIFI_ATIM = (BIT(7) | BIT(4) | IEEE80211_FTYPE_MGMT),
WIFI_DISASSOC = (BIT(7) | BIT(5) | IEEE80211_FTYPE_MGMT),
WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | IEEE80211_FTYPE_MGMT),
WIFI_DEAUTH = (BIT(7) | BIT(6) | IEEE80211_FTYPE_MGMT),
WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | IEEE80211_FTYPE_MGMT),
/* below is for control frame */
WIFI_PSPOLL = (BIT(7) | BIT(5) | IEEE80211_FTYPE_CTL),
/* below is for data frame */
WIFI_DATA = (0 | IEEE80211_FTYPE_DATA),
WIFI_DATA_CFACK = (BIT(4) | IEEE80211_FTYPE_DATA),
WIFI_DATA_CFPOLL = (BIT(5) | IEEE80211_FTYPE_DATA),
WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | IEEE80211_FTYPE_DATA),
WIFI_DATA_NULL = (BIT(6) | IEEE80211_FTYPE_DATA),
WIFI_QOS_DATA_NULL = (BIT(6) | IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA),
};
enum WIFI_REASON_CODE {
_RSON_RESERVED_ = 0,
_RSON_UNSPECIFIED_ = 1,
_RSON_AUTH_NO_LONGER_VALID_ = 2,
_RSON_DEAUTH_STA_LEAVING_ = 3,
_RSON_INACTIVITY_ = 4,
_RSON_UNABLE_HANDLE_ = 5,
_RSON_CLS2_ = 6,
_RSON_CLS3_ = 7,
_RSON_DISAOC_STA_LEAVING_ = 8,
_RSON_ASOC_NOT_AUTH_ = 9,
/* WPA reason */
_RSON_INVALID_IE_ = 13,
_RSON_MIC_FAILURE_ = 14,
_RSON_4WAY_HNDSHK_TIMEOUT_ = 15,
_RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16,
_RSON_DIFF_IE_ = 17,
_RSON_MLTCST_CIPHER_NOT_VALID_ = 18,
_RSON_UNICST_CIPHER_NOT_VALID_ = 19,
_RSON_AKMP_NOT_VALID_ = 20,
_RSON_UNSUPPORT_RSNE_VER_ = 21,
_RSON_INVALID_RSNE_CAP_ = 22,
_RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23,
/* belowing are Realtek definition */
_RSON_PMK_NOT_AVAILABLE_ = 24,
_RSON_TDLS_TEAR_TOOFAR_ = 25,
_RSON_TDLS_TEAR_UN_RSN_ = 26,
};
enum WIFI_STATUS_CODE {
_STATS_SUCCESSFUL_ = 0,
_STATS_FAILURE_ = 1,
_STATS_CAP_FAIL_ = 10,
_STATS_NO_ASOC_ = 11,
_STATS_OTHER_ = 12,
_STATS_NO_SUPP_ALG_ = 13,
_STATS_OUT_OF_AUTH_SEQ_ = 14,
_STATS_CHALLENGE_FAIL_ = 15,
_STATS_AUTH_TIMEOUT_ = 16,
_STATS_UNABLE_HANDLE_STA_ = 17,
_STATS_RATE_FAIL_ = 18,
};
/* entended */
/* IEEE 802.11b */
#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
/* IEEE 802.11h */
#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22
#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23
#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24
/* IEEE 802.11g */
#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25
#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26
#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27
/* IEEE 802.11w */
#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30
#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31
/* IEEE 802.11i */
#define WLAN_STATUS_INVALID_IE 40
#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41
#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42
#define WLAN_STATUS_AKMP_NOT_VALID 43
#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44
#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45
#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46
#define WLAN_STATUS_TS_NOT_CREATED 47
#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48
#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49
#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50
#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51
/* IEEE 802.11r */
#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52
#define WLAN_STATUS_INVALID_PMKID 53
#define WLAN_STATUS_INVALID_MDIE 54
#define WLAN_STATUS_INVALID_FTIE 55
enum WIFI_REG_DOMAIN {
DOMAIN_FCC = 1,
DOMAIN_IC = 2,
DOMAIN_ETSI = 3,
DOMAIN_SPA = 4,
DOMAIN_FRANCE = 5,
DOMAIN_MKK = 6,
DOMAIN_ISRAEL = 7,
DOMAIN_MKK1 = 8,
DOMAIN_MKK2 = 9,
DOMAIN_MKK3 = 10,
DOMAIN_MAX
};
#define _TO_DS_ BIT(8)
#define _FROM_DS_ BIT(9)
#define _MORE_FRAG_ BIT(10)
#define _RETRY_ BIT(11)
#define _PWRMGT_ BIT(12)
#define _MORE_DATA_ BIT(13)
#define _PRIVACY_ BIT(14)
#define SetToDs(pbuf) \
*(__le16 *)(pbuf) |= cpu_to_le16(_TO_DS_)
#define GetToDs(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_TO_DS_)) != 0)
#define SetFrDs(pbuf) \
*(__le16 *)(pbuf) |= cpu_to_le16(_FROM_DS_)
#define GetFrDs(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_FROM_DS_)) != 0)
#define SetMFrag(pbuf) \
*(__le16 *)(pbuf) |= cpu_to_le16(_MORE_FRAG_)
#define ClearMFrag(pbuf) \
*(__le16 *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_))
#define GetRetry(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_RETRY_)) != 0)
#define SetPwrMgt(pbuf) \
*(__le16 *)(pbuf) |= cpu_to_le16(_PWRMGT_)
#define GetPwrMgt(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_PWRMGT_)) != 0)
#define SetMData(pbuf) \
*(__le16 *)(pbuf) |= cpu_to_le16(_MORE_DATA_)
#define SetPrivacy(pbuf) \
*(__le16 *)(pbuf) |= cpu_to_le16(_PRIVACY_)
#define GetFrameType(pbuf) \
(le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(3) | BIT(2)))
#define GetFrameSubType(pbuf) (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(7) |\
BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2)))
#define SetFrameSubType(pbuf, type) \
do { \
*(__le16 *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | \
BIT(5) | BIT(4) | BIT(3) | BIT(2))); \
*(__le16 *)(pbuf) |= cpu_to_le16(type); \
} while (0)
#define SetSeqNum(pbuf, num) \
do { \
*(__le16 *)((size_t)(pbuf) + 22) = \
((*(__le16 *)((size_t)(pbuf) + 22)) & cpu_to_le16((unsigned short)0x000f)) | \
cpu_to_le16((unsigned short)(0xfff0 & (num << 4))); \
} while (0)
#define SetDuration(pbuf, dur) \
*(__le16 *)((size_t)(pbuf) + 2) = cpu_to_le16(0xffff & (dur))
#define SetPriority(pbuf, tid) \
*(__le16 *)(pbuf) |= cpu_to_le16(tid & 0xf)
#define SetEOSP(pbuf, eosp) \
*(__le16 *)(pbuf) |= cpu_to_le16((eosp & 1) << 4)
#define SetAckpolicy(pbuf, ack) \
*(__le16 *)(pbuf) |= cpu_to_le16((ack & 3) << 5)
#define GetAckpolicy(pbuf) (((le16_to_cpu(*(__le16 *)pbuf)) >> 5) & 0x3)
#define GetAMsdu(pbuf) (((le16_to_cpu(*(__le16 *)pbuf)) >> 7) & 0x1)
#define GetAddr1Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 4))
#define GetAddr2Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 10))
#define GetAddr3Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 16))
#define GetAddr4Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 24))
static inline unsigned char *get_sa(unsigned char *pframe)
{
unsigned char *sa;
unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe);
switch (to_fr_ds) {
case 0x00: /* ToDs=0, FromDs=0 */
sa = GetAddr2Ptr(pframe);
break;
case 0x01: /* ToDs=0, FromDs=1 */
sa = GetAddr3Ptr(pframe);
break;
case 0x02: /* ToDs=1, FromDs=0 */
sa = GetAddr2Ptr(pframe);
break;
default: /* ToDs=1, FromDs=1 */
sa = GetAddr4Ptr(pframe);
break;
}
return sa;
}
static inline unsigned char *get_hdr_bssid(unsigned char *pframe)
{
unsigned char *sa;
unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe);
switch (to_fr_ds) {
case 0x00: /* ToDs=0, FromDs=0 */
sa = GetAddr3Ptr(pframe);
break;
case 0x01: /* ToDs=0, FromDs=1 */
sa = GetAddr2Ptr(pframe);
break;
case 0x02: /* ToDs=1, FromDs=0 */
sa = GetAddr1Ptr(pframe);
break;
case 0x03: /* ToDs=1, FromDs=1 */
sa = GetAddr1Ptr(pframe);
break;
default:
sa = NULL; /* */
break;
}
return sa;
}
/*-----------------------------------------------------------------------------
Below is for the security related definition
------------------------------------------------------------------------------*/
#define _RESERVED_FRAME_TYPE_ 0
#define _SKB_FRAME_TYPE_ 2
#define _PRE_ALLOCMEM_ 1
#define _PRE_ALLOCHDR_ 3
#define _PRE_ALLOCLLCHDR_ 4
#define _PRE_ALLOCICVHDR_ 5
#define _PRE_ALLOCMICHDR_ 6
#define _SIFSTIME_ \
(priv->pmib->dot11BssType.net_work_type = 10)
#define _ACKCTSLNG_ 14 /* 14 bytes long, including crclng */
#define _CRCLNG_ 4
#define _ASOCREQ_IE_OFFSET_ 4 /* excluding wlan_hdr */
#define _ASOCRSP_IE_OFFSET_ 6
#define _REASOCREQ_IE_OFFSET_ 10
#define _REASOCRSP_IE_OFFSET_ 6
#define _PROBEREQ_IE_OFFSET_ 0
#define _PROBERSP_IE_OFFSET_ 12
#define _AUTH_IE_OFFSET_ 6
#define _DEAUTH_IE_OFFSET_ 0
#define _BEACON_IE_OFFSET_ 12
#define _PUBLIC_ACTION_IE_OFFSET_ 8
#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_
#define _SSID_IE_ 0
#define _SUPPORTEDRATES_IE_ 1
#define _DSSET_IE_ 3
#define _TIM_IE_ 5
#define _IBSS_PARA_IE_ 6
#define _COUNTRY_IE_ 7
#define _CHLGETXT_IE_ 16
#define _SUPPORTED_CH_IE_ 36
#define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */
#define _RSN_IE_2_ 48
#define _SSN_IE_1_ 221
#define _ERPINFO_IE_ 42
#define _EXT_SUPPORTEDRATES_IE_ 50
#define _HT_CAPABILITY_IE_ 45
#define _FTIE_ 55
#define _TIMEOUT_ITVL_IE_ 56
#define _SRC_IE_ 59
#define _HT_EXTRA_INFO_IE_ 61
#define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */
#define _WAPI_IE_ 68
#define EID_BSSCoexistence 72 /* 20/40 BSS Coexistence */
#define EID_BSSIntolerantChlReport 73
#define _RIC_Descriptor_IE_ 75
#define _LINK_ID_IE_ 101
#define _CH_SWITCH_TIMING_ 104
#define _PTI_BUFFER_STATUS_ 106
#define _EXT_CAP_IE_ 127
#define _VENDOR_SPECIFIC_IE_ 221
#define _RESERVED47_ 47
/* ---------------------------------------------------------------------------
Below is the fixed elements...
-----------------------------------------------------------------------------*/
#define _AUTH_ALGM_NUM_ 2
#define _AUTH_SEQ_NUM_ 2
#define _BEACON_ITERVAL_ 2
#define _CAPABILITY_ 2
#define _CURRENT_APADDR_ 6
#define _LISTEN_INTERVAL_ 2
#define _RSON_CODE_ 2
#define _ASOC_ID_ 2
#define _STATUS_CODE_ 2
#define _TIMESTAMP_ 8
#define cap_ESS BIT(0)
#define cap_IBSS BIT(1)
#define cap_CFPollable BIT(2)
#define cap_CFRequest BIT(3)
#define cap_Privacy BIT(4)
#define cap_ShortPremble BIT(5)
#define cap_PBCC BIT(6)
#define cap_ChAgility BIT(7)
#define cap_SpecMgmt BIT(8)
#define cap_QoSi BIT(9)
#define cap_ShortSlot BIT(10)
/*-----------------------------------------------------------------------------
Below is the definition for 802.11i / 802.1x
------------------------------------------------------------------------------*/
#define _IEEE8021X_MGT_ 1 /* WPA */
#define _IEEE8021X_PSK_ 2 /* WPA with pre-shared key */
/*-----------------------------------------------------------------------------
Below is the definition for WMM
------------------------------------------------------------------------------*/
#define _WMM_IE_Length_ 7 /* for WMM STA */
#define _WMM_Para_Element_Length_ 24
/*-----------------------------------------------------------------------------
Below is the definition for 802.11n
------------------------------------------------------------------------------*/
/**
* struct rtw_ieee80211_bar - HT Block Ack Request
*
* This structure refers to "HT BlockAckReq" as
* described in 802.11n draft section 7.2.1.7.1
*/
struct rtw_ieee80211_bar {
__le16 frame_control;
__le16 duration;
unsigned char ra[ETH_ALEN];
unsigned char ta[ETH_ALEN];
__le16 control;
__le16 start_seq_num;
} __packed;
/**
* struct ieee80211_ht_cap - HT additional information
*
* This structure refers to "HT information element" as
* described in 802.11n draft section 7.3.2.53
*/
struct ieee80211_ht_addt_info {
unsigned char control_chan;
unsigned char ht_param;
__le16 operation_mode;
__le16 stbc_param;
unsigned char basic_set[16];
} __packed;
struct HT_caps_element {
union {
struct {
__le16 HT_caps_info;
unsigned char AMPDU_para;
unsigned char MCS_rate[16];
__le16 HT_ext_caps;
__le16 Beamforming_caps;
unsigned char ASEL_caps;
} HT_cap_element;
unsigned char HT_cap[26];
} u;
} __packed;
struct HT_info_element {
unsigned char primary_channel;
unsigned char infos[5];
unsigned char MCS_rate[16];
} __packed;
struct AC_param {
unsigned char ACI_AIFSN;
unsigned char CW;
__le16 TXOP_limit;
} __packed;
struct WMM_para_element {
unsigned char QoS_info;
unsigned char reserved;
struct AC_param ac_param[4];
} __packed;
#define MAX_AMPDU_FACTOR_64K 3
/* Spatial Multiplexing Power Save Modes */
#define WLAN_HT_CAP_SM_PS_STATIC 0
#define WLAN_HT_CAP_SM_PS_DYNAMIC 1
#define WLAN_HT_CAP_SM_PS_INVALID 2
#define WLAN_HT_CAP_SM_PS_DISABLED 3
#define OP_MODE_PURE 0
#define OP_MODE_MAY_BE_LEGACY_STAS 1
#define OP_MODE_20MHZ_HT_STA_ASSOCED 2
#define OP_MODE_MIXED 3
#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1))
#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0))
#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1))
#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2))
#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3))
#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4))
#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5))
#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \
((u16) (0x0001 | 0x0002))
#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0
#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2))
#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3))
#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4))
/* ===============WPS Section=============== */
/* For WPSv1.0 */
#define WPSOUI 0x0050f204
/* WPS attribute ID */
#define WPS_ATTR_VER1 0x104A
#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044
#define WPS_ATTR_RESP_TYPE 0x103B
#define WPS_ATTR_UUID_E 0x1047
#define WPS_ATTR_MANUFACTURER 0x1021
#define WPS_ATTR_MODEL_NAME 0x1023
#define WPS_ATTR_MODEL_NUMBER 0x1024
#define WPS_ATTR_SERIAL_NUMBER 0x1042
#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054
#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055
#define WPS_ATTR_DEVICE_NAME 0x1011
#define WPS_ATTR_CONF_METHOD 0x1008
#define WPS_ATTR_RF_BANDS 0x103C
#define WPS_ATTR_DEVICE_PWID 0x1012
#define WPS_ATTR_REQUEST_TYPE 0x103A
#define WPS_ATTR_ASSOCIATION_STATE 0x1002
#define WPS_ATTR_CONFIG_ERROR 0x1009
#define WPS_ATTR_VENDOR_EXT 0x1049
#define WPS_ATTR_SELECTED_REGISTRAR 0x1041
/* Value of WPS attribute "WPS_ATTR_DEVICE_NAME */
#define WPS_MAX_DEVICE_NAME_LEN 32
/* Value of WPS Request Type Attribute */
#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00
#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01
#define WPS_REQ_TYPE_REGISTRAR 0x02
#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03
/* Value of WPS Response Type Attribute */
#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00
#define WPS_RESPONSE_TYPE_8021X 0x01
#define WPS_RESPONSE_TYPE_REGISTRAR 0x02
#define WPS_RESPONSE_TYPE_AP 0x03
/* Value of WPS WiFi Simple Configuration State Attribute */
#define WPS_WSC_STATE_NOT_CONFIG 0x01
#define WPS_WSC_STATE_CONFIG 0x02
/* Value of WPS Version Attribute */
#define WPS_VERSION_1 0x10
/* Value of WPS Configuration Method Attribute */
#define WPS_CONFIG_METHOD_FLASH 0x0001
#define WPS_CONFIG_METHOD_ETHERNET 0x0002
#define WPS_CONFIG_METHOD_LABEL 0x0004
#define WPS_CONFIG_METHOD_DISPLAY 0x0008
#define WPS_CONFIG_METHOD_E_NFC 0x0010
#define WPS_CONFIG_METHOD_I_NFC 0x0020
#define WPS_CONFIG_METHOD_NFC 0x0040
#define WPS_CONFIG_METHOD_PBC 0x0080
#define WPS_CONFIG_METHOD_KEYPAD 0x0100
#define WPS_CONFIG_METHOD_VPBC 0x0280
#define WPS_CONFIG_METHOD_PPBC 0x0480
#define WPS_CONFIG_METHOD_VDISPLAY 0x2008
#define WPS_CONFIG_METHOD_PDISPLAY 0x4008
/* Value of Category ID of WPS Primary Device Type Attribute */
#define WPS_PDT_CID_DISPLAYS 0x0007
#define WPS_PDT_CID_MULIT_MEDIA 0x0008
#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA
/* Value of Sub Category ID of WPS Primary Device Type Attribute */
#define WPS_PDT_SCID_MEDIA_SERVER 0x0005
#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER
/* Value of Device Password ID */
#define WPS_DPID_P 0x0000
#define WPS_DPID_USER_SPEC 0x0001
#define WPS_DPID_MACHINE_SPEC 0x0002
#define WPS_DPID_REKEY 0x0003
#define WPS_DPID_PBC 0x0004
#define WPS_DPID_REGISTRAR_SPEC 0x0005
/* Value of WPS RF Bands Attribute */
#define WPS_RF_BANDS_2_4_GHZ 0x01
#define WPS_RF_BANDS_5_GHZ 0x02
/* Value of WPS Association State Attribute */
#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00
#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01
#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02
#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03
#define WPS_ASSOC_STATE_IP_FAILURE 0x04
/* =====================P2P Section===================== */
/* For P2P */
#define P2POUI 0x506F9A09
/* P2P Attribute ID */
#define P2P_ATTR_STATUS 0x00
#define P2P_ATTR_MINOR_REASON_CODE 0x01
#define P2P_ATTR_CAPABILITY 0x02
#define P2P_ATTR_DEVICE_ID 0x03
#define P2P_ATTR_GO_INTENT 0x04
#define P2P_ATTR_CONF_TIMEOUT 0x05
#define P2P_ATTR_LISTEN_CH 0x06
#define P2P_ATTR_GROUP_BSSID 0x07
#define P2P_ATTR_EX_LISTEN_TIMING 0x08
#define P2P_ATTR_INTENTED_IF_ADDR 0x09
#define P2P_ATTR_MANAGEABILITY 0x0A
#define P2P_ATTR_CH_LIST 0x0B
#define P2P_ATTR_NOA 0x0C
#define P2P_ATTR_DEVICE_INFO 0x0D
#define P2P_ATTR_GROUP_INFO 0x0E
#define P2P_ATTR_GROUP_ID 0x0F
#define P2P_ATTR_INTERFACE 0x10
#define P2P_ATTR_OPERATING_CH 0x11
#define P2P_ATTR_INVITATION_FLAGS 0x12
/* Value of Status Attribute */
#define P2P_STATUS_SUCCESS 0x00
#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01
#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02
#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03
#define P2P_STATUS_FAIL_INVALID_PARAM 0x04
#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05
#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06
#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07
#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08
#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09
#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A
#define P2P_STATUS_FAIL_USER_REJECT 0x0B
/* Value of Inviation Flags Attribute */
#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0)
#define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \
P2P_DEVCAP_CLIENT_DISCOVERABILITY | \
P2P_DEVCAP_CONCURRENT_OPERATION | \
P2P_DEVCAP_INVITATION_PROC)
#define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS)
/* Value of Device Capability Bitmap */
#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0)
#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1)
#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2)
#define P2P_DEVCAP_INFRA_MANAGED BIT(3)
#define P2P_DEVCAP_DEVICE_LIMIT BIT(4)
#define P2P_DEVCAP_INVITATION_PROC BIT(5)
/* Value of Group Capability Bitmap */
#define P2P_GRPCAP_GO BIT(0)
#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1)
#define P2P_GRPCAP_GROUP_LIMIT BIT(2)
#define P2P_GRPCAP_INTRABSS BIT(3)
#define P2P_GRPCAP_CROSS_CONN BIT(4)
#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5)
#define P2P_GRPCAP_GROUP_FORMATION BIT(6)
/* P2P Public Action Frame (Management Frame) */
#define P2P_PUB_ACTION_ACTION 0x09
/* P2P Public Action Frame Type */
#define P2P_GO_NEGO_REQ 0
#define P2P_GO_NEGO_RESP 1
#define P2P_GO_NEGO_CONF 2
#define P2P_INVIT_REQ 3
#define P2P_INVIT_RESP 4
#define P2P_DEVDISC_REQ 5
#define P2P_DEVDISC_RESP 6
#define P2P_PROVISION_DISC_REQ 7
#define P2P_PROVISION_DISC_RESP 8
/* P2P Action Frame Type */
#define P2P_NOTICE_OF_ABSENCE 0
#define P2P_PRESENCE_REQUEST 1
#define P2P_PRESENCE_RESPONSE 2
#define P2P_GO_DISC_REQUEST 3
#define P2P_MAX_PERSISTENT_GROUP_NUM 10
#define P2P_PROVISIONING_SCAN_CNT 3
#define P2P_WILDCARD_SSID_LEN 7
/* default value, used when: (1)p2p disabled or (2)p2p enabled
* but only do 1 scan phase */
#define P2P_FINDPHASE_EX_NONE 0
/* used when p2p enabled and want to do 1 scan phase and
* P2P_FINDPHASE_EX_MAX-1 find phase */
#define P2P_FINDPHASE_EX_FULL 1
#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1)
#define P2P_FINDPHASE_EX_MAX 4
#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX
/* 5 seconds timeout for sending the provision discovery request */
#define P2P_PROVISION_TIMEOUT 5000
/* 3 seconds timeout for sending the prov disc request concurrent mode */
#define P2P_CONCURRENT_PROVISION_TIME 3000
/* 5 seconds timeout for receiving the group negotiation response */
#define P2P_GO_NEGO_TIMEOUT 5000
/* 3 seconds timeout for sending the negotiation request under concurrent mode */
#define P2P_CONCURRENT_GO_NEGO_TIME 3000
/* 100ms */
#define P2P_TX_PRESCAN_TIMEOUT 100
/* 5 seconds timeout for sending the invitation request */
#define P2P_INVITE_TIMEOUT 5000
/* 3 seconds timeout for sending the invitation request under concurrent mode */
#define P2P_CONCURRENT_INVITE_TIME 3000
/* 25 seconds timeout to reset the scan channel (based on channel plan) */
#define P2P_RESET_SCAN_CH 25000
#define P2P_MAX_INTENT 15
#define P2P_MAX_NOA_NUM 2
/* WPS Configuration Method */
#define WPS_CM_NONE 0x0000
#define WPS_CM_LABEL 0x0004
#define WPS_CM_DISPLYA 0x0008
#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010
#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020
#define WPS_CM_NFC_INTERFACE 0x0040
#define WPS_CM_PUSH_BUTTON 0x0080
#define WPS_CM_KEYPAD 0x0100
#define WPS_CM_SW_PUHS_BUTTON 0x0280
#define WPS_CM_HW_PUHS_BUTTON 0x0480
#define WPS_CM_SW_DISPLAY_P 0x2008
#define WPS_CM_LCD_DISPLAY_P 0x4008
enum P2P_ROLE {
P2P_ROLE_DISABLE = 0,
P2P_ROLE_DEVICE = 1,
P2P_ROLE_CLIENT = 2,
P2P_ROLE_GO = 3
};
enum P2P_STATE {
P2P_STATE_NONE = 0, /* P2P disable */
/* P2P had enabled and do nothing */
P2P_STATE_IDLE = 1,
P2P_STATE_LISTEN = 2, /* In pure listen state */
P2P_STATE_SCAN = 3, /* In scan phase */
/* In the listen state of find phase */
P2P_STATE_FIND_PHASE_LISTEN = 4,
/* In the search state of find phase */
P2P_STATE_FIND_PHASE_SEARCH = 5,
/* In P2P provisioning discovery */
P2P_STATE_TX_PROVISION_DIS_REQ = 6,
P2P_STATE_RX_PROVISION_DIS_RSP = 7,
P2P_STATE_RX_PROVISION_DIS_REQ = 8,
/* Doing the group owner negotiation handshake */
P2P_STATE_GONEGO_ING = 9,
/* finish the group negotiation handshake with success */
P2P_STATE_GONEGO_OK = 10,
/* finish the group negotiation handshake with failure */
P2P_STATE_GONEGO_FAIL = 11,
/* receiving the P2P Inviation request and match with the profile. */
P2P_STATE_RECV_INVITE_REQ_MATCH = 12,
/* Doing the P2P WPS */
P2P_STATE_PROVISIONING_ING = 13,
/* Finish the P2P WPS */
P2P_STATE_PROVISIONING_DONE = 14,
/* Transmit the P2P Invitation request */
P2P_STATE_TX_INVITE_REQ = 15,
/* Receiving the P2P Invitation response */
P2P_STATE_RX_INVITE_RESP_OK = 16,
/* receiving the P2P Inviation request and dismatch with the profile. */
P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17,
/* receiving the P2P Inviation request and this wifi is GO. */
P2P_STATE_RECV_INVITE_REQ_GO = 18,
/* receiving the P2P Inviation request to join an existing P2P Group. */
P2P_STATE_RECV_INVITE_REQ_JOIN = 19,
/* recveing the P2P Inviation response with failure */
P2P_STATE_RX_INVITE_RESP_FAIL = 20,
/* receiving p2p negotiation response with information is not available */
P2P_STATE_RX_INFOR_NOREADY = 21,
/* sending p2p negotiation response with information is not available */
P2P_STATE_TX_INFOR_NOREADY = 22,
};
enum P2P_WPSINFO {
P2P_NO_WPSINFO = 0,
P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1,
P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2,
P2P_GOT_WPSINFO_PBC = 3,
};
#define P2P_PRIVATE_IOCTL_SET_LEN 64
enum P2P_PROTO_WK_ID {
P2P_FIND_PHASE_WK = 0,
P2P_RESTORE_STATE_WK = 1,
P2P_PRE_TX_PROVDISC_PROCESS_WK = 2,
P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3,
P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4,
P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5,
P2P_RO_CH_WK = 6,
};
enum P2P_PS_STATE {
P2P_PS_DISABLE = 0,
P2P_PS_ENABLE = 1,
P2P_PS_SCAN = 2,
P2P_PS_SCAN_DONE = 3,
P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
};
enum P2P_PS_MODE {
P2P_PS_NONE = 0,
P2P_PS_CTWINDOW = 1,
P2P_PS_NOA = 2,
P2P_PS_MIX = 3, /* CTWindow and NoA */
};
#define IP_MCAST_MAC(mac) \
((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e))
#define ICMPV6_MCAST_MAC(mac) \
((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff))
#endif /* _WIFI_H_ */

272
drivers/staging/r8188eu/include/wlan_bssdef.h
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@ -1,272 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#ifndef __WLAN_BSSDEF_H__
#define __WLAN_BSSDEF_H__
#define MAX_IE_SZ 768
#define NDIS_802_11_LENGTH_SSID 32
#define NDIS_802_11_LENGTH_RATES 8
#define NDIS_802_11_LENGTH_RATES_EX 16
#define NDIS_802_11_RSSI long /* in dBm */
struct ndis_802_11_ssid {
u32 SsidLength;
u8 Ssid[32];
};
struct ndis_802_11_config_fh {
u32 Length; /* Length of structure */
u32 HopPattern; /* As defined by 802.11, MSB set */
u32 HopSet; /* to one if non-802.11 */
u32 DwellTime; /* units are Kusec */
};
/*
* FW will only save the channel number in DSConfig.
* ODI Handler will convert the channel number to freq. number.
*/
struct ndis_802_11_config {
u32 Length; /* Length of structure */
u32 BeaconPeriod; /* units are Kusec */
u32 ATIMWindow; /* units are Kusec */
u32 DSConfig; /* Frequency, units are kHz */
struct ndis_802_11_config_fh FHConfig;
};
enum ndis_802_11_network_infra {
Ndis802_11IBSS,
Ndis802_11Infrastructure,
Ndis802_11AutoUnknown,
Ndis802_11InfrastructureMax, /* dummy upper bound */
Ndis802_11APMode
};
struct ndis_802_11_fixed_ie {
u8 Timestamp[8];
u16 BeaconInterval;
u16 Capabilities;
};
struct ndis_802_11_var_ie {
u8 ElementID;
u8 Length;
u8 data[];
};
/*
* Length is the 4 bytes multiples of the sume of
* [ETH_ALEN] + 2 + sizeof (struct ndis_802_11_ssid) + sizeof (u32)
* + sizeof (NDIS_802_11_RSSI) + sizeof (enum NDIS_802_11_NETWORK_TYPE)
* + sizeof (struct ndis_802_11_config)
* + NDIS_802_11_LENGTH_RATES_EX + IELength
*
* Except the IELength, all other fields are fixed length.
* Therefore, we can define a macro to represent the partial sum. */
enum ndis_802_11_auth_mode {
Ndis802_11AuthModeOpen,
Ndis802_11AuthModeShared,
Ndis802_11AuthModeAutoSwitch,
Ndis802_11AuthModeWPA,
Ndis802_11AuthModeWPAPSK,
Ndis802_11AuthModeWPANone,
Ndis802_11AuthModeWAPI,
Ndis802_11AuthModeMax /* Not a real mode, upper bound */
};
enum ndis_802_11_wep_status {
Ndis802_11WEPEnabled,
Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
Ndis802_11WEPDisabled,
Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
Ndis802_11WEPKeyAbsent,
Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
Ndis802_11WEPNotSupported,
Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
Ndis802_11Encryption2Enabled,
Ndis802_11Encryption2KeyAbsent,
Ndis802_11Encryption3Enabled,
Ndis802_11Encryption3KeyAbsent,
Ndis802_11_EncryptionWAPI
};
#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2
#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4
#define NDIS_802_11_AI_RESFI_CAPABILITIES 1
#define NDIS_802_11_AI_RESFI_STATUSCODE 2
#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4
struct ndis_802_11_ai_reqfi {
u16 Capabilities;
u16 ListenInterval;
unsigned char CurrentAPAddress[ETH_ALEN];
};
struct ndis_802_11_ai_resfi {
u16 Capabilities;
u16 StatusCode;
u16 AssociationId;
};
struct ndis_802_11_assoc_info {
u32 Length;
u16 AvailableRequestFixedIEs;
struct ndis_802_11_ai_reqfi RequestFixedIEs;
u32 RequestIELength;
u32 OffsetRequestIEs;
u16 AvailableResponseFixedIEs;
struct ndis_802_11_ai_resfi ResponseFixedIEs;
u32 ResponseIELength;
u32 OffsetResponseIEs;
};
/* Key mapping keys require a BSSID */
struct ndis_802_11_key {
u32 Length; /* Length of this structure */
u32 KeyIndex;
u32 KeyLength; /* length of key in bytes */
unsigned char BSSID[ETH_ALEN];
unsigned long long KeyRSC;
u8 KeyMaterial[32]; /* var len depending on above field */
};
struct ndis_802_11_remove_key {
u32 Length; /* Length */
u32 KeyIndex;
unsigned char BSSID[ETH_ALEN];
};
struct ndis_802_11_wep {
u32 Length; /* Length of this structure */
u32 KeyIndex; /* 0 is the per-client key,
* 1-N are the global keys */
u32 KeyLength; /* length of key in bytes */
u8 KeyMaterial[16];/* variable len depending on above field */
};
struct ndis_802_11_auth_req {
u32 Length; /* Length of structure */
unsigned char Bssid[ETH_ALEN];
u32 Flags;
};
enum ndis_802_11_status_type {
Ndis802_11StatusType_Authentication,
Ndis802_11StatusType_MediaStreamMode,
Ndis802_11StatusType_PMKID_CandidateList,
Ndis802_11StatusTypeMax /* not a real type, defined as
* an upper bound */
};
struct ndis_802_11_status_ind {
enum ndis_802_11_status_type StatusType;
};
/* mask for authentication/integrity fields */
#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f
#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01
#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02
#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06
#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E
/* MIC check time, 60 seconds. */
#define MIC_CHECK_TIME 60000000
#ifndef Ndis802_11APMode
#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1)
#endif
struct wlan_phy_info {
u8 SignalStrength;/* in percentage) */
u8 SignalQuality;/* in percentage) */
u8 Optimum_antenna; /* for Antenna diversity */
u8 Reserved_0;
};
struct wlan_bcn_info {
/* these infor get from rtw_get_encrypt_info when
* * translate scan to UI */
u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */
int group_cipher; /* WPA/WPA2 group cipher */
int pairwise_cipher;/* WPA/WPA2/WEP pairwise cipher */
int is_8021x;
/* bwmode 20/40 and ch_offset UP/LOW */
unsigned short ht_cap_info;
unsigned char ht_info_infos_0;
};
/* temporally add #pragma pack for structure alignment issue of
* struct wlan_bssid_ex and get_struct wlan_bssid_ex_sz()
*/
struct wlan_bssid_ex {
u32 Length;
unsigned char MacAddress[ETH_ALEN];
u8 Reserved[2];/* 0]: IS beacon frame */
struct ndis_802_11_ssid Ssid;
u32 Privacy;
NDIS_802_11_RSSI Rssi;/* in dBM,raw data ,get from PHY) */
struct ndis_802_11_config Configuration;
enum ndis_802_11_network_infra InfrastructureMode;
unsigned char SupportedRates[NDIS_802_11_LENGTH_RATES_EX];
struct wlan_phy_info PhyInfo;
u32 IELength;
u8 IEs[MAX_IE_SZ]; /* timestamp, beacon interval, and
* capability information) */
} __packed;
static inline uint get_wlan_bssid_ex_sz(struct wlan_bssid_ex *bss)
{
return sizeof(struct wlan_bssid_ex) - MAX_IE_SZ + bss->IELength;
}
struct wlan_network {
struct list_head list;
int network_type; /* refer to ieee80211.h for WIRELESS_11B/G */
int fixed; /* set fixed when not to be removed
* in site-surveying */
unsigned long last_scanned; /* timestamp for the network */
int aid; /* will only be valid when a BSS is joinned. */
int join_res;
struct wlan_bssid_ex network; /* must be the last item */
struct wlan_bcn_info BcnInfo;
};
enum VRTL_CARRIER_SENSE {
DISABLE_VCS,
ENABLE_VCS,
AUTO_VCS
};
enum VCS_TYPE {
NONE_VCS,
RTS_CTS,
CTS_TO_SELF
};
#define PWR_CAM 0
#define PWR_MINPS 1
#define PWR_MAXPS 2
#define PWR_UAPSD 3
#define PWR_VOIP 4
enum UAPSD_MAX_SP {
NO_LIMIT,
TWO_MSDU,
FOUR_MSDU,
SIX_MSDU
};
#define NUM_PRE_AUTH_KEY 16
#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY
u8 key_2char2num(u8 hch, u8 lch);
u8 key_char2num(u8 ch);
u8 str_2char2num(u8 hch, u8 lch);
#endif /* ifndef WLAN_BSSDEF_H_ */

3775
drivers/staging/r8188eu/os_dep/ioctl_linux.c
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drivers/staging/r8188eu/os_dep/os_intfs.c
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// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2011 Realtek Corporation. */
#define _OS_INTFS_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/hal_intf.h"
#include "../include/rtw_ioctl.h"
#include "../include/usb_osintf.h"
#include "../include/rtw_br_ext.h"
#include "../include/rtw_led.h"
#include "../include/rtl8188e_dm.h"
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
MODULE_AUTHOR("Realtek Semiconductor Corp.");
MODULE_FIRMWARE(FW_RTL8188EU);
#define CONFIG_BR_EXT_BRNAME "br0"
#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
/* module param defaults */
static int rtw_rfintfs = HWPI;
static int rtw_lbkmode;/* RTL8712_AIR_TRX; */
static int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; infra, ad-hoc, auto */
static int rtw_channel = 1;/* ad-hoc support requirement */
static int rtw_wireless_mode = WIRELESS_11BG_24N;
static int rtw_vrtl_carrier_sense = AUTO_VCS;
static int rtw_vcs_type = RTS_CTS;/* */
static int rtw_rts_thresh = 2347;/* */
static int rtw_frag_thresh = 2346;/* */
static int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */
static int rtw_scan_mode = 1;/* active, passive */
static int rtw_adhoc_tx_pwr = 1;
static int rtw_soft_ap;
static int rtw_power_mgnt = 1;
static int rtw_ips_mode = IPS_NORMAL;
static int rtw_smart_ps = 2;
module_param(rtw_ips_mode, int, 0644);
MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode");
static int rtw_radio_enable = 1;
static int rtw_long_retry_lmt = 7;
static int rtw_short_retry_lmt = 7;
static int rtw_busy_thresh = 40;
static int rtw_ack_policy = NORMAL_ACK;
static int rtw_software_encrypt;
static int rtw_software_decrypt;
static int rtw_acm_method;/* 0:By SW 1:By HW. */
static int rtw_wmm_enable = 1;/* default is set to enable the wmm. */
static int rtw_uapsd_enable;
static int rtw_uapsd_max_sp = NO_LIMIT;
static int rtw_uapsd_acbk_en;
static int rtw_uapsd_acbe_en;
static int rtw_uapsd_acvi_en;
static int rtw_uapsd_acvo_en;
static int rtw_led_enable = 1;
static int rtw_ht_enable = 1;
static int rtw_cbw40_enable = 3; /* 0 :disable, bit(0): enable 2.4g, bit(1): enable 5g */
static int rtw_ampdu_enable = 1;/* for enable tx_ampdu */
static int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
static int rtw_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto */
static int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */
static int rtw_low_power;
static int rtw_wifi_spec;
static int rtw_channel_plan = RT_CHANNEL_DOMAIN_MAX;
static int rtw_AcceptAddbaReq = true;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */
static int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */
static int rtw_antdiv_type; /* 0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.(2 Ant, Tx and RxCG are both on aux port, RxCS is on main port), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
static int rtw_hwpdn_mode = 2;/* 0:disable, 1:enable, 2: by EFUSE config */
static int rtw_hwpwrp_detect; /* HW power ping detect 0:disable , 1:enable */
static int rtw_hw_wps_pbc = 1;
int rtw_mc2u_disable;
static int rtw_80211d;
static char *ifname = "wlan%d";
module_param(ifname, charp, 0644);
MODULE_PARM_DESC(ifname, "The default name to allocate for first interface");
static char *if2name = "wlan%d";
module_param(if2name, charp, 0644);
MODULE_PARM_DESC(if2name, "The default name to allocate for second interface");
char *rtw_initmac; /* temp mac address if users want to use instead of the mac address in Efuse */
module_param(rtw_initmac, charp, 0644);
module_param(rtw_channel_plan, int, 0644);
module_param(rtw_rfintfs, int, 0644);
module_param(rtw_lbkmode, int, 0644);
module_param(rtw_network_mode, int, 0644);
module_param(rtw_channel, int, 0644);
module_param(rtw_wmm_enable, int, 0644);
module_param(rtw_vrtl_carrier_sense, int, 0644);
module_param(rtw_vcs_type, int, 0644);
module_param(rtw_busy_thresh, int, 0644);
module_param(rtw_led_enable, int, 0644);
module_param(rtw_ht_enable, int, 0644);
module_param(rtw_cbw40_enable, int, 0644);
module_param(rtw_ampdu_enable, int, 0644);
module_param(rtw_rx_stbc, int, 0644);
module_param(rtw_ampdu_amsdu, int, 0644);
module_param(rtw_lowrate_two_xmit, int, 0644);
module_param(rtw_power_mgnt, int, 0644);
module_param(rtw_smart_ps, int, 0644);
module_param(rtw_low_power, int, 0644);
module_param(rtw_wifi_spec, int, 0644);
module_param(rtw_antdiv_cfg, int, 0644);
module_param(rtw_antdiv_type, int, 0644);
module_param(rtw_hwpdn_mode, int, 0644);
module_param(rtw_hwpwrp_detect, int, 0644);
module_param(rtw_hw_wps_pbc, int, 0644);
static uint rtw_max_roaming_times = 2;
module_param(rtw_max_roaming_times, uint, 0644);
MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try");
static int rtw_fw_iol = 1;/* 0:Disable, 1:enable, 2:by usb speed */
module_param(rtw_fw_iol, int, 0644);
MODULE_PARM_DESC(rtw_fw_iol, "FW IOL");
module_param(rtw_mc2u_disable, int, 0644);
module_param(rtw_80211d, int, 0644);
MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism");
static uint rtw_notch_filter = RTW_NOTCH_FILTER;
module_param(rtw_notch_filter, uint, 0644);
MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P");
static uint loadparam(struct adapter *padapter)
{
struct registry_priv *registry_par = &padapter->registrypriv;
registry_par->rfintfs = (u8)rtw_rfintfs;
registry_par->lbkmode = (u8)rtw_lbkmode;
registry_par->network_mode = (u8)rtw_network_mode;
memcpy(registry_par->ssid.Ssid, "ANY", 3);
registry_par->ssid.SsidLength = 3;
registry_par->channel = (u8)rtw_channel;
registry_par->wireless_mode = (u8)rtw_wireless_mode;
registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense;
registry_par->vcs_type = (u8)rtw_vcs_type;
registry_par->rts_thresh = (u16)rtw_rts_thresh;
registry_par->frag_thresh = (u16)rtw_frag_thresh;
registry_par->preamble = (u8)rtw_preamble;
registry_par->scan_mode = (u8)rtw_scan_mode;
registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr;
registry_par->soft_ap = (u8)rtw_soft_ap;
registry_par->smart_ps = (u8)rtw_smart_ps;
registry_par->power_mgnt = (u8)rtw_power_mgnt;
registry_par->ips_mode = (u8)rtw_ips_mode;
registry_par->radio_enable = (u8)rtw_radio_enable;
registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt;
registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt;
registry_par->busy_thresh = (u16)rtw_busy_thresh;
registry_par->ack_policy = (u8)rtw_ack_policy;
registry_par->software_encrypt = (u8)rtw_software_encrypt;
registry_par->software_decrypt = (u8)rtw_software_decrypt;
registry_par->acm_method = (u8)rtw_acm_method;
/* UAPSD */
registry_par->wmm_enable = (u8)rtw_wmm_enable;
registry_par->uapsd_enable = (u8)rtw_uapsd_enable;
registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp;
registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en;
registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en;
registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en;
registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en;
registry_par->led_enable = (u8)rtw_led_enable;
registry_par->ht_enable = (u8)rtw_ht_enable;
registry_par->cbw40_enable = (u8)rtw_cbw40_enable;
registry_par->ampdu_enable = (u8)rtw_ampdu_enable;
registry_par->rx_stbc = (u8)rtw_rx_stbc;
registry_par->ampdu_amsdu = (u8)rtw_ampdu_amsdu;
registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit;
registry_par->low_power = (u8)rtw_low_power;
registry_par->wifi_spec = (u8)rtw_wifi_spec;
registry_par->channel_plan = (u8)rtw_channel_plan;
registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq;
registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg;
registry_par->antdiv_type = (u8)rtw_antdiv_type;
registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;/* 0:disable, 1:enable, 2:by EFUSE config */
registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;/* 0:disable, 1:enable */
registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc;
registry_par->max_roaming_times = (u8)rtw_max_roaming_times;
registry_par->fw_iol = rtw_fw_iol;
registry_par->enable80211d = (u8)rtw_80211d;
snprintf(registry_par->ifname, 16, "%s", ifname);
snprintf(registry_par->if2name, 16, "%s", if2name);
registry_par->notch_filter = (u8)rtw_notch_filter;
return _SUCCESS;
}
static int rtw_net_set_mac_address(struct net_device *pnetdev, void *p)
{
struct adapter *padapter = (struct adapter *)rtw_netdev_priv(pnetdev);
struct sockaddr *addr = p;
if (!padapter->bup)
memcpy(padapter->eeprompriv.mac_addr, addr->sa_data, ETH_ALEN);
return 0;
}
static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev)
{
struct adapter *padapter = (struct adapter *)rtw_netdev_priv(pnetdev);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct recv_priv *precvpriv = &padapter->recvpriv;
padapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */
padapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */
padapter->stats.tx_dropped = pxmitpriv->tx_drop;
padapter->stats.rx_dropped = precvpriv->rx_drop;
padapter->stats.tx_bytes = pxmitpriv->tx_bytes;
padapter->stats.rx_bytes = precvpriv->rx_bytes;
return &padapter->stats;
}
/*
* AC to queue mapping
*
* AC_VO -> queue 0
* AC_VI -> queue 1
* AC_BE -> queue 2
* AC_BK -> queue 3
*/
static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 };
/* Given a data frame determine the 802.1p/1d tag to use. */
static unsigned int rtw_classify8021d(struct sk_buff *skb)
{
unsigned int dscp;
/* skb->priority values from 256->263 are magic values to
* directly indicate a specific 802.1d priority. This is used
* to allow 802.1d priority to be passed directly in from VLAN
* tags, etc.
*/
if (skb->priority >= 256 && skb->priority <= 263)
return skb->priority - 256;
switch (skb->protocol) {
case htons(ETH_P_IP):
dscp = ip_hdr(skb)->tos & 0xfc;
break;
default:
return 0;
}
return dscp >> 5;
}
static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev)
{
struct adapter *padapter = rtw_netdev_priv(dev);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
skb->priority = rtw_classify8021d(skb);
if (pmlmepriv->acm_mask != 0)
skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority);
return rtw_1d_to_queue[skb->priority];
}
u16 rtw_recv_select_queue(struct sk_buff *skb)
{
struct iphdr *piphdr;
unsigned int dscp;
__be16 eth_type;
u32 priority;
u8 *pdata = skb->data;
memcpy(&eth_type, pdata + (ETH_ALEN << 1), 2);
switch (eth_type) {
case htons(ETH_P_IP):
piphdr = (struct iphdr *)(pdata + ETH_HLEN);
dscp = piphdr->tos & 0xfc;
priority = dscp >> 5;
break;
default:
priority = 0;
}
return rtw_1d_to_queue[priority];
}
static const struct net_device_ops rtw_netdev_ops = {
.ndo_open = netdev_open,
.ndo_stop = netdev_close,
.ndo_start_xmit = rtw_xmit_entry,
.ndo_select_queue = rtw_select_queue,
.ndo_set_mac_address = rtw_net_set_mac_address,
.ndo_get_stats = rtw_net_get_stats,
};
int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname)
{
int err;
err = dev_alloc_name(pnetdev, ifname);
if (err < 0)
return err;
netif_carrier_off(pnetdev);
return 0;
}
static const struct device_type wlan_type = {
.name = "wlan",
};
struct net_device *rtw_init_netdev(struct adapter *old_padapter)
{
struct adapter *padapter;
struct net_device *pnetdev;
if (old_padapter)
pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(struct adapter), (void *)old_padapter);
else
pnetdev = rtw_alloc_etherdev(sizeof(struct adapter));
if (!pnetdev)
return NULL;
pnetdev->dev.type = &wlan_type;
padapter = rtw_netdev_priv(pnetdev);
padapter->pnetdev = pnetdev;
pnetdev->netdev_ops = &rtw_netdev_ops;
pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */
pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def;
/* step 2. */
loadparam(padapter);
return pnetdev;
}
int rtw_start_drv_threads(struct adapter *padapter)
{
padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD");
if (IS_ERR(padapter->cmdThread))
return PTR_ERR(padapter->cmdThread);
/* wait for rtw_cmd_thread() to start running */
wait_for_completion(&padapter->cmdpriv.start_cmd_thread);
return 0;
}
void rtw_stop_drv_threads(struct adapter *padapter)
{
/* Below is to termindate rtw_cmd_thread & event_thread... */
complete(&padapter->cmdpriv.enqueue_cmd);
if (padapter->cmdThread)
/* wait for rtw_cmd_thread() to stop running */
wait_for_completion(&padapter->cmdpriv.stop_cmd_thread);
}
static void rtw_init_default_value(struct adapter *padapter)
{
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
/* xmit_priv */
pxmitpriv->frag_len = pregistrypriv->frag_thresh;
/* mlme_priv */
pmlmepriv->scan_interval = SCAN_INTERVAL;/* 30*2 sec = 60sec */
pmlmepriv->scan_mode = SCAN_ACTIVE;
/* ht_priv */
pmlmepriv->htpriv.ampdu_enable = false;/* set to disabled */
/* security_priv */
psecuritypriv->binstallGrpkey = false;
psecuritypriv->sw_encrypt = pregistrypriv->software_encrypt;
psecuritypriv->sw_decrypt = pregistrypriv->software_decrypt;
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
psecuritypriv->dot11PrivacyKeyIndex = 0;
psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
psecuritypriv->dot118021XGrpKeyid = 1;
psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled;
/* registry_priv */
rtw_init_registrypriv_dev_network(padapter);
rtw_update_registrypriv_dev_network(padapter);
/* hal_priv */
rtl8188eu_init_default_value(padapter);
/* misc. */
padapter->bReadPortCancel = false;
padapter->bWritePortCancel = false;
padapter->bRxRSSIDisplay = 0;
padapter->bNotifyChannelChange = 0;
padapter->bShowGetP2PState = 1;
}
void rtw_reset_drv_sw(struct adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
/* hal_priv */
rtl8188eu_init_default_value(padapter);
padapter->bReadPortCancel = false;
padapter->bWritePortCancel = false;
padapter->bRxRSSIDisplay = 0;
pmlmepriv->scan_interval = SCAN_INTERVAL;/* 30*2 sec = 60sec */
padapter->xmitpriv.tx_pkts = 0;
padapter->recvpriv.rx_pkts = 0;
pmlmepriv->LinkDetectInfo.bBusyTraffic = false;
_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING);
/* mlmeextpriv */
padapter->mlmeextpriv.sitesurvey_res.state = SCAN_DISABLE;
rtw_set_signal_stat_timer(&padapter->recvpriv);
}
u8 rtw_init_drv_sw(struct adapter *padapter)
{
if (rtw_init_cmd_priv(&padapter->cmdpriv)) {
dev_err(dvobj_to_dev(padapter->dvobj), "rtw_init_cmd_priv failed\n");
return _FAIL;
}
padapter->cmdpriv.padapter = padapter;
if (rtw_init_evt_priv(&padapter->evtpriv)) {
dev_err(dvobj_to_dev(padapter->dvobj), "rtw_init_evt_priv failed\n");
goto free_cmd_priv;
}
if (rtw_init_mlme_priv(padapter)) {
dev_err(dvobj_to_dev(padapter->dvobj), "rtw_init_mlme_priv failed\n");
goto free_evt_priv;
}
rtw_init_wifidirect_timers(padapter);
init_wifidirect_info(padapter, P2P_ROLE_DISABLE);
reset_global_wifidirect_info(padapter);
init_mlme_ext_priv(padapter);
if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter)) {
dev_err(dvobj_to_dev(padapter->dvobj), "_rtw_init_xmit_priv failed\n");
goto free_mlme_ext;
}
if (_rtw_init_recv_priv(&padapter->recvpriv, padapter)) {
dev_err(dvobj_to_dev(padapter->dvobj), "_rtw_init_recv_priv failed\n");
goto free_xmit_priv;
}
if (_rtw_init_sta_priv(&padapter->stapriv)) {
dev_err(dvobj_to_dev(padapter->dvobj), "_rtw_init_sta_priv failed\n");
goto free_recv_priv;
}
padapter->stapriv.padapter = padapter;
rtw_init_bcmc_stainfo(padapter);
rtw_init_pwrctrl_priv(padapter);
rtw_init_default_value(padapter);
rtl8188e_init_dm_priv(padapter);
rtl8188eu_InitSwLeds(padapter);
spin_lock_init(&padapter->br_ext_lock);
return _SUCCESS;
free_recv_priv:
_rtw_free_recv_priv(&padapter->recvpriv);
free_xmit_priv:
_rtw_free_xmit_priv(&padapter->xmitpriv);
free_mlme_ext:
free_mlme_ext_priv(&padapter->mlmeextpriv);
rtw_free_mlme_priv(&padapter->mlmepriv);
free_evt_priv:
rtw_free_evt_priv(&padapter->evtpriv);
free_cmd_priv:
rtw_free_cmd_priv(&padapter->cmdpriv);
return _FAIL;
}
void rtw_cancel_all_timer(struct adapter *padapter)
{
_cancel_timer_ex(&padapter->mlmepriv.assoc_timer);
_cancel_timer_ex(&padapter->mlmepriv.scan_to_timer);
_cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer);
/* cancel sw led timer */
rtl8188eu_DeInitSwLeds(padapter);
_cancel_timer_ex(&padapter->pwrctrlpriv.pwr_state_check_timer);
_cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);
}
void rtw_free_drv_sw(struct adapter *padapter)
{
/* we can call rtw_p2p_enable here, but: */
/* 1. rtw_p2p_enable may have IO operation */
/* 2. rtw_p2p_enable is bundled with wext interface */
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
_cancel_timer_ex(&pwdinfo->find_phase_timer);
_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
}
}
free_mlme_ext_priv(&padapter->mlmeextpriv);
rtw_free_cmd_priv(&padapter->cmdpriv);
rtw_free_evt_priv(&padapter->evtpriv);
rtw_free_mlme_priv(&padapter->mlmepriv);
_rtw_free_xmit_priv(&padapter->xmitpriv);
_rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */
_rtw_free_recv_priv(&padapter->recvpriv);
/* free the old_pnetdev */
if (padapter->rereg_nd_name_priv.old_pnetdev) {
free_netdev(padapter->rereg_nd_name_priv.old_pnetdev);
padapter->rereg_nd_name_priv.old_pnetdev = NULL;
}
/* clear pbuddystruct adapter to avoid access wrong pointer. */
if (padapter->pbuddy_adapter)
padapter->pbuddy_adapter->pbuddy_adapter = NULL;
}
void netdev_br_init(struct net_device *netdev)
{
struct adapter *adapter = (struct adapter *)rtw_netdev_priv(netdev);
rcu_read_lock();
if (rcu_dereference(adapter->pnetdev->rx_handler_data)) {
struct net_device *br_netdev;
struct net *devnet = NULL;
devnet = dev_net(netdev);
br_netdev = dev_get_by_name(devnet, CONFIG_BR_EXT_BRNAME);
if (br_netdev) {
memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN);
dev_put(br_netdev);
} else {
pr_info("%s()-%d: dev_get_by_name(%s) failed!",
__func__, __LINE__, CONFIG_BR_EXT_BRNAME);
}
}
adapter->ethBrExtInfo.addPPPoETag = 1;
rcu_read_unlock();
}
static int _netdev_open(struct net_device *pnetdev)
{
uint status;
struct adapter *padapter = (struct adapter *)rtw_netdev_priv(pnetdev);
if (!padapter->bup) {
padapter->bDriverStopped = false;
padapter->bSurpriseRemoved = false;
status = rtw_hal_init(padapter);
if (status == _FAIL)
goto netdev_open_error;
netdev_dbg(pnetdev, "MAC Address = %pM\n", pnetdev->dev_addr);
if (rtw_start_drv_threads(padapter)) {
pr_info("Initialize driver software resource Failed!\n");
goto netdev_open_error;
}
if (init_hw_mlme_ext(padapter) == _FAIL) {
pr_info("can't init mlme_ext_priv\n");
goto netdev_open_error;
}
if (rtl8188eu_inirp_init(padapter))
goto netdev_open_error;
rtw_led_control(padapter, LED_CTL_NO_LINK);
padapter->bup = true;
}
padapter->net_closed = false;
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
padapter->pwrctrlpriv.bips_processing = false;
rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
if (!rtw_netif_queue_stopped(pnetdev))
netif_tx_start_all_queues(pnetdev);
else
netif_tx_wake_all_queues(pnetdev);
netdev_br_init(pnetdev);
return 0;
netdev_open_error:
padapter->bup = false;
netif_carrier_off(pnetdev);
netif_tx_stop_all_queues(pnetdev);
return -1;
}
int netdev_open(struct net_device *pnetdev)
{
int ret;
struct adapter *padapter = (struct adapter *)rtw_netdev_priv(pnetdev);
mutex_lock(padapter->hw_init_mutex);
ret = _netdev_open(pnetdev);
mutex_unlock(padapter->hw_init_mutex);
return ret;
}
static int ips_netdrv_open(struct adapter *padapter)
{
int status = _SUCCESS;
padapter->net_closed = false;
padapter->bDriverStopped = false;
padapter->bSurpriseRemoved = false;
status = rtw_hal_init(padapter);
if (status == _FAIL)
goto netdev_open_error;
if (rtl8188eu_inirp_init(padapter))
goto netdev_open_error;
rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 5000);
return _SUCCESS;
netdev_open_error:
return _FAIL;
}
int rtw_ips_pwr_up(struct adapter *padapter)
{
int result;
rtw_reset_drv_sw(padapter);
result = ips_netdrv_open(padapter);
rtw_led_control(padapter, LED_CTL_NO_LINK);
return result;
}
void rtw_ips_pwr_down(struct adapter *padapter)
{
padapter->net_closed = true;
rtw_led_control(padapter, LED_CTL_POWER_OFF);
rtw_ips_dev_unload(padapter);
}
static void rtw_fifo_cleanup(struct adapter *adapter)
{
struct pwrctrl_priv *pwrpriv = &adapter->pwrctrlpriv;
u8 trycnt = 100;
int res;
u32 reg;
/* pause tx */
rtw_write8(adapter, REG_TXPAUSE, 0xff);
/* keep sn */
/* FIXME: return an error to caller */
res = rtw_read16(adapter, REG_NQOS_SEQ, &adapter->xmitpriv.nqos_ssn);
if (res)
return;
if (!pwrpriv->bkeepfwalive) {
/* RX DMA stop */
res = rtw_read32(adapter, REG_RXPKT_NUM, &reg);
if (res)
return;
rtw_write32(adapter, REG_RXPKT_NUM,
(reg | RW_RELEASE_EN));
do {
res = rtw_read32(adapter, REG_RXPKT_NUM, &reg);
if (res)
continue;
if (!(reg & RXDMA_IDLE))
break;
} while (trycnt--);
/* RQPN Load 0 */
rtw_write16(adapter, REG_RQPN_NPQ, 0x0);
rtw_write32(adapter, REG_RQPN, 0x80000000);
mdelay(10);
}
}
void rtw_ips_dev_unload(struct adapter *padapter)
{
rtw_fifo_cleanup(padapter);
rtw_read_port_cancel(padapter);
rtw_write_port_cancel(padapter);
/* s5. */
if (!padapter->bSurpriseRemoved)
rtw_hal_deinit(padapter);
}
int netdev_close(struct net_device *pnetdev)
{
struct adapter *padapter = (struct adapter *)rtw_netdev_priv(pnetdev);
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
padapter->net_closed = true;
if (padapter->pwrctrlpriv.rf_pwrstate == rf_on) {
/* s1. */
if (pnetdev) {
if (!rtw_netif_queue_stopped(pnetdev))
netif_tx_stop_all_queues(pnetdev);
}
/* s2. */
LeaveAllPowerSaveMode(padapter);
rtw_disassoc_cmd(padapter, 500, false);
/* s2-2. indicate disconnect to os */
rtw_indicate_disconnect(padapter);
/* s2-3. */
rtw_free_assoc_resources(padapter, 1);
/* s2-4. */
rtw_free_network_queue(padapter, true);
/* Close LED */
rtw_led_control(padapter, LED_CTL_POWER_OFF);
}
nat25_db_cleanup(padapter);
rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
kfree(dvobj->firmware.data);
dvobj->firmware.data = NULL;
return 0;
}

227
drivers/staging/r8188eu/os_dep/osdep_service.c
View File

@ -1,227 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2012 Realtek Corporation. */
#define _OSDEP_SERVICE_C_
#include "../include/osdep_service.h"
#include "../include/drv_types.h"
#include "../include/rtw_ioctl_set.h"
/*
* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE
* @return: one of RTW_STATUS_CODE
*/
inline int RTW_STATUS_CODE(int error_code)
{
if (error_code >= 0)
return _SUCCESS;
return _FAIL;
}
void *rtw_malloc2d(int h, int w, int size)
{
int j;
void **a = kzalloc(h * sizeof(void *) + h * w * size, GFP_KERNEL);
if (!a)
return NULL;
for (j = 0; j < h; j++)
a[j] = ((char *)(a + h)) + j * w * size;
return a;
}
/*
For the following list_xxx operations,
caller must guarantee the atomic context.
Otherwise, there will be racing condition.
*/
/*
Caller must check if the list is empty before calling rtw_list_delete
*/
static const struct device_type wlan_type = {
.name = "wlan",
};
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv,
void *old_priv)
{
struct net_device *pnetdev;
struct rtw_netdev_priv_indicator *pnpi;
pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
if (!pnetdev)
return NULL;
pnetdev->dev.type = &wlan_type;
pnpi = netdev_priv(pnetdev);
pnpi->priv = old_priv;
pnpi->sizeof_priv = sizeof_priv;
return pnetdev;
}
struct net_device *rtw_alloc_etherdev(int sizeof_priv)
{
struct net_device *pnetdev;
struct rtw_netdev_priv_indicator *pnpi;
pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
if (!pnetdev)
return NULL;
pnpi = netdev_priv(pnetdev);
pnpi->priv = vzalloc(sizeof_priv);
if (!pnpi->priv) {
free_netdev(pnetdev);
return NULL;
}
pnpi->sizeof_priv = sizeof_priv;
return pnetdev;
}
void rtw_free_netdev(struct net_device *netdev)
{
struct rtw_netdev_priv_indicator *pnpi;
pnpi = netdev_priv(netdev);
vfree(pnpi->priv);
free_netdev(netdev);
}
int rtw_change_ifname(struct adapter *padapter, const char *ifname)
{
struct net_device *pnetdev;
struct net_device *cur_pnetdev;
struct rereg_nd_name_data *rereg_priv;
int ret;
if (!padapter)
goto error;
cur_pnetdev = padapter->pnetdev;
rereg_priv = &padapter->rereg_nd_name_priv;
/* free the old_pnetdev */
if (rereg_priv->old_pnetdev) {
free_netdev(rereg_priv->old_pnetdev);
rereg_priv->old_pnetdev = NULL;
}
if (!rtnl_is_locked())
unregister_netdev(cur_pnetdev);
else
unregister_netdevice(cur_pnetdev);
rereg_priv->old_pnetdev = cur_pnetdev;
pnetdev = rtw_init_netdev(padapter);
if (!pnetdev) {
ret = -1;
goto error;
}
SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter)));
rtw_init_netdev_name(pnetdev, ifname);
eth_hw_addr_set(pnetdev, padapter->eeprompriv.mac_addr);
if (!rtnl_is_locked())
ret = register_netdev(pnetdev);
else
ret = register_netdevice(pnetdev);
if (ret != 0)
goto error;
return 0;
error:
return -1;
}
void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len)
{
u32 dup_len = 0;
u8 *ori = NULL;
u8 *dup = NULL;
if (!buf || !buf_len)
return;
if (!src || !src_len)
goto keep_ori;
/* duplicate src */
dup = kmalloc(src_len, GFP_ATOMIC);
if (dup) {
dup_len = src_len;
memcpy(dup, src, dup_len);
}
keep_ori:
ori = *buf;
/* replace buf with dup */
*buf_len = 0;
*buf = dup;
*buf_len = dup_len;
/* free ori */
kfree(ori);
}
/**
* rtw_cbuf_empty - test if cbuf is empty
* @cbuf: pointer of struct rtw_cbuf
*
* Returns: true if cbuf is empty
*/
inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)
{
return cbuf->write == cbuf->read;
}
/**
* rtw_cbuf_pop - pop a pointer from cbuf
* @cbuf: pointer of struct rtw_cbuf
*
* Lock free operation, be careful of the use scheme
* Returns: pointer popped out
*/
void *rtw_cbuf_pop(struct rtw_cbuf *cbuf)
{
void *buf;
if (rtw_cbuf_empty(cbuf))
return NULL;
buf = cbuf->bufs[cbuf->read];
cbuf->read = (cbuf->read + 1) % cbuf->size;
return buf;
}
/**
* rtw_cbuf_alloc - allocate a rtw_cbuf with given size and do initialization
* @size: size of pointer
*
* Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure
*/
struct rtw_cbuf *rtw_cbuf_alloc(u32 size)
{
struct rtw_cbuf *cbuf;
cbuf = kmalloc(struct_size(cbuf, bufs, size), GFP_KERNEL);
if (cbuf) {
cbuf->write = 0;
cbuf->read = 0;
cbuf->size = size;
}
return cbuf;
}

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