drm/amd/include:cleanup vega10 dce header files.

Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

@@ -29,8 +29,8 @@
 #include "hdp/hdp_4_0_offset.h"
 #include "hdp/hdp_4_0_sh_mask.h"
 #include "vega10/GC/gc_9_0_sh_mask.h"
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/vega10_enum.h"
 #include "vega10/MMHUB/mmhub_1_0_offset.h"
 #include "athub/athub_1_0_offset.h"

drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

@@ -31,8 +31,8 @@
 
 #include "dce110/dce110_hw_sequencer.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 #include "reg_helper.h"
 

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

@@ -54,8 +54,8 @@
 #include "dce/dce_abm.h"
 #include "dce/dce_dmcu.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 #include "vega10/NBIO/nbio_6_1_offset.h"
 #include "reg_helper.h"

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

@@ -25,8 +25,8 @@
 
 #include "dm_services.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 #include "dc_types.h"

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

@@ -34,8 +34,8 @@
 
 #include "hw_factory_dce120.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 #define block HPD

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

@@ -33,8 +33,8 @@
 #include "include/gpio_types.h"
 #include "../hw_translate.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 /* begin *********************

drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c

@@ -36,8 +36,8 @@
 #include "../dce110/aux_engine_dce110.h"
 #include "../dce110/i2caux_dce110.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 /* begin *********************

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

@@ -30,8 +30,8 @@
 #include "irq_service_dce120.h"
 #include "../dce110/irq_service_dce110.h"
 
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "dce/dce_12_0_offset.h"
+#include "dce/dce_12_0_sh_mask.h"
 #include "vega10/soc15ip.h"
 
 #include "ivsrcid/ivsrcid_vislands30.h"