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net: ixp4xx_hss: remove redundant spaces

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According to the chackpatch.pl,
space prohibited after that open parenthesis '('.

Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Peng Li 2021-06-10 15:20:03 +08:00 committed by David S. Miller
parent dee0145677
commit 137d5672f8
1 changed files with 13 additions and 13 deletions
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26
drivers/net/wan/ixp4xx_hss.c
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@ -150,21 +150,21 @@
#define CCR_SECOND_HSS 0x01000000
/* hss_config, clkCR: main:10, num:10, denom:12 */
#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
#define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/
#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
#define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15)
#define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47)
#define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192)
#define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63)
#define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127)
#define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255)
#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
#define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127)
#define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383)
#define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385)
#define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511)
#define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023)
#define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047)
/*
* HSS_CONFIG_CLOCK_CR register consists of 3 parts: