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clk: xgene: Fix divider with non-zero shift value
The X-Gene clock driver missed the divider shift operation when
set the divider value.
Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caee
("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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1 changed files with 2 additions and 1 deletions
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@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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/* Set new divider */
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data = xgene_clk_read(pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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data &= ~((1 << pclk->param.reg_divider_width) - 1);
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data &= ~((1 << pclk->param.reg_divider_width) - 1)
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<< pclk->param.reg_divider_shift;
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data |= divider;
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xgene_clk_write(data, pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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