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drm/amd/display: [FW Promotion] Release 0.0.189.0
- Minor formatting changes - Update defines to match the bit width of the field it is used for - Add new boot up bits to control HW sub block regions power down Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Anthony Koo <anthony.koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 5 additions and 7 deletions
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@ -583,6 +583,7 @@ union dmub_fw_boot_status {
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uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
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uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
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uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
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uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
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} bits; /**< status bits */
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uint32_t all; /**< 32-bit access to status bits */
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};
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@ -599,6 +600,7 @@ enum dmub_fw_boot_status_bit {
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DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
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DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
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DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
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DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
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};
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/* Register bit definition for SCRATCH5 */
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@ -2098,7 +2100,7 @@ enum psr_version {
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/**
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* PSR not supported.
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*/
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PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
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PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide
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};
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/**
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@ -3620,7 +3622,6 @@ struct dmub_cmd_abm_pause_data {
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uint8_t pad[1];
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};
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/**
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* Definition of a DMUB_CMD__ABM_PAUSE command.
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*/
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@ -4046,6 +4047,7 @@ union dmub_rb_cmd {
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* Definition of a DMUB_CMD__MALL command.
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*/
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struct dmub_rb_cmd_mall mall;
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/**
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* Definition of a DMUB_CMD__CAB command.
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*/
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@ -4067,6 +4069,7 @@ union dmub_rb_cmd {
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* Definition of DMUB_CMD__PANEL_CNTL commands.
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*/
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struct dmub_rb_cmd_panel_cntl panel_cntl;
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/**
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* Definition of a DMUB_CMD__ABM_SET_PIPE command.
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*/
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@ -4470,10 +4473,6 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
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uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
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uint8_t i;
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/* Don't remove this.
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* The contents need to actually be read from the ring buffer
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* for this function to be effective.
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*/
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for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
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(void)READ_ONCE(*data++);
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@ -4522,5 +4521,4 @@ static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
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//==============================================================================
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//</DMUB_RB>====================================================================
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//==============================================================================
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#endif /* _DMUB_CMD_H_ */
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