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clk: sunxi: Specify number of child clocks for divs clocks
Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks. On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered. This patch adds an entry for the number of child clocks alongside the data structures for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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1 changed files with 9 additions and 2 deletions
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@ -906,6 +906,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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struct divs_data {
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const struct factors_data *factors; /* data for the factor clock */
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int ndivs; /* number of children */
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struct {
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u8 fixed; /* is it a fixed divisor? if not... */
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struct clk_div_table *table; /* is it a table based divisor? */
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@ -925,6 +926,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
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static const struct divs_data pll5_divs_data __initconst = {
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.factors = &sun4i_pll5_data,
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.ndivs = 2,
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.div = {
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{ .shift = 0, .pow = 0, }, /* M, DDR */
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{ .shift = 16, .pow = 1, }, /* P, other */
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@ -933,6 +935,7 @@ static const struct divs_data pll5_divs_data __initconst = {
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static const struct divs_data pll6_divs_data __initconst = {
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.factors = &sun4i_pll6_data,
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.ndivs = 2,
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.div = {
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{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
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{ .fixed = 2 }, /* P, other */
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@ -963,7 +966,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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struct clk_fixed_factor *fix_factor;
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struct clk_divider *divider;
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void __iomem *reg;
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int i = 0;
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int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
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int flags, clkflags;
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/* Set up factor clock that we will be dividing */
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@ -986,7 +989,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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* our RAM clock! */
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clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
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for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
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/* if number of children known, use it */
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if (data->ndivs)
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ndivs = data->ndivs;
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for (i = 0; i < ndivs; i++) {
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if (of_property_read_string_index(node, "clock-output-names",
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i, &clk_name) != 0)
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break;
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