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ASoC: cs42l42: Add PLL ratio table values

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Add 4.8Mhz 9.6Mhz and 19.2MHz SCLK values
for MCLK 12MHz and 12.288MHz requested by Intel.

Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230524125236.57149-1-vitalyr@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vitaly Rodionov 2023-05-24 13:52:36 +01:00 committed by Mark Brown
parent f9f46d0500
commit 13e75f4b03
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1 changed files with 7 additions and 0 deletions
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sound/soc/codecs/cs42l42.c
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@ -646,12 +646,19 @@ static const struct cs42l42_pll_params pll_ratio_table[] = {
{ 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
{ 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1},
{ 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1},
{ 4800000, 1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 4800000, 1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2},
{ 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
{ 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
{ 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
{ 6144000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1},
{ 9600000, 1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 9600000, 1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2},
{ 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
{ 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
{ 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
{ 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
{ 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2},
{ 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
{ 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
{ 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}