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KVM: arm/arm64: vgic-new: Add GICv2 world switch backend
Processing maintenance interrupts and accessing the list registers are dependent on the host's GIC version. Introduce vgic-v2.c to contain GICv2 specific functions. Implement the GICv2 specific code for syncing the emulation state into the VGIC registers. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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@ -76,6 +76,7 @@
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#define GICH_LR_VIRTUALID (0x3ff << 0)
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#define GICH_LR_PHYSID_CPUID_SHIFT (10)
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#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
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#define GICH_LR_PRIORITY_SHIFT 23
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#define GICH_LR_STATE (3 << 28)
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#define GICH_LR_PENDING_BIT (1 << 28)
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#define GICH_LR_ACTIVE_BIT (1 << 29)
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176
virt/kvm/arm/vgic/vgic-v2.c
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176
virt/kvm/arm/vgic/vgic-v2.c
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/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include "vgic.h"
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/*
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* Call this function to convert a u64 value to an unsigned long * bitmask
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* in a way that works on both 32-bit and 64-bit LE and BE platforms.
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*
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* Warning: Calling this function may modify *val.
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*/
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static unsigned long *u64_to_bitmask(u64 *val)
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{
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#if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
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*val = (*val >> 32) | (*val << 32);
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#endif
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return (unsigned long *)val;
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}
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void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
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{
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struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
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if (cpuif->vgic_misr & GICH_MISR_EOI) {
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u64 eisr = cpuif->vgic_eisr;
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unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
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int lr;
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for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
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u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
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WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
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kvm_notify_acked_irq(vcpu->kvm, 0,
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intid - VGIC_NR_PRIVATE_IRQS);
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}
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}
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/* check and disable underflow maintenance IRQ */
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cpuif->vgic_hcr &= ~GICH_HCR_UIE;
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/*
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* In the next iterations of the vcpu loop, if we sync the
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* vgic state after flushing it, but before entering the guest
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* (this happens for pending signals and vmid rollovers), then
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* make sure we don't pick up any old maintenance interrupts
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* here.
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*/
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cpuif->vgic_eisr = 0;
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}
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
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{
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struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
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cpuif->vgic_hcr |= GICH_HCR_UIE;
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}
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/*
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* transfer the content of the LRs back into the corresponding ap_list:
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* - active bit is transferred as is
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* - pending bit is
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* - transferred as is in case of edge sensitive IRQs
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* - set to the line-level (resample time) for level sensitive IRQs
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*/
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void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
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int lr;
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for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
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u32 val = cpuif->vgic_lr[lr];
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u32 intid = val & GICH_LR_VIRTUALID;
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struct vgic_irq *irq;
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irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
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spin_lock(&irq->irq_lock);
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/* Always preserve the active bit */
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irq->active = !!(val & GICH_LR_ACTIVE_BIT);
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/* Edge is the only case where we preserve the pending bit */
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if (irq->config == VGIC_CONFIG_EDGE &&
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(val & GICH_LR_PENDING_BIT)) {
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irq->pending = true;
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if (vgic_irq_is_sgi(intid)) {
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u32 cpuid = val & GICH_LR_PHYSID_CPUID;
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cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
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irq->source |= (1 << cpuid);
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}
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}
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/* Clear soft pending state when level IRQs have been acked */
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if (irq->config == VGIC_CONFIG_LEVEL &&
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!(val & GICH_LR_PENDING_BIT)) {
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irq->soft_pending = false;
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irq->pending = irq->line_level;
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}
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spin_unlock(&irq->irq_lock);
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}
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}
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/*
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* Populates the particular LR with the state of a given IRQ:
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* - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
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* - for a level sensitive IRQ the pending state value is unchanged;
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* it is dictated directly by the input level
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*
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* If @irq describes an SGI with multiple sources, we choose the
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* lowest-numbered source VCPU and clear that bit in the source bitmap.
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*
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* The irq_lock must be held by the caller.
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*/
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
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{
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u32 val = irq->intid;
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if (irq->pending) {
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val |= GICH_LR_PENDING_BIT;
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if (irq->config == VGIC_CONFIG_EDGE)
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irq->pending = false;
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if (vgic_irq_is_sgi(irq->intid)) {
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u32 src = ffs(irq->source);
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BUG_ON(!src);
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val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
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irq->source &= ~(1 << (src - 1));
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if (irq->source)
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irq->pending = true;
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}
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}
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if (irq->active)
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val |= GICH_LR_ACTIVE_BIT;
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if (irq->hw) {
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val |= GICH_LR_HW;
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val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
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} else {
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if (irq->config == VGIC_CONFIG_LEVEL)
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val |= GICH_LR_EOI;
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}
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/* The GICv2 LR only holds five bits of priority. */
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val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
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vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
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}
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
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{
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vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
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}
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@ -400,10 +400,12 @@ static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
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static inline void vgic_process_maintenance_interrupt(struct kvm_vcpu *vcpu)
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{
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vgic_v2_process_maintenance(vcpu);
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}
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static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
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{
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vgic_v2_fold_lr_state(vcpu);
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}
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/* Requires the irq_lock to be held. */
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struct vgic_irq *irq, int lr)
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{
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DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
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vgic_v2_populate_lr(vcpu, irq, lr);
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}
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static inline void vgic_clear_lr(struct kvm_vcpu *vcpu, int lr)
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{
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vgic_v2_clear_lr(vcpu, lr);
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}
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static inline void vgic_set_underflow(struct kvm_vcpu *vcpu)
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{
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vgic_v2_set_underflow(vcpu);
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}
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/* Requires the ap_list_lock to be held. */
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@ -22,4 +22,10 @@ struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
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u32 intid);
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bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
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void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu);
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void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
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#endif
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