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drm/i915/cdclk: update intel_dump_cdclk_config() logging
Gather some intel_dump_cdclk_config() changes together to avoid extra churn: Rename to intel_cdclk_dump_config() to following naming conventions. Pass in i915. Use i915 for struct drm_device based logging. Switch to KMS drm debug class. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/80469a83a74912ad69c4518d9cc68f07d65e9aaf.1642769982.git.jani.nikula@intel.com
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parent
15d641c417
commit
140f70aeef
4 changed files with 15 additions and 13 deletions
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@ -1156,7 +1156,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
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goto sanitize;
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intel_update_cdclk(dev_priv);
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intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
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intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
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/* Is PLL enabled and locked ? */
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if (dev_priv->cdclk.hw.vco == 0 ||
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@ -1817,7 +1817,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
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int cdclk, clock, vco;
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intel_update_cdclk(dev_priv);
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intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
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intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
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if (dev_priv->cdclk.hw.vco == 0 ||
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dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
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@ -2057,13 +2057,14 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
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a->voltage_level != b->voltage_level;
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}
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void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
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void intel_cdclk_dump_config(struct drm_i915_private *i915,
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const struct intel_cdclk_config *cdclk_config,
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const char *context)
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{
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DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
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context, cdclk_config->cdclk, cdclk_config->vco,
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cdclk_config->ref, cdclk_config->bypass,
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cdclk_config->voltage_level);
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drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
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context, cdclk_config->cdclk, cdclk_config->vco,
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cdclk_config->ref, cdclk_config->bypass,
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cdclk_config->voltage_level);
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}
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/**
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@ -2087,7 +2088,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
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if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
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return;
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intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
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intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
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for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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@ -2130,8 +2131,8 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
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if (drm_WARN(&dev_priv->drm,
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intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
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"cdclk state doesn't match!\n")) {
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intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
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intel_dump_cdclk_config(cdclk_config, "[sw state]");
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intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]");
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intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
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}
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}
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@ -62,7 +62,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
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const struct intel_cdclk_config *b);
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void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
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void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
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void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
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void intel_cdclk_dump_config(struct drm_i915_private *i915,
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const struct intel_cdclk_config *cdclk_config,
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const char *context);
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int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
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void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
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@ -9478,7 +9478,7 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
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cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
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intel_update_cdclk(i915);
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intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
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intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
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cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
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}
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@ -5580,7 +5580,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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intel_update_cdclk(dev_priv);
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intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
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intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
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}
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/*
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