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memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members 

The struct exynos5_dmc members bypass_rate, mx_mspll_ccore_phy,
mout_mx_mspll_ccore_phy and opp_bypass are not actually used.

Apparently there was a plan to store the OPP for the bypass mode in
opp_bypass member, but driver fails to do it and instead always sets
target voltage during bypass mode.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200822163218.21857-2-krzk@kernel.org
This commit is contained in:
Krzysztof Kozlowski 2020-08-22 18:32:17 +02:00
parent bb0ebc7d39
commit 1415fa0dca
1 changed files with 0 additions and 9 deletions
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9
drivers/memory/samsung/exynos5422-dmc.c
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@ -123,9 +123,7 @@ struct exynos5_dmc {
struct mutex lock;
unsigned long curr_rate;
unsigned long curr_volt;
unsigned long bypass_rate;
struct dmc_opp_table *opp;
struct dmc_opp_table opp_bypass;
int opp_count;
u32 timings_arr_size;
u32 *timing_row;
@ -143,8 +141,6 @@ struct exynos5_dmc {
struct clk *mout_bpll;
struct clk *mout_mclk_cdrex;
struct clk *mout_mx_mspll_ccore;
struct clk *mx_mspll_ccore_phy;
struct clk *mout_mx_mspll_ccore_phy;
struct devfreq_event_dev **counter;
int num_counters;
u64 last_overflow_ts[2];
@ -455,9 +451,6 @@ static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
unsigned long target_volt)
{
int ret = 0;
unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
target_volt = max(bypass_volt, target_volt);
if (dmc->curr_volt >= target_volt)
return 0;
@ -1268,8 +1261,6 @@ static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore);
clk_prepare_enable(dmc->fout_bpll);
clk_prepare_enable(dmc->mout_bpll);