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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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arm64: dts: qcom: sm8350: move more nodes to correct place
Continue ordering DT nodes by their address. Move RNG, UFS, system NoC and SLPI nodes to the proper position. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209133839.762631-4-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
Bjorn Andersson
parent
f5f6bd5818
commit
1417372f4f
1 changed files with 157 additions and 157 deletions
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@ -1421,6 +1421,13 @@ spi13: spi@a94000 {
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};
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};
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};
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};
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rng: rng@10d3000 {
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compatible = "qcom,prng-ee";
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reg = <0 0x010d3000 0 0x1000>;
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clocks = <&rpmhcc RPMH_HWKM_CLK>;
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clock-names = "core";
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};
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config_noc: interconnect@1500000 {
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config_noc: interconnect@1500000 {
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compatible = "qcom,sm8350-config-noc";
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compatible = "qcom,sm8350-config-noc";
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reg = <0 0x01500000 0 0xa580>;
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reg = <0 0x01500000 0 0xa580>;
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@ -1641,18 +1648,76 @@ pcie1_phy: phy@1c0f000 {
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status = "disabled";
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status = "disabled";
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};
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};
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lpass_ag_noc: interconnect@3c40000 {
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ufs_mem_hc: ufshc@1d84000 {
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compatible = "qcom,sm8350-lpass-ag-noc";
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compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
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reg = <0 0x03c40000 0 0xf080>;
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"jedec,ufs-2.0";
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#interconnect-cells = <2>;
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reg = <0 0x01d84000 0 0x3000>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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power-domains = <&gcc UFS_PHY_GDSC>;
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iommus = <&apps_smmu 0xe0 0x0>;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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status = "disabled";
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};
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};
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compute_noc: interconnect@a0c0000 {
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ufs_mem_phy: phy@1d87000 {
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compatible = "qcom,sm8350-compute-noc";
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compatible = "qcom,sm8350-qmp-ufs-phy";
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reg = <0 0x0a0c0000 0 0xa180>;
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reg = <0 0x01d87000 0 0x1c4>;
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#interconnect-cells = <2>;
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#address-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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#size-cells = <2>;
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ranges;
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clock-names = "ref",
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"ref_aux";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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resets = <&ufs_mem_hc 0>;
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reset-names = "ufsphy";
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status = "disabled";
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ufs_mem_phy_lanes: phy@1d87400 {
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reg = <0 0x01d87400 0 0x188>,
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<0 0x01d87600 0 0x200>,
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<0 0x01d87c00 0 0x200>,
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<0 0x01d87800 0 0x188>,
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<0 0x01d87a00 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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};
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ipa: ipa@1e40000 {
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ipa: ipa@1e40000 {
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@ -1700,6 +1765,13 @@ tcsr_mutex: hwlock@1f40000 {
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#hwlock-cells = <1>;
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#hwlock-cells = <1>;
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};
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};
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lpass_ag_noc: interconnect@3c40000 {
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compatible = "qcom,sm8350-lpass-ag-noc";
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reg = <0 0x03c40000 0 0xf080>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mpss: remoteproc@4080000 {
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mpss: remoteproc@4080000 {
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compatible = "qcom,sm8350-mpss-pas";
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compatible = "qcom,sm8350-mpss-pas";
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reg = <0x0 0x04080000 0x0 0x4040>;
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reg = <0x0 0x04080000 0x0 0x4040>;
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@ -1742,6 +1814,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
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};
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};
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};
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};
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slpi: remoteproc@5c00000 {
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compatible = "qcom,sm8350-slpi-pas";
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reg = <0 0x05c00000 0 0x4000>;
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interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8350_LCX>,
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<&rpmhpd SM8350_LMX>;
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power-domain-names = "lcx", "lmx";
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memory-region = <&pil_slpi_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_slpi_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "slpi";
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qcom,remote-pid = <3>;
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fastrpc {
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compatible = "qcom,fastrpc";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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label = "sdsp";
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qcom,non-secure-domain;
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#address-cells = <1>;
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#size-cells = <0>;
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compute-cb@1 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <1>;
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iommus = <&apps_smmu 0x0541 0x0>;
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};
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compute-cb@2 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <2>;
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iommus = <&apps_smmu 0x0542 0x0>;
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};
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compute-cb@3 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <3>;
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iommus = <&apps_smmu 0x0543 0x0>;
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/* note: shared-cb = <4> in downstream */
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};
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};
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};
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};
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pdc: interrupt-controller@b220000 {
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8350-pdc", "qcom,pdc";
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compatible = "qcom,sm8350-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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@ -2012,153 +2152,6 @@ qup_i2c19_default: qup-i2c19-default-state {
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};
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};
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};
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};
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rng: rng@10d3000 {
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compatible = "qcom,prng-ee";
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reg = <0 0x010d3000 0 0x1000>;
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clocks = <&rpmhcc RPMH_HWKM_CLK>;
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clock-names = "core";
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};
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ufs_mem_hc: ufshc@1d84000 {
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compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0 0x01d84000 0 0x3000>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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power-domains = <&gcc UFS_PHY_GDSC>;
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iommus = <&apps_smmu 0xe0 0x0>;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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status = "disabled";
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};
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ufs_mem_phy: phy@1d87000 {
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compatible = "qcom,sm8350-qmp-ufs-phy";
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reg = <0 0x01d87000 0 0x1c4>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "ref",
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"ref_aux";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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resets = <&ufs_mem_hc 0>;
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reset-names = "ufsphy";
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status = "disabled";
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ufs_mem_phy_lanes: phy@1d87400 {
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reg = <0 0x01d87400 0 0x188>,
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<0 0x01d87600 0 0x200>,
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<0 0x01d87c00 0 0x200>,
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<0 0x01d87800 0 0x188>,
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<0 0x01d87a00 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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slpi: remoteproc@5c00000 {
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compatible = "qcom,sm8350-slpi-pas";
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reg = <0 0x05c00000 0 0x4000>;
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interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
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<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SM8350_LCX>,
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<&rpmhpd SM8350_LMX>;
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power-domain-names = "lcx", "lmx";
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memory-region = <&pil_slpi_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_slpi_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_SLPI
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "slpi";
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qcom,remote-pid = <3>;
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fastrpc {
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compatible = "qcom,fastrpc";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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label = "sdsp";
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qcom,non-secure-domain;
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#address-cells = <1>;
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#size-cells = <0>;
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compute-cb@1 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <1>;
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iommus = <&apps_smmu 0x0541 0x0>;
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};
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compute-cb@2 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <2>;
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iommus = <&apps_smmu 0x0542 0x0>;
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};
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compute-cb@3 {
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compatible = "qcom,fastrpc-compute-cb";
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reg = <3>;
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iommus = <&apps_smmu 0x0543 0x0>;
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/* note: shared-cb = <4> in downstream */
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};
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};
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};
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};
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sdhc_2: mmc@8804000 {
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sdhc_2: mmc@8804000 {
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compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
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compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x08804000 0 0x1000>;
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reg = <0 0x08804000 0 0x1000>;
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@ -2307,6 +2300,13 @@ system-cache-controller@9200000 {
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reg-names = "llcc_base", "llcc_broadcast_base";
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
compute_noc: interconnect@a0c0000 {
|
||||||
|
compatible = "qcom,sm8350-compute-noc";
|
||||||
|
reg = <0 0x0a0c0000 0 0xa180>;
|
||||||
|
#interconnect-cells = <2>;
|
||||||
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||||
|
};
|
||||||
|
|
||||||
usb_1: usb@a6f8800 {
|
usb_1: usb@a6f8800 {
|
||||||
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
|
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
|
||||||
reg = <0 0x0a6f8800 0 0x400>;
|
reg = <0 0x0a6f8800 0 0x400>;
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue