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[ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem
Patch from Catalin Marinas ARM1136 erratum 371025 (category 2) specifies that, under rare conditions, an invalidate I-cache by MVA (line or range) operation can fail to invalidate a cache line. The recommended workaround is to either invalidate the entire I-cache or invalidate the range by set/way rather than MVA. Note that for a 16K cache size, invalidating a 4K page by set/way is equivalent to invalidating the entire I-cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
e7fcdb79ec
commit
141fa40cff
2 changed files with 8 additions and 5 deletions
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@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range)
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#ifdef HARVARD_CACHE
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bic r0, r0, #CACHE_LINE_SIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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#ifdef HARVARD_CACHE
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mov r0, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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#else
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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#endif
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mov pc, lr
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@ -24,14 +24,16 @@
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static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
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{
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unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
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const int zero = 0;
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set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
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flush_tlb_kernel_page(to);
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asm( "mcrr p15, 0, %1, %0, c14\n"
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" mcrr p15, 0, %1, %0, c5\n"
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" mcr p15, 0, %2, c7, c10, 4\n"
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" mcr p15, 0, %2, c7, c5, 0\n"
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:
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: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
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: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
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: "cc");
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}
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