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iommu/arm-smmu: Ensure that page-table updates are visible before TLBI
commit7d321bd354
upstream. The IO-pgtable code relies on the driver TLB invalidation callbacks to ensure that all page-table updates are visible to the IOMMU page-table walker. In the case that the page-table walker is cache-coherent, we cannot rely on an implicit DSB from the DMA-mapping code, so we must ensure that we execute a DSB in our tlb_add_flush() callback prior to triggering the invalidation. Cc: <stable@vger.kernel.org> Cc: Robin Murphy <robin.murphy@arm.com> Fixes:2df7a25ce4
("iommu/arm-smmu: Clean up DMA API usage") Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 6 additions and 0 deletions
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@ -469,6 +469,9 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
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bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
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void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
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if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
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wmb();
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if (stage1) {
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reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
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@ -510,6 +513,9 @@ static void arm_smmu_tlb_inv_vmid_nosync(unsigned long iova, size_t size,
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struct arm_smmu_domain *smmu_domain = cookie;
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void __iomem *base = ARM_SMMU_GR0(smmu_domain->smmu);
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if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
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wmb();
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writel_relaxed(smmu_domain->cfg.vmid, base + ARM_SMMU_GR0_TLBIVMID);
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}
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