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On 24K we did always disable cache parity protection - obviously not
the greatest thing to do. Try to enable parity protection, check if we actually succeeded and print a message about the outcome of this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 5 additions and 9 deletions
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@ -736,16 +736,12 @@ static inline void parity_protection_init(void)
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{
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switch (current_cpu_data.cputype) {
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case CPU_24K:
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/* 24K cache parity not currently implemented in FPGA */
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printk(KERN_INFO "Disable cache parity protection for "
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"MIPS 24K CPU.\n");
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write_c0_ecc(read_c0_ecc() & ~0x80000000);
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break;
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case CPU_5KC:
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/* Set the PE bit (bit 31) in the c0_ecc register. */
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printk(KERN_INFO "Enable cache parity protection for "
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"MIPS 5KC/24K CPUs.\n");
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write_c0_ecc(read_c0_ecc() | 0x80000000);
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write_c0_ecc(0x80000000);
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back_to_back_c0_hazard();
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/* Set the PE bit (bit 31) in the c0_errctl register. */
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printk(KERN_INFO "Cache parity protection %sabled\n",
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(read_c0_ecc() & 0x80000000) ? "en" : "dis");
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break;
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case CPU_20KC:
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case CPU_25KF:
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