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net: dt-bindings: dwmac: Convert mediatek-dwmac to DT schema
Convert mediatek-dwmac to DT schema, and delete old mediatek-dwmac.txt.
And there are some changes in .yaml than .txt, others almost keep the same:
1. compatible "const: snps,dwmac-4.20".
2. delete "snps,reset-active-low;" in example, since driver remove this
property long ago.
3. add "snps,reset-delay-us = <0 10000 10000>" in example.
4. the example is for rgmii interface, keep related properties only.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Biao Huang
David S. Miller
parent
79e1177809
commit
150b6adda6
2 changed files with 155 additions and 91 deletions
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@ -1,91 +0,0 @@
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MediaTek DWMAC glue layer controller
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This file documents platform glue layer for stmmac.
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Please see stmmac.txt for the other unchanged properties.
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The device node has following properties.
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Required properties:
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- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the MAC interrupts
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- interrupt-names: Should contain a list of interrupt names corresponding to
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the interrupts in the interrupts property, if available.
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Should be "macirq" for the main MAC IRQ
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- clocks: Must contain a phandle for each entry in clock-names.
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- clock-names: The name of the clock listed in the clocks property. These are
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"axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
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- mac-address: See ethernet.txt in the same directory
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- phy-mode: See ethernet.txt in the same directory
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- mediatek,pericfg: A phandle to the syscon node that control ethernet
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interface and timing delay.
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Optional properties:
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- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
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It should be defined for RGMII/MII interface.
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It should be defined for RMII interface when the reference clock is from MT2712 SoC.
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- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
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It should be defined for RGMII/MII interface.
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It should be defined for RMII interface.
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Both delay properties need to be a multiple of 170 for RGMII interface,
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or will round down. Range 0~31*170.
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Both delay properties need to be a multiple of 550 for MII/RMII interface,
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or will round down. Range 0~31*550.
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- mediatek,rmii-rxc: boolean property, if present indicates that the RMII
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reference clock, which is from external PHYs, is connected to RXC pin
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on MT2712 SoC.
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Otherwise, is connected to TXC pin.
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- mediatek,rmii-clk-from-mac: boolean property, if present indicates that
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MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
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- mediatek,txc-inverse: boolean property, if present indicates that
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1. tx clock will be inversed in MII/RGMII case,
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2. tx clock inside MAC will be inversed relative to reference clock
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which is from external PHYs in RMII case, and it rarely happen.
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3. the reference clock, which outputs to TXC pin will be inversed in RMII case
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when the reference clock is from MT2712 SoC.
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- mediatek,rxc-inverse: boolean property, if present indicates that
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1. rx clock will be inversed in MII/RGMII case.
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2. reference clock will be inversed when arrived at MAC in RMII case, when
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the reference clock is from external PHYs.
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3. the inside clock, which be sent to MAC, will be inversed in RMII case when
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the reference clock is from MT2712 SoC.
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- assigned-clocks: mac_main and ptp_ref clocks
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- assigned-clock-parents: parent clocks of the assigned clocks
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Example:
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eth: ethernet@1101c000 {
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compatible = "mediatek,mt2712-gmac";
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reg = <0 0x1101c000 0 0x1300>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "macirq";
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phy-mode ="rgmii-rxid";
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mac-address = [00 55 7b b5 7d f7];
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clock-names = "axi",
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"apb",
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"mac_main",
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"ptp_ref",
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"rmii_internal";
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clocks = <&pericfg CLK_PERI_GMAC>,
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<&pericfg CLK_PERI_GMAC_PCLK>,
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<&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
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assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
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<&topckgen CLK_TOP_APLL1_D3>,
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<&topckgen CLK_TOP_ETHERPLL_50M>;
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power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
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mediatek,pericfg = <&pericfg>;
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mediatek,tx-delay-ps = <1530>;
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mediatek,rx-delay-ps = <1530>;
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mediatek,rmii-rxc;
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mediatek,txc-inverse;
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mediatek,rxc-inverse;
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snps,txpbl = <1>;
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snps,rxpbl = <1>;
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snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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};
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155
Documentation/devicetree/bindings/net/mediatek-dwmac.yaml
Normal file
155
Documentation/devicetree/bindings/net/mediatek-dwmac.yaml
Normal file
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@ -0,0 +1,155 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek DWMAC glue layer controller
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maintainers:
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- Biao Huang <biao.huang@mediatek.com>
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description:
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This file documents platform glue layer for stmmac.
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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select:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt2712-gmac
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required:
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- compatible
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allOf:
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- $ref: "snps,dwmac.yaml#"
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt2712-gmac
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- const: snps,dwmac-4.20a
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clocks:
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items:
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- description: AXI clock
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- description: APB clock
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- description: MAC Main clock
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- description: PTP clock
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- description: RMII reference clock provided by MAC
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clock-names:
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items:
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- const: axi
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- const: apb
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- const: mac_main
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- const: ptp_ref
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- const: rmii_internal
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mediatek,pericfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The phandle to the syscon node that control ethernet
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interface and timing delay.
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mediatek,tx-delay-ps:
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description:
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The internal TX clock delay (provided by this driver) in nanoseconds.
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For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
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or will round down. Range 0~31*170.
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For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
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or will round down. Range 0~31*550.
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mediatek,rx-delay-ps:
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description:
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The internal RX clock delay (provided by this driver) in nanoseconds.
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For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
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or will round down. Range 0~31*170.
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For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
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or will round down. Range 0~31*550.
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mediatek,rmii-rxc:
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type: boolean
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description:
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If present, indicates that the RMII reference clock, which is from external
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PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
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mediatek,rmii-clk-from-mac:
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type: boolean
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description:
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If present, indicates that MAC provides the RMII reference clock, which
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outputs to TXC pin only.
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mediatek,txc-inverse:
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type: boolean
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description:
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If present, indicates that
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1. tx clock will be inversed in MII/RGMII case,
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2. tx clock inside MAC will be inversed relative to reference clock
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which is from external PHYs in RMII case, and it rarely happen.
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3. the reference clock, which outputs to TXC pin will be inversed in RMII case
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when the reference clock is from MAC.
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mediatek,rxc-inverse:
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type: boolean
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description:
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If present, indicates that
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1. rx clock will be inversed in MII/RGMII case.
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2. reference clock will be inversed when arrived at MAC in RMII case, when
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the reference clock is from external PHYs.
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3. the inside clock, which be sent to MAC, will be inversed in RMII case when
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the reference clock is from MAC.
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- phy-mode
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- mediatek,pericfg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt2712-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt2712-power.h>
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eth: ethernet@1101c000 {
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compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
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reg = <0x1101c000 0x1300>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "macirq";
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phy-mode ="rgmii-rxid";
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mac-address = [00 55 7b b5 7d f7];
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clock-names = "axi",
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"apb",
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"mac_main",
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"ptp_ref",
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"rmii_internal";
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clocks = <&pericfg CLK_PERI_GMAC>,
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<&pericfg CLK_PERI_GMAC_PCLK>,
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<&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
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assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
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<&topckgen CLK_TOP_APLL1_D3>,
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<&topckgen CLK_TOP_ETHERPLL_50M>;
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power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
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mediatek,pericfg = <&pericfg>;
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mediatek,tx-delay-ps = <1530>;
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snps,txpbl = <1>;
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snps,rxpbl = <1>;
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snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
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snps,reset-delays-us = <0 10000 10000>;
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};
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