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i2c: mpc: Interrupt driven transfer
The fsl-i2c controller will generate an interrupt after every byte transferred. Make use of this interrupt to drive a state machine which allows the next part of a transfer to happen as soon as the interrupt is received. This is particularly helpful with SMBUS devices like the LM81 which will timeout if we take too long between bytes in a transfer. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Chris Packham
Wolfram Sang
parent
e5b2e3e742
commit
1538d82f46
1 changed files with 239 additions and 187 deletions
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@ -58,11 +58,35 @@
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#define CSR_MIF 0x02
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#define CSR_RXAK 0x01
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enum mpc_i2c_action {
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MPC_I2C_ACTION_START = 1,
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MPC_I2C_ACTION_RESTART,
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MPC_I2C_ACTION_READ_BEGIN,
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MPC_I2C_ACTION_READ_BYTE,
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MPC_I2C_ACTION_WRITE,
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MPC_I2C_ACTION_STOP,
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__MPC_I2C_ACTION_CNT
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};
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static const char * const action_str[] = {
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"invalid",
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"start",
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"restart",
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"read begin",
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"read",
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"write",
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"stop",
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};
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static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
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struct mpc_i2c {
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struct device *dev;
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void __iomem *base;
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u32 interrupt;
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wait_queue_head_t queue;
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wait_queue_head_t waitq;
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spinlock_t lock;
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struct i2c_adapter adap;
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int irq;
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u32 real_clk;
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@ -70,6 +94,16 @@ struct mpc_i2c {
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u8 fdr, dfsrr;
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#endif
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struct clk *clk_per;
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u32 cntl_bits;
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enum mpc_i2c_action action;
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struct i2c_msg *msgs;
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int num_msgs;
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int curr_msg;
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u32 byte_posn;
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u32 block;
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int rc;
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int expect_rxack;
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};
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struct mpc_i2c_divider {
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@ -86,19 +120,6 @@ static inline void writeccr(struct mpc_i2c *i2c, u32 x)
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writeb(x, i2c->base + MPC_I2C_CR);
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}
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static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
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{
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struct mpc_i2c *i2c = dev_id;
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if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
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/* Read again to allow register to stabilise */
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i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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wake_up(&i2c->queue);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
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* the bus, because it wants to send ACK.
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* Following sequence of enabling/disabling and sending start/stop generates
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@ -121,45 +142,6 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
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}
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}
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static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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{
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u32 cmd_err;
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int result;
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result = wait_event_timeout(i2c->queue,
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(i2c->interrupt & CSR_MIF), timeout);
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if (unlikely(!(i2c->interrupt & CSR_MIF))) {
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dev_dbg(i2c->dev, "wait timeout\n");
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writeccr(i2c, 0);
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result = -ETIMEDOUT;
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}
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cmd_err = i2c->interrupt;
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i2c->interrupt = 0;
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if (result < 0)
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return result;
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if (!(cmd_err & CSR_MCF)) {
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dev_dbg(i2c->dev, "unfinished\n");
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return -EIO;
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}
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if (cmd_err & CSR_MAL) {
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dev_dbg(i2c->dev, "MAL\n");
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return -EAGAIN;
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}
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if (writing && (cmd_err & CSR_RXAK)) {
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dev_dbg(i2c->dev, "No RXAK\n");
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/* generate stop */
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writeccr(i2c, CCR_MEN);
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return -ENXIO;
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}
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return 0;
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}
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#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
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static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
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{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
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@ -434,168 +416,209 @@ static void mpc_i2c_setup_8xxx(struct device_node *node,
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}
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#endif /* CONFIG_FSL_SOC */
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static void mpc_i2c_start(struct mpc_i2c *i2c)
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static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
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{
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/* Clear arbitration */
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writeb(0, i2c->base + MPC_I2C_SR);
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/* Start with MEN */
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writeccr(i2c, CCR_MEN);
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i2c->rc = rc;
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i2c->block = 0;
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i2c->cntl_bits = CCR_MEN;
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writeccr(i2c, i2c->cntl_bits);
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wake_up(&i2c->waitq);
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}
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static void mpc_i2c_stop(struct mpc_i2c *i2c)
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static void mpc_i2c_do_action(struct mpc_i2c *i2c)
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{
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writeccr(i2c, CCR_MEN);
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}
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struct i2c_msg *msg = &i2c->msgs[i2c->curr_msg];
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int dir = 0;
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int recv_len = 0;
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u8 byte;
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static int mpc_write(struct mpc_i2c *i2c, int target,
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const u8 *data, int length, int restart)
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{
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int i, result;
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unsigned timeout = i2c->adap.timeout;
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u32 flags = restart ? CCR_RSTA : 0;
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dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
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/* Start as master */
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
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/* Write target byte */
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writeb((target << 1), i2c->base + MPC_I2C_DR);
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i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
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result = i2c_wait(i2c, timeout, 1);
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if (result < 0)
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return result;
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if (msg->flags & I2C_M_RD)
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dir = 1;
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if (msg->flags & I2C_M_RECV_LEN)
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recv_len = 1;
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for (i = 0; i < length; i++) {
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/* Write data byte */
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writeb(data[i], i2c->base + MPC_I2C_DR);
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switch (i2c->action) {
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case MPC_I2C_ACTION_RESTART:
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i2c->cntl_bits |= CCR_RSTA;
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fallthrough;
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result = i2c_wait(i2c, timeout, 1);
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if (result < 0)
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return result;
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}
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case MPC_I2C_ACTION_START:
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i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
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writeccr(i2c, i2c->cntl_bits);
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writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
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i2c->expect_rxack = 1;
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i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
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break;
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return 0;
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}
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case MPC_I2C_ACTION_READ_BEGIN:
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if (msg->len) {
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if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
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i2c->cntl_bits |= CCR_TXAK;
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static int mpc_read(struct mpc_i2c *i2c, int target,
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u8 *data, int length, int restart, bool recv_len)
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{
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unsigned timeout = i2c->adap.timeout;
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int i, result;
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u32 flags = restart ? CCR_RSTA : 0;
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writeccr(i2c, i2c->cntl_bits);
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/* Dummy read */
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readb(i2c->base + MPC_I2C_DR);
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}
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i2c->action = MPC_I2C_ACTION_READ_BYTE;
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break;
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/* Switch to read - restart */
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
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/* Write target address byte - this time with the read flag set */
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writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
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result = i2c_wait(i2c, timeout, 1);
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if (result < 0)
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return result;
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if (length) {
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if (length == 1 && !recv_len)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
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else
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
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/* Dummy read */
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readb(i2c->base + MPC_I2C_DR);
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}
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for (i = 0; i < length; i++) {
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u8 byte;
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result = i2c_wait(i2c, timeout, 0);
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if (result < 0)
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return result;
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/*
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* For block reads, we have to know the total length (1st byte)
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* before we can determine if we are done.
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*/
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if (i || !recv_len) {
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/* Generate txack on next to last byte */
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if (i == length - 2)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
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| CCR_TXAK);
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case MPC_I2C_ACTION_READ_BYTE:
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if (i2c->byte_posn || !recv_len) {
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/* Generate Tx ACK on next to last byte */
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if (i2c->byte_posn == msg->len - 2)
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i2c->cntl_bits |= CCR_TXAK;
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/* Do not generate stop on last byte */
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if (i == length - 1)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
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| CCR_MTX);
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if (i2c->byte_posn == msg->len - 1)
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i2c->cntl_bits |= CCR_MTX;
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writeccr(i2c, i2c->cntl_bits);
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}
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byte = readb(i2c->base + MPC_I2C_DR);
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/*
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* Adjust length if first received byte is length.
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* The length is 1 length byte plus actually data length
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*/
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if (i == 0 && recv_len) {
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if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
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return -EPROTO;
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length += byte;
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if (i2c->byte_posn == 0 && recv_len) {
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if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
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mpc_i2c_finish(i2c, -EPROTO);
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return;
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}
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msg->len += byte;
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/*
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* For block reads, generate txack here if data length
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* For block reads, generate Tx ACK here if data length
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* is 1 byte (total length is 2 bytes).
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*/
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if (length == 2)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
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| CCR_TXAK);
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if (msg->len == 2) {
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i2c->cntl_bits |= CCR_TXAK;
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writeccr(i2c, i2c->cntl_bits);
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}
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}
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data[i] = byte;
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dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
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msg->buf[i2c->byte_posn++] = byte;
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break;
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case MPC_I2C_ACTION_WRITE:
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dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
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msg->buf[i2c->byte_posn]);
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writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
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i2c->expect_rxack = 1;
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break;
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case MPC_I2C_ACTION_STOP:
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mpc_i2c_finish(i2c, 0);
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break;
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default:
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WARN(1, "Unexpected action %d\n", i2c->action);
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break;
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}
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return length;
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if (msg->len == i2c->byte_posn) {
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i2c->curr_msg++;
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i2c->byte_posn = 0;
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if (i2c->curr_msg == i2c->num_msgs) {
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i2c->action = MPC_I2C_ACTION_STOP;
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/*
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* We don't get another interrupt on read so
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* finish the transfer now
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*/
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if (dir)
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mpc_i2c_finish(i2c, 0);
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} else {
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i2c->action = MPC_I2C_ACTION_RESTART;
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}
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}
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}
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static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
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{
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struct i2c_msg *pmsg;
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int i;
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int ret = 0;
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unsigned long orig_jiffies = jiffies;
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struct mpc_i2c *i2c = i2c_get_adapdata(adap);
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spin_lock(&i2c->lock);
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mpc_i2c_start(i2c);
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/* Allow bus up to 1s to become not busy */
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while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
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if (signal_pending(current)) {
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dev_dbg(i2c->dev, "Interrupted\n");
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writeccr(i2c, 0);
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return -EINTR;
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}
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if (time_after(jiffies, orig_jiffies + HZ)) {
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u8 status = readb(i2c->base + MPC_I2C_SR);
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dev_dbg(i2c->dev, "timeout\n");
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if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
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writeb(status & ~CSR_MAL,
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i2c->base + MPC_I2C_SR);
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i2c_recover_bus(&i2c->adap);
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}
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return -EIO;
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}
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schedule();
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if (!(status & CSR_MCF)) {
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dev_dbg(i2c->dev, "unfinished\n");
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mpc_i2c_finish(i2c, -EIO);
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goto out;
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}
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for (i = 0; ret >= 0 && i < num; i++) {
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pmsg = &msgs[i];
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dev_dbg(i2c->dev,
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"Doing %s %d bytes to 0x%02x - %d of %d messages\n",
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pmsg->flags & I2C_M_RD ? "read" : "write",
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pmsg->len, pmsg->addr, i + 1, num);
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if (pmsg->flags & I2C_M_RD) {
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bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
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ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
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recv_len);
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if (recv_len && ret > 0)
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pmsg->len = ret;
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} else {
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ret =
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mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
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}
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if (status & CSR_MAL) {
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dev_dbg(i2c->dev, "arbitration lost\n");
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mpc_i2c_finish(i2c, -EAGAIN);
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goto out;
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}
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mpc_i2c_stop(i2c); /* Initiate STOP */
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if (i2c->expect_rxack && (status & CSR_RXAK)) {
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dev_dbg(i2c->dev, "no Rx ACK\n");
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mpc_i2c_finish(i2c, -ENXIO);
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goto out;
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}
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i2c->expect_rxack = 0;
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mpc_i2c_do_action(i2c);
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out:
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spin_unlock(&i2c->lock);
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}
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static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
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{
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struct mpc_i2c *i2c = dev_id;
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u8 status;
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status = readb(i2c->base + MPC_I2C_SR);
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if (status & CSR_MIF) {
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writeb(0, i2c->base + MPC_I2C_SR);
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mpc_i2c_do_intr(i2c, status);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
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{
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long time_left;
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time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
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if (!time_left)
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return -ETIMEDOUT;
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if (time_left < 0)
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return time_left;
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return 0;
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}
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static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
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{
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unsigned long orig_jiffies;
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unsigned long flags;
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int ret;
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|
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spin_lock_irqsave(&i2c->lock, flags);
|
||||
|
||||
i2c->curr_msg = 0;
|
||||
i2c->rc = 0;
|
||||
i2c->byte_posn = 0;
|
||||
i2c->block = 1;
|
||||
i2c->action = MPC_I2C_ACTION_START;
|
||||
|
||||
i2c->cntl_bits = CCR_MEN | CCR_MIEN;
|
||||
writeb(0, i2c->base + MPC_I2C_SR);
|
||||
writeccr(i2c, i2c->cntl_bits);
|
||||
|
||||
mpc_i2c_do_action(i2c);
|
||||
|
||||
spin_unlock_irqrestore(&i2c->lock, flags);
|
||||
|
||||
ret = mpc_i2c_wait_for_completion(i2c);
|
||||
if (ret)
|
||||
i2c->rc = ret;
|
||||
|
||||
if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
|
||||
i2c_recover_bus(&i2c->adap);
|
||||
|
||||
orig_jiffies = jiffies;
|
||||
/* Wait until STOP is seen, allow up to 1 s */
|
||||
while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
|
||||
|
|
@ -612,7 +635,35 @@ static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|||
}
|
||||
cond_resched();
|
||||
}
|
||||
return (ret < 0) ? ret : num;
|
||||
|
||||
return i2c->rc;
|
||||
}
|
||||
|
||||
static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
int rc, ret = num;
|
||||
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
|
||||
int i;
|
||||
|
||||
dev_dbg(i2c->dev, "num = %d\n", num);
|
||||
for (i = 0; i < num; i++)
|
||||
dev_dbg(i2c->dev, " addr = %02x, flags = %02x, len = %d, %*ph\n",
|
||||
msgs[i].addr, msgs[i].flags, msgs[i].len,
|
||||
msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
|
||||
msgs[i].buf);
|
||||
|
||||
WARN_ON(i2c->msgs != NULL);
|
||||
i2c->msgs = msgs;
|
||||
i2c->num_msgs = num;
|
||||
|
||||
rc = mpc_i2c_execute_msg(i2c);
|
||||
if (rc < 0)
|
||||
ret = rc;
|
||||
|
||||
i2c->num_msgs = 0;
|
||||
i2c->msgs = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 mpc_functionality(struct i2c_adapter *adap)
|
||||
|
|
@ -667,7 +718,8 @@ static int fsl_i2c_probe(struct platform_device *op)
|
|||
|
||||
i2c->dev = &op->dev; /* for debug and error output */
|
||||
|
||||
init_waitqueue_head(&i2c->queue);
|
||||
init_waitqueue_head(&i2c->waitq);
|
||||
spin_lock_init(&i2c->lock);
|
||||
|
||||
i2c->base = devm_platform_ioremap_resource(op, 0);
|
||||
if (IS_ERR(i2c->base)) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue