From abe38831a5ff77336df008cbc831d7302bb51e14 Mon Sep 17 00:00:00 2001 From: Delphine CC Chiu Date: Fri, 11 Nov 2022 11:48:25 +0800 Subject: [PATCH 01/14] dt-bindings: arm: aspeed: add Facebook Greatlakes board Document the new compatibles used on Facebook Greatlakes Signed-off-by: Delphine CC Chiu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221111034828.2377-2-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 73f272664e83..8ef74b941e88 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -78,6 +78,7 @@ properties: - facebook,cloudripper-bmc - facebook,elbert-bmc - facebook,fuji-bmc + - facebook,greatlakes-bmc - ibm,everest-bmc - ibm,rainier-bmc - ibm,tacoma-bmc From c3769d87f3fc1773dfadbeb63f4e3b3110159587 Mon Sep 17 00:00:00 2001 From: Delphine CC Chiu Date: Fri, 11 Nov 2022 11:48:26 +0800 Subject: [PATCH 02/14] ARM: dts: aspeed: greatlakes: Add Facebook greatlakes (AST2600) BMC Add linux device tree entry related to greatlakes specific devices connected to BMC SoC. Signed-off-by: Delphine CC Chiu Link: https://lore.kernel.org/r/20221111034828.2377-3-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../dts/aspeed-bmc-facebook-greatlakes.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d08a3c450ce7..2a5a24bea422 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1605,6 +1605,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-elbert.dtb \ aspeed-bmc-facebook-fuji.dtb \ aspeed-bmc-facebook-galaxy100.dtb \ + aspeed-bmc-facebook-greatlakes.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts new file mode 100644 index 000000000000..8c05bd56ce1e --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Facebook Greatlakes BMC"; + compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 2>, <&adc1 3>, <&adc1 4>, + <&adc1 5>, <&adc1 6>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + no-hw-checksum; + use-ncsi; + mlx,multi-host; + ncsi-ctrl,start-redo-probe; + ncsi-ctrl,no-channel-monitor; + ncsi-package = <1>; + ncsi-channel = <1>; + ncsi-rexmit = <1>; + ncsi-timeout = <2>; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + }; +}; + +&i2c0 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c1 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c2 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + // NIC EEPROM + eeprom@50 { + compatible = "st,24c32"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c12 { + status = "okay"; + temperature-sensor@4f { + compatible = "lm75"; + reg = <0x4f>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default + &pinctrl_adc11_default &pinctrl_adc12_default + &pinctrl_adc13_default &pinctrl_adc14_default>; +}; + + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; +}; From 2ee2a66ae5092281e3b3e6ddda91734dbb54e527 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Jan 2023 15:19:17 +0300 Subject: [PATCH 03/14] ARM: dts: aspeed: ethanolx: Enable VUART Enable Virtual UART (VUART) module. This module provides virtual serial communication capabilities between host CPU and BMC and can be used for the Serial-Over-LAN (SoL) feature implementation. Signed-off-by: Konstantin Aladyshev Link: https://lore.kernel.org/r/20230111121917.1636-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 6406a0f080ee..93d395df1f2a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -5,6 +5,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "AMD EthanolX BMC"; @@ -261,6 +262,12 @@ &lpc_ctrl { status = "okay"; }; +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; + &pwm_tacho { status = "okay"; pinctrl-names = "default"; From a7b322d164cffce24b69fa3e49a3ed9eebd01238 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Jan 2023 14:32:08 +0300 Subject: [PATCH 04/14] ARM: dts: aspeed: ethanolx: Correct EEPROM device name BMC on the EthanolX board uses 24LC128 EEPROM chip for the configuration settings. The correct compatible string for this chip is "atmel,24c128". Signed-off-by: Konstantin Aladyshev Link: https://lore.kernel.org/r/20230111113208.964-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 93d395df1f2a..f1f9c3f7e63f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -161,7 +161,7 @@ &i2c2 { &i2c3 { status = "okay"; eeprom@50 { - compatible = "atmel,24c256"; + compatible = "atmel,24c128"; reg = <0x50>; pagesize = <64>; }; From 59e099e877d41b3a3ba79e6be425b73965f1aee9 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Jan 2023 13:01:04 +0300 Subject: [PATCH 05/14] ARM: dts: aspeed: ethanolx: Add label for the master partition Add label "bmc" for the flash master partition. The master partition is required for the firmware update in the OpenBMC ecosystem. Signed-off-by: Konstantin Aladyshev Link: https://lore.kernel.org/r/20230111100105.707-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index f1f9c3f7e63f..e1f97721ada5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -59,6 +59,7 @@ &fmc { flash@0 { status = "okay"; m25p,fast-read; + label = "bmc"; #include "openbmc-flash-layout.dtsi" }; }; From 9664e1ba47fd27e2f21132ba6798c34adcaea288 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Jan 2023 14:52:27 +0300 Subject: [PATCH 06/14] ARM: dts: aspeed: ethanolx: Enable CTS/RTS pins on UART1 BMC UART1 is connected to the P0 CPU UART1. As the connection has CTS and RTS signals, enable these functions on the BMC side. Signed-off-by: Konstantin Aladyshev Link: https://lore.kernel.org/r/20230111115227.1357-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index e1f97721ada5..90feac5ec628 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -80,7 +80,9 @@ &uart1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ncts1_default>; }; &uart5 { From 03d24e12749281f51545c9011fc953ac844df413 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Jan 2023 14:39:34 +0300 Subject: [PATCH 07/14] ARM: dts: aspeed: ethanolx: Add BIOS flash chip Add a BIOS flash chip to the DTS to open a possibility to reflash the main CPU BIOS from the BMC. Signed-off-by: Konstantin Aladyshev Link: https://lore.kernel.org/r/20230111113934.1176-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 90feac5ec628..6bded774c457 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -64,6 +64,17 @@ flash@0 { }; }; +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; &mac0 { status = "okay"; From 107fb95f7ba14f38003218c7e340d8431c2e1d50 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 26 Dec 2022 13:45:34 +0800 Subject: [PATCH 08/14] ARM: dts: aspeed: bletchley: Rename flash1 label In OpenBMC phosphor-software-manager uses "alt-bmc" for the secondary flash label. Rename flash1 label to "alt-bmc" to support the dual image feature in OpenBMC. Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Link: https://lore.kernel.org/r/20221226054535.2836110-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index a619eec70633..791f83aaac50 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -307,7 +307,7 @@ flash@0 { flash@1 { status = "okay"; m25p,fast-read; - label = "flash1"; + label = "alt-bmc"; spi-max-frequency = <50000000>; }; }; From c021d9fe410adadf35a835098073e4528f2db728 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 26 Dec 2022 13:45:35 +0800 Subject: [PATCH 09/14] ARM: dts: aspeed: bletchley: Enable wdtrst1 Enable WDTRST1 external signal to send a reset pulse to peripherals while BMC reset. Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Link: https://lore.kernel.org/r/20221226054535.2836110-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 791f83aaac50..e899de681f47 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -1064,3 +1064,14 @@ pinctrl_gpiov2_unbiased_default: gpiov2 { bias-disable; }; }; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; From 8803d9438ef65c96b03ae95472e19b3ac072c930 Mon Sep 17 00:00:00 2001 From: Ali El-Haj-Mahmoud Date: Wed, 18 Jan 2023 10:00:30 -0500 Subject: [PATCH 10/14] arm: dts: aspeed: tyan s8036: Enable kcs interrupts When the BIOS is built with kcs interrupts enabled, not enabling interrupts on the BMC results in very poor IPMI performance. The other way around (BIOS with interrupts disabled, BMC with interrupts enabled) doesn't suffer degraded IPMI performance. Enabling interrupts on the BMC covers both scenarios, and should be the default. TESTED: manually verified IPMI performance when BIOS is built with and without KCS interrupts. Signed-off-by: Ali El-Haj-Mahmoud Link: https://lore.kernel.org/r/20230118150030.2079226-1-aaelhaj@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts index 708ee78e4b83..f6c4549c0ac4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts @@ -364,6 +364,7 @@ &kcs1 { &kcs3 { status = "okay"; aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; /* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ From 4fa180f7fc1921e235f80e4672c80b560b4946c7 Mon Sep 17 00:00:00 2001 From: Jordan Chang Date: Thu, 19 Jan 2023 18:21:00 +0800 Subject: [PATCH 11/14] dt-bindings: vendor-prefixes: Add prefix for Ufi Space Add a vendor prefix for Ufi Space (https://www.ufispace.com). Signed-off-by: Jordan Chang Link: https://lore.kernel.org/r/20230119102102.73414-2-jordan.chang@ufispace.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 70ffb3780621..51be4a8247ff 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1372,6 +1372,8 @@ patternProperties: description: uCRobotics "^udoo,.*": description: Udoo + "^ufispace,.*": + description: Ufi Space Co., Ltd. "^ugoos,.*": description: Ugoos Industrial Co., Ltd. "^uniwest,.*": From 64e4f2412f548a8537b9da44267f7490e294edf8 Mon Sep 17 00:00:00 2001 From: Jordan Chang Date: Thu, 19 Jan 2023 18:21:01 +0800 Subject: [PATCH 12/14] dt-bindings: arm: aspeed: document Ufispace NCPLite BMC Document Ufispace NCPLite board compatible. Signed-off-by: Jordan Chang Link: https://lore.kernel.org/r/20230119102102.73414-3-jordan.chang@ufispace.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 8ef74b941e88..e0eff4c05879 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -86,6 +86,7 @@ properties: - jabil,rbp-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc + - ufispace,ncplite-bmc - const: aspeed,ast2600 additionalProperties: true From 28cfb03afcb20a841e96e821ba20870a7c437034 Mon Sep 17 00:00:00 2001 From: Jordan Chang Date: Thu, 19 Jan 2023 18:21:02 +0800 Subject: [PATCH 13/14] ARM: dts: aspeed: Add device tree for Ufispace NCPLite BMC Add initial version of device tree for Ufispace NCPlite platform which is equipped with AST2600-based BMC. Signed-off-by: Jordan Chang Link: https://lore.kernel.org/r/20230119102102.73414-4-jordan.chang@ufispace.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/aspeed-bmc-ufispace-ncplite.dts | 360 ++++++++++++++++++ 2 files changed, 361 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2a5a24bea422..9df89ab749fd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1642,6 +1642,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ aspeed-bmc-tyan-s8036.dtb \ + aspeed-bmc-ufispace-ncplite.dtb \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts new file mode 100644 index 000000000000..7ab29129d1e4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2022 Ufispace Co., Ltd. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Ufispace NCPLite BMC"; + compatible = "ufispace,ncplite-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + fan-status-int-l { + label = "fan-status-int-l"; + gpios = <&gpio0 ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + allpwr-good { + label = "allpwr-good"; + gpios = <&gpio0 ASPEED_GPIO(V, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + psu0-alert-n { + label = "psu0-alert-n"; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1-alert-n { + label = "psu1-alert-n"; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + int-thermal-alert { + label = "int-thermal-alert"; + gpios = <&gpio0 ASPEED_GPIO(P, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + cpu-caterr-l { + label = "cpu-caterr-l"; + gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + cpu-thermtrip-l { + label = "cpu-thermtrip-l"; + gpios = <&gpio0 ASPEED_GPIO(V, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu0-presence-l { + label = "psu0-presence-l"; + gpios = <&gpio0 ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1-presence-l { + label = "psu1-presence-l"; + gpios = <&gpio0 ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu0-power-ok { + label = "psu0-power-ok"; + gpios = <&gpio0 ASPEED_GPIO(M, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + psu1-power-ok { + label = "psu1-power-ok"; + gpios = <&gpio0 ASPEED_GPIO(M, 5) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&fan_ioexp 2 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&fan_ioexp 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&fan_ioexp 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&fan_ioexp 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + }; +}; + +&mac2 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_reset { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&peci0 { + status = "okay"; +}; + +&udc { + status = "okay"; +}; + +&adc0 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + lm75@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + lm86@4c { + compatible = "national,lm86"; + reg = <0x4c>; + }; +}; + +&i2c2 { + status = "okay"; + + lm75@4f { + cpmpatible = "national,lm75"; + reg = <0x4f>; + }; + + fan_ioexp: pca9535@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","","presence-fan0","", + "","","presence-fan1","", + "","","presence-fan2","", + "","","presence-fan3",""; + }; +}; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c4 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <1>; + }; +}; + +&i2c5 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <1>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&gpio0 { + status = "okay"; + + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "CPU_PWRGD","","","power-button","host0-ready","","presence-ps0","presence-ps1", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","reset-button","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","power-chassis-good","","",""; +}; From 1480bcf074d34e754990204240f8473cdbef0072 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 26 Jan 2023 16:08:42 -0600 Subject: [PATCH 14/14] ARM: dts: aspeed: p10bmc: Enable UART2 The APSS can be accessed over the second uart on these systems. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20230126220842.885965-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 4 ++++ arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 4 ++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index d1971ddf06a5..f53a97d9e1b3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -857,6 +857,10 @@ &i2c15 { status = "okay"; }; +&uart2 { + status = "okay"; +}; + &vuart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 1448ea895be4..456ca2830a31 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -3649,6 +3649,10 @@ &ibt { status = "okay"; }; +&uart2 { + status = "okay"; +}; + &vuart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 20ef958698ec..e1b5d44308fe 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -2352,6 +2352,10 @@ led@7 { }; }; +&uart2 { + status = "okay"; +}; + &vuart1 { status = "okay"; };