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drm/mgag200: Split DPMS function into helpers

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Of the DPMS code, only ON and OFF states are used. Simplify mode setting
by moving both into separate functions and removing the rest.

The original code busy waited in the middle of updating the screen state
in SEQ1. To simplify the procedure, the new code busy waits first and then
updates SEQ1 in one chunk.

The DPMS code also set the LUT before enabling the screen. The patch moves
this code into the simple-display pipe's enable function.

v2:
	* comment on SEQ1 updates in commit message

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200707082411.6583-5-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann 2020-07-07 10:24:08 +02:00
parent 379ba8043d
commit 153fef4115
2 changed files with 46 additions and 32 deletions
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75
drivers/gpu/drm/mgag200/mgag200_mode.c
View file

@ -1282,41 +1282,50 @@ static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
WREG_ECRT(0x06, 0x00);
}
static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
static void mgag200_enable_display(struct mga_device *mdev)
{
struct drm_device *dev = crtc->dev;
struct mga_device *mdev = to_mga_device(dev);
u8 seq1 = 0, crtcext1 = 0;
u8 seq1, crtcext1;
switch (mode) {
case DRM_MODE_DPMS_ON:
seq1 = 0;
crtcext1 = 0;
mga_crtc_load_lut(crtc);
break;
case DRM_MODE_DPMS_STANDBY:
seq1 = 0x20;
crtcext1 = 0x10;
break;
case DRM_MODE_DPMS_SUSPEND:
seq1 = 0x20;
crtcext1 = 0x20;
break;
case DRM_MODE_DPMS_OFF:
seq1 = 0x20;
crtcext1 = 0x30;
break;
}
WREG8(MGAREG_SEQ_INDEX, 0x01);
seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
/*
* TODO: replace busy waiting with vblank IRQ; put
* msleep(50) before changing SCROFF
*/
mga_wait_vsync(mdev);
mga_wait_busy(mdev);
WREG8(MGAREG_SEQ_DATA, seq1);
RREG_SEQ(0x01, seq1);
seq1 &= ~MGAREG_SEQ1_SCROFF;
WREG_SEQ(0x01, seq1);
msleep(20);
WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
RREG_ECRT(0x01, crtcext1);
crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
WREG_ECRT(0x01, crtcext1);
}
static void mgag200_disable_display(struct mga_device *mdev)
{
u8 seq1, crtcext1;
/*
* TODO: replace busy waiting with vblank IRQ; put
* msleep(50) before changing SCROFF
*/
mga_wait_vsync(mdev);
mga_wait_busy(mdev);
RREG_SEQ(0x01, seq1);
seq1 |= MGAREG_SEQ1_SCROFF;
WREG_SEQ(0x01, seq1);
msleep(20);
RREG_ECRT(0x01, crtcext1);
crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
MGAREG_CRTCEXT1_HSYNCOFF;
WREG_ECRT(0x01, crtcext1);
}
/*
@ -1349,7 +1358,8 @@ static void mga_crtc_commit(struct drm_crtc *crtc)
mga_g200wb_commit(crtc);
WREG_SEQ(0, 0x3);
mga_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
mga_crtc_load_lut(crtc);
mgag200_enable_display(mdev);
}
/*
@ -1595,8 +1605,9 @@ static void
mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
{
struct drm_crtc *crtc = &pipe->crtc;
struct mga_device *mdev = to_mga_device(crtc->dev);
mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
mgag200_disable_display(mdev);
}
static int

3
drivers/gpu/drm/mgag200/mgag200_reg.h
View file

@ -250,6 +250,9 @@
#define MGAREG_CRTCEXT0_OFFSET_MASK GENMASK(5, 4)
#define MGAREG_CRTCEXT1_VSYNCOFF BIT(5)
#define MGAREG_CRTCEXT1_HSYNCOFF BIT(4)
/* Cursor X and Y position */
#define MGA_CURPOSXL 0x3c0c
#define MGA_CURPOSXH 0x3c0d