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remoteproc updates for v5.10

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This introduces support for the Mediatek MT9182 SCP and controlling the
 Cortex R5F processors found in TI K3 platforms. It clones the
 longstanding debugfs interface for controlling crash handling to sysfs.
 Lastly it solves a bug where after a warm reset of Qualcomm platforms
 the modem would crash upon first boot.
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Merge tag 'rproc-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc

Pull remoteproc updates from Bjorn Andersson:
 "This introduces support for the Mediatek MT9182 SCP and controlling
  the Cortex R5F processors found in TI K3 platforms. It clones the
  longstanding debugfs interface for controlling crash handling to
  sysfs. Lastly it solves a bug where after a warm reset of Qualcomm
  platforms the modem would crash upon first boot"

* tag 'rproc-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc:
  remoteproc/mediatek: Remove non-standard dsb()
  remoteproc: Add recovery configuration to the sysfs interface
  remoteproc: Add coredump as part of sysfs interface
  remoteproc: Change default dump configuration to "disabled"
  remoteproc: k3-r5: Add loading support for on-chip SRAM regions
  remoteproc: k3-r5: Initialize TCM memories for ECC
  remoteproc: k3-r5: Add a remoteproc driver for R5F subsystem
  dt-bindings: remoteproc: Add bindings for R5F subsystem on TI K3 SoCs
  remoteproc/mediatek: Add support for mt8192 SCP
  remoteproc: Fixup coredump debugfs disable request
  remoteproc: qcom_q6v5: Assign mpss region to Q6 before MBA boot
  remoteproc/mediatek: fix null pointer dereference on null scp pointer
  remoteproc: stm32: Fix pointer assignement
  remoteproc: scp: add COMPILE_TEST dependency
This commit is contained in:
Linus Torvalds 2020-10-22 12:56:33 -07:00
commit 1553d96854
14 changed files with 2086 additions and 62 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

44
Documentation/ABI/testing/sysfs-class-remoteproc
View file

@ -58,3 +58,47 @@ Description: Remote processor name
Reports the name of the remote processor. This can be used by
userspace in exactly identifying a remote processor and ease
up the usage in modifying the 'firmware' or 'state' files.
What: /sys/class/remoteproc/.../coredump
Date: July 2020
Contact: Bjorn Andersson <bjorn.andersson@linaro.org>, Ohad Ben-Cohen <ohad@wizery.com>
Description: Remote processor coredump configuration
Reports the coredump configuration of the remote processor,
which will be one of:
"disabled"
"enabled"
"inline"
"disabled" means no dump will be collected.
"enabled" means when the remote processor's coredump is
collected it will be copied to a separate buffer and that
buffer is exposed to userspace.
"inline" means when the remote processor's coredump is
collected userspace will directly read from the remote
processor's device memory. Extra buffer will not be used to
copy the dump. Also recovery process will not proceed until
all data is read by usersapce.
What: /sys/class/remoteproc/.../recovery
Date: July 2020
Contact: Bjorn Andersson <bjorn.andersson@linaro.org>, Ohad Ben-Cohen <ohad@wizery.com>
Description: Remote processor recovery mechanism
Reports the recovery mechanism of the remote processor,
which will be one of:
"enabled"
"disabled"
"enabled" means, the remote processor will be automatically
recovered whenever it crashes. Moreover, if the remote
processor crashes while recovery is disabled, it will
be automatically recovered too as soon as recovery is enabled.
"disabled" means, a remote processor will remain in a crashed
state if it crashes. This is useful for debugging purposes;
without it, debugging a crash is substantially harder.

281
Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml Normal file
View file

@ -0,0 +1,281 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI K3 R5F processor subsystems
maintainers:
- Suman Anna <s-anna@ti.com>
description: |
The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
processor subsystems/clusters (R5FSS). The dual core cluster can be used
either in a LockStep mode providing safety/fault tolerance features or in a
Split mode providing two individual compute cores for doubling the compute
capacity. These are used together with other processors present on the SoC
to achieve various system level goals.
Each Dual-Core R5F sub-system is represented as a single DTS node
representing the cluster, with a pair of child DT nodes representing
the individual R5F cores. Each node has a number of required or optional
properties that enable the OS running on the host processor to perform
the device management of the remote processor and to communicate with the
remote processor.
properties:
$nodename:
pattern: "^r5fss(@.*)?"
compatible:
enum:
- ti,am654-r5fss
- ti,j721e-r5fss
power-domains:
description: |
Should contain a phandle to a PM domain provider node and an args
specifier containing the R5FSS device id value.
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
description: |
Standard ranges definition providing address translations for
local R5F TCM address spaces to bus addresses.
# Optional properties:
# --------------------
ti,cluster-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Configuration Mode for the Dual R5F cores within the R5F cluster.
Should be either a value of 1 (LockStep mode) or 0 (Split mode),
default is LockStep mode if omitted.
# R5F Processor Child Nodes:
# ==========================
patternProperties:
"^r5f@[a-f0-9]+$":
type: object
description: |
The R5F Sub-System device node should define two R5F child nodes, each
node representing a TI instantiation of the Arm Cortex R5F core. There
are some specific integration differences for the IP like the usage of
a Region Address Translator (RAT) for translating the larger SoC bus
addresses into a 32-bit address space for the processor.
Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
internal memories split between two banks - TCMA and TCMB (further
interleaved into two banks TCMB0 and TCMB1). These memories (also called
ATCM and BTCM) provide read/write performance on par with the core's L1
caches. Each of the TCMs can be enabled or disabled independently and
either of them can be configured to appear at that R5F's address 0x0.
The cores do not use an MMU, but has a Region Address Translater
(RAT) module that is accessible only from the R5Fs for providing
translations between 32-bit CPU addresses into larger system bus
addresses. Cache and memory access settings are provided through a
Memory Protection Unit (MPU), programmable only from the R5Fs.
allOf:
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
compatible:
enum:
- ti,am654-r5f
- ti,j721e-r5f
reg:
items:
- description: Address and Size of the ATCM internal memory region
- description: Address and Size of the BTCM internal memory region
reg-names:
items:
- const: atcm
- const: btcm
resets:
description: |
Should contain the phandle to the reset controller node managing the
local resets for this device, and a reset specifier.
maxItems: 1
firmware-name:
description: |
Should contain the name of the default firmware image
file located on the firmware search path
# The following properties are mandatory for R5F Core0 in both LockStep and Split
# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
# R5F Core1 in LockStep mode:
mboxes:
description: |
OMAP Mailbox specifier denoting the sub-mailbox, to be used for
communication with the remote processor. This property should match
with the sub-mailbox node used in the firmware image.
maxItems: 1
memory-region:
description: |
phandle to the reserved memory nodes to be associated with the
remoteproc device. There should be at least two reserved memory nodes
defined. The reserved memory nodes should be carveout nodes, and
should be defined with a "no-map" property as per the bindings in
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
minItems: 2
maxItems: 8
items:
- description: region used for dynamic DMA allocations like vrings and
vring buffers
- description: region reserved for firmware image sections
additionalItems: true
# Optional properties:
# --------------------
# The following properties are optional properties for each of the R5F cores:
ti,atcm-enable:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
R5F core configuration mode dictating if ATCM should be enabled. The
R5F address of ATCM is dictated by ti,loczrama property. Should be
either a value of 1 (enabled) or 0 (disabled), default is disabled
if omitted. Recommended to enable it for maximizing TCMs.
ti,btcm-enable:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
R5F core configuration mode dictating if BTCM should be enabled. The
R5F address of BTCM is dictated by ti,loczrama property. Should be
either a value of 1 (enabled) or 0 (disabled), default is enabled if
omitted.
ti,loczrama:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
R5F core configuration mode dictating which TCM should appear at
address 0 (from core's view). Should be either a value of 1 (ATCM
at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
description: |
phandles to one or more reserved on-chip SRAM regions. The regions
should be defined as child nodes of the respective SRAM node, and
should be defined as per the generic bindings in,
Documentation/devicetree/bindings/sram/sram.yaml
required:
- compatible
- reg
- reg-names
- ti,sci
- ti,sci-dev-id
- ti,sci-proc-ids
- resets
- firmware-name
unevaluatedProperties: false
required:
- compatible
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654-evm", "ti,am654";
#address-cells = <2>;
#size-cells = <2>;
bus@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
bus@28380000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
/* AM65x MCU R5FSS node */
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,am654-r5fss";
power-domains = <&k3_pds 129>;
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
mcu_r5f0: r5f@41000000 {
compatible = "ti,am654-r5f";
reg = <0x41000000 0x00008000>,
<0x41010000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <159>;
ti,sci-proc-ids = <0x01 0xFF>;
resets = <&k3_reset 159 1>;
firmware-name = "am65x-mcu-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
sram = <&mcu_r5fss0_core0_sram>;
};
mcu_r5f1: r5f@41400000 {
compatible = "ti,am654-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x02 0xFF>;
resets = <&k3_reset 245 1>;
firmware-name = "am65x-mcu-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
};
};
};
};
};

13
drivers/remoteproc/Kconfig
View file

@ -275,6 +275,19 @@ config TI_K3_DSP_REMOTEPROC
It's safe to say N here if you're not interested in utilizing
the DSP slave processors.
config TI_K3_R5_REMOTEPROC
tristate "TI K3 R5 remoteproc support"
depends on ARCH_K3
select MAILBOX
select OMAP2PLUS_MBOX
help
Say m here to support TI's R5F remote processor subsystems
on various TI K3 family of SoCs through the remote processor
framework.
It's safe to say N here if you're not interested in utilizing
a slave processor.
endif # REMOTEPROC
endmenu

1
drivers/remoteproc/Makefile
View file

@ -33,3 +33,4 @@ obj-$(CONFIG_ST_REMOTEPROC) += st_remoteproc.o
obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
obj-$(CONFIG_STM32_RPROC) += stm32_rproc.o
obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o
obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o

32
drivers/remoteproc/mtk_common.h
View file

@ -32,6 +32,23 @@
#define MT8183_SCP_CACHESIZE_8KB BIT(8)
#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
#define MT8192_L2TCM_SRAM_PD_0 0x210C0
#define MT8192_L2TCM_SRAM_PD_1 0x210C4
#define MT8192_L2TCM_SRAM_PD_2 0x210C8
#define MT8192_L1TCM_SRAM_PDN 0x2102C
#define MT8192_CPU0_SRAM_PD 0x21080
#define MT8192_SCP2APMCU_IPC_SET 0x24080
#define MT8192_SCP2APMCU_IPC_CLR 0x24084
#define MT8192_SCP_IPC_INT_BIT BIT(0)
#define MT8192_SCP2SPM_IPC_CLR 0x24094
#define MT8192_GIPC_IN_SET 0x24098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
#define MT8192_CORE0_SW_RSTN_CLR 0x30000
#define MT8192_CORE0_SW_RSTN_SET 0x30004
#define MT8192_CORE0_WDT_CFG 0x30034
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
@ -50,6 +67,19 @@ struct scp_ipi_desc {
void *priv;
};
struct mtk_scp;
struct mtk_scp_of_data {
int (*scp_before_load)(struct mtk_scp *scp);
void (*scp_irq_handler)(struct mtk_scp *scp);
void (*scp_reset_assert)(struct mtk_scp *scp);
void (*scp_reset_deassert)(struct mtk_scp *scp);
void (*scp_stop)(struct mtk_scp *scp);
u32 host_to_scp_reg;
u32 host_to_scp_int_bit;
};
struct mtk_scp {
struct device *dev;
struct rproc *rproc;
@ -58,6 +88,8 @@ struct mtk_scp {
void __iomem *sram_base;
size_t sram_size;
const struct mtk_scp_of_data *data;
struct mtk_share_obj __iomem *recv_buf;
struct mtk_share_obj __iomem *send_buf;
struct scp_run run;

199
drivers/remoteproc/mtk_scp.c
View file

@ -124,9 +124,6 @@ static int scp_ipi_init(struct mtk_scp *scp)
size_t send_offset = SCP_FW_END - sizeof(struct mtk_share_obj);
size_t recv_offset = send_offset - sizeof(struct mtk_share_obj);
/* Disable SCP to host interrupt */
writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
/* shared buffer initialization */
scp->recv_buf =
(struct mtk_share_obj __iomem *)(scp->sram_base + recv_offset);
@ -138,7 +135,7 @@ static int scp_ipi_init(struct mtk_scp *scp)
return 0;
}
static void scp_reset_assert(const struct mtk_scp *scp)
static void mt8183_scp_reset_assert(struct mtk_scp *scp)
{
u32 val;
@ -147,7 +144,7 @@ static void scp_reset_assert(const struct mtk_scp *scp)
writel(val, scp->reg_base + MT8183_SW_RSTN);
}
static void scp_reset_deassert(const struct mtk_scp *scp)
static void mt8183_scp_reset_deassert(struct mtk_scp *scp)
{
u32 val;
@ -156,17 +153,19 @@ static void scp_reset_deassert(const struct mtk_scp *scp)
writel(val, scp->reg_base + MT8183_SW_RSTN);
}
static irqreturn_t scp_irq_handler(int irq, void *priv)
static void mt8192_scp_reset_assert(struct mtk_scp *scp)
{
struct mtk_scp *scp = priv;
u32 scp_to_host;
int ret;
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
}
ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(scp->dev, "failed to enable clocks\n");
return IRQ_NONE;
}
static void mt8192_scp_reset_deassert(struct mtk_scp *scp)
{
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR);
}
static void mt8183_scp_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;
scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST);
if (scp_to_host & MT8183_SCP_IPC_INT_BIT)
@ -177,6 +176,40 @@ static irqreturn_t scp_irq_handler(int irq, void *priv)
/* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */
writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT,
scp->reg_base + MT8183_SCP_TO_HOST);
}
static void mt8192_scp_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;
scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);
if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
scp_ipi_handler(scp);
else
scp_wdt_handler(scp, scp_to_host);
/*
* SCP won't send another interrupt until we clear
* MT8192_SCP2APMCU_IPC.
*/
writel(MT8192_SCP_IPC_INT_BIT,
scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
}
static irqreturn_t scp_irq_handler(int irq, void *priv)
{
struct mtk_scp *scp = priv;
int ret;
ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(scp->dev, "failed to enable clocks\n");
return IRQ_NONE;
}
scp->data->scp_irq_handler(scp);
clk_disable_unprepare(scp->clk);
return IRQ_HANDLED;
@ -238,20 +271,10 @@ static int scp_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
return ret;
}
static int scp_load(struct rproc *rproc, const struct firmware *fw)
static int mt8183_scp_before_load(struct mtk_scp *scp)
{
const struct mtk_scp *scp = rproc->priv;
struct device *dev = scp->dev;
int ret;
ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(dev, "failed to enable clocks\n");
return ret;
}
/* Hold SCP in reset while loading FW. */
scp_reset_assert(scp);
/* Clear SCP to host interrupt */
writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
/* Reset clocks before loading FW */
writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
@ -272,6 +295,63 @@ static int scp_load(struct rproc *rproc, const struct firmware *fw)
scp->reg_base + MT8183_SCP_CACHE_CON);
writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
return 0;
}
static void mt8192_power_on_sram(void *addr)
{
int i;
for (i = 31; i >= 0; i--)
writel(GENMASK(i, 0), addr);
writel(0, addr);
}
static void mt8192_power_off_sram(void *addr)
{
int i;
writel(0, addr);
for (i = 0; i < 32; i++)
writel(GENMASK(i, 0), addr);
}
static int mt8192_scp_before_load(struct mtk_scp *scp)
{
/* clear SPM interrupt, SCP2SPM_IPC_CLR */
writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
/* enable SRAM clock */
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
return 0;
}
static int scp_load(struct rproc *rproc, const struct firmware *fw)
{
struct mtk_scp *scp = rproc->priv;
struct device *dev = scp->dev;
int ret;
ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(dev, "failed to enable clocks\n");
return ret;
}
/* Hold SCP in reset while loading FW. */
scp->data->scp_reset_assert(scp);
ret = scp->data->scp_before_load(scp);
if (ret < 0)
return ret;
ret = scp_elf_load_segments(rproc, fw);
clk_disable_unprepare(scp->clk);
@ -293,7 +373,7 @@ static int scp_start(struct rproc *rproc)
run->signaled = false;
scp_reset_deassert(scp);
scp->data->scp_reset_deassert(scp);
ret = wait_event_interruptible_timeout(
run->wq,
@ -309,13 +389,14 @@ static int scp_start(struct rproc *rproc)
dev_err(dev, "wait SCP interrupted by a signal!\n");
goto stop;
}
clk_disable_unprepare(scp->clk);
dev_info(dev, "SCP is ready. FW version %s\n", run->fw_ver);
return 0;
stop:
scp_reset_assert(scp);
scp->data->scp_reset_assert(scp);
clk_disable_unprepare(scp->clk);
return ret;
}
@ -329,7 +410,7 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
offset = da;
if (offset >= 0 && (offset + len) < scp->sram_size)
return (void __force *)scp->sram_base + offset;
} else {
} else if (scp->dram_size) {
offset = da - scp->dma_addr;
if (offset >= 0 && (offset + len) < scp->dram_size)
return (void __force *)scp->cpu_addr + offset;
@ -338,6 +419,25 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da, size_t len)
return NULL;
}
static void mt8183_scp_stop(struct mtk_scp *scp)
{
/* Disable SCP watchdog */
writel(0, scp->reg_base + MT8183_WDT_CFG);
}
static void mt8192_scp_stop(struct mtk_scp *scp)
{
/* Disable SRAM clock */
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
mt8192_power_off_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
mt8192_power_off_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
/* Disable SCP watchdog */
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
}
static int scp_stop(struct rproc *rproc)
{
struct mtk_scp *scp = (struct mtk_scp *)rproc->priv;
@ -349,9 +449,8 @@ static int scp_stop(struct rproc *rproc)
return ret;
}
scp_reset_assert(scp);
/* Disable SCP watchdog */
writel(0, scp->reg_base + MT8183_WDT_CFG);
scp->data->scp_reset_assert(scp);
scp->data->scp_stop(scp);
clk_disable_unprepare(scp->clk);
return 0;
@ -443,6 +542,13 @@ static int scp_map_memory_region(struct mtk_scp *scp)
int ret;
ret = of_reserved_mem_device_init(scp->dev);
/* reserved memory is optional. */
if (ret == -ENODEV) {
dev_info(scp->dev, "skipping reserved memory initialization.");
return 0;
}
if (ret) {
dev_err(scp->dev, "failed to assign memory-region: %d\n", ret);
return -ENOMEM;
@ -460,6 +566,9 @@ static int scp_map_memory_region(struct mtk_scp *scp)
static void scp_unmap_memory_region(struct mtk_scp *scp)
{
if (scp->dram_size == 0)
return;
dma_free_coherent(scp->dev, scp->dram_size, scp->cpu_addr,
scp->dma_addr);
of_reserved_mem_device_release(scp->dev);
@ -536,6 +645,7 @@ static int scp_probe(struct platform_device *pdev)
scp = (struct mtk_scp *)rproc->priv;
scp->rproc = rproc;
scp->dev = dev;
scp->data = of_device_get_match_data(dev);
platform_set_drvdata(pdev, scp);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
@ -642,8 +752,29 @@ static int scp_remove(struct platform_device *pdev)
return 0;
}
static const struct mtk_scp_of_data mt8183_of_data = {
.scp_before_load = mt8183_scp_before_load,
.scp_irq_handler = mt8183_scp_irq_handler,
.scp_reset_assert = mt8183_scp_reset_assert,
.scp_reset_deassert = mt8183_scp_reset_deassert,
.scp_stop = mt8183_scp_stop,
.host_to_scp_reg = MT8183_HOST_TO_SCP,
.host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT,
};
static const struct mtk_scp_of_data mt8192_of_data = {
.scp_before_load = mt8192_scp_before_load,
.scp_irq_handler = mt8192_scp_irq_handler,
.scp_reset_assert = mt8192_scp_reset_assert,
.scp_reset_deassert = mt8192_scp_reset_deassert,
.scp_stop = mt8192_scp_stop,
.host_to_scp_reg = MT8192_GIPC_IN_SET,
.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
};
static const struct of_device_id mtk_scp_of_match[] = {
{ .compatible = "mediatek,mt8183-scp"},
{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data },
{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
{},
};
MODULE_DEVICE_TABLE(of, mtk_scp_of_match);

9
drivers/remoteproc/mtk_scp_ipi.c
View file

@ -30,10 +30,8 @@ int scp_ipi_register(struct mtk_scp *scp,
scp_ipi_handler_t handler,
void *priv)
{
if (!scp) {
dev_err(scp->dev, "scp device is not ready\n");
if (!scp)
return -EPROBE_DEFER;
}
if (WARN_ON(id >= SCP_IPI_MAX) || WARN_ON(handler == NULL))
return -EINVAL;
@ -182,7 +180,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
ret = -ETIMEDOUT;
goto clock_disable;
}
} while (readl(scp->reg_base + MT8183_HOST_TO_SCP));
} while (readl(scp->reg_base + scp->data->host_to_scp_reg));
scp_memcpy_aligned(send_obj->share_buf, buf, len);
@ -191,7 +189,8 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
scp->ipi_id_ack[id] = false;
/* send the command to SCP */
writel(MT8183_HOST_IPC_INT_BIT, scp->reg_base + MT8183_HOST_TO_SCP);
writel(scp->data->host_to_scp_int_bit,
scp->reg_base + scp->data->host_to_scp_reg);
if (wait) {
/* wait for SCP's ACK */

16
drivers/remoteproc/qcom_q6v5_mss.c
View file

@ -931,6 +931,17 @@ static int q6v5_mba_load(struct q6v5 *qproc)
goto assert_reset;
}
/*
* Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
* the Q6 access to this region.
*/
ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
qproc->mpss_phys, qproc->mpss_size);
if (ret) {
dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
goto disable_active_clks;
}
/* Assign MBA image access in DDR to q6 */
ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
qproc->mba_phys, qproc->mba_size);
@ -1135,10 +1146,9 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
}
/**
/*
* In case of a modem subsystem restart on secure devices, the modem
* memory can be reclaimed only after MBA is loaded. For modem cold
* boot this will be a nop
* memory can be reclaimed only after MBA is loaded.
*/
q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
qproc->mpss_phys, qproc->mpss_size);

6
drivers/remoteproc/remoteproc_coredump.c
View file

@ -257,7 +257,7 @@ void rproc_coredump(struct rproc *rproc)
* directly read from device memory.
*/
data_size += elf_size_of_phdr(class);
if (dump_conf == RPROC_COREDUMP_DEFAULT)
if (dump_conf == RPROC_COREDUMP_ENABLED)
data_size += segment->size;
phnum++;
@ -297,14 +297,14 @@ void rproc_coredump(struct rproc *rproc)
elf_phdr_set_p_flags(class, phdr, PF_R | PF_W | PF_X);
elf_phdr_set_p_align(class, phdr, 0);
if (dump_conf == RPROC_COREDUMP_DEFAULT)
if (dump_conf == RPROC_COREDUMP_ENABLED)
rproc_copy_segment(rproc, data + offset, segment, 0,
segment->size);
offset += elf_phdr_get_p_filesz(class, phdr);
phdr += elf_size_of_phdr(class);
}
if (dump_conf == RPROC_COREDUMP_DEFAULT) {
if (dump_conf == RPROC_COREDUMP_ENABLED) {
dev_coredumpv(&rproc->dev, data, data_size, GFP_KERNEL);
return;
}

23
drivers/remoteproc/remoteproc_debugfs.c
View file

@ -33,9 +33,9 @@ static struct dentry *rproc_dbg;
* enum rproc_coredump_mechanism
*/
static const char * const rproc_coredump_str[] = {
[RPROC_COREDUMP_DEFAULT] = "default",
[RPROC_COREDUMP_INLINE] = "inline",
[RPROC_COREDUMP_DISABLED] = "disabled",
[RPROC_COREDUMP_ENABLED] = "enabled",
[RPROC_COREDUMP_INLINE] = "inline",
};
/* Expose the current coredump configuration via debugfs */
@ -54,20 +54,19 @@ static ssize_t rproc_coredump_read(struct file *filp, char __user *userbuf,
/*
* By writing to the 'coredump' debugfs entry, we control the behavior of the
* coredump mechanism dynamically. The default value of this entry is "default".
* coredump mechanism dynamically. The default value of this entry is "disabled".
*
* The 'coredump' debugfs entry supports these commands:
*
* default: This is the default coredump mechanism. When the remoteproc
* crashes the entire coredump will be copied to a separate buffer
* and exposed to userspace.
* disabled: By default coredump collection is disabled. Recovery will
* proceed without collecting any dump.
*
* enabled: When the remoteproc crashes the entire coredump will be copied
* to a separate buffer and exposed to userspace.
*
* inline: The coredump will not be copied to a separate buffer and the
* recovery process will have to wait until data is read by
* userspace. But this avoid usage of extra memory.
*
* disabled: This will disable coredump. Recovery will proceed without
* collecting any dump.
*/
static ssize_t rproc_coredump_write(struct file *filp,
const char __user *user_buf, size_t count,
@ -94,12 +93,12 @@ static ssize_t rproc_coredump_write(struct file *filp,
goto out;
}
if (!strncmp(buf, "disable", count)) {
if (!strncmp(buf, "disabled", count)) {
rproc->dump_conf = RPROC_COREDUMP_DISABLED;
} else if (!strncmp(buf, "enabled", count)) {
rproc->dump_conf = RPROC_COREDUMP_ENABLED;
} else if (!strncmp(buf, "inline", count)) {
rproc->dump_conf = RPROC_COREDUMP_INLINE;
} else if (!strncmp(buf, "default", count)) {
rproc->dump_conf = RPROC_COREDUMP_DEFAULT;
} else {
dev_err(&rproc->dev, "Invalid coredump configuration\n");
err = -EINVAL;

119
drivers/remoteproc/remoteproc_sysfs.c
View file

@ -10,6 +10,123 @@
#define to_rproc(d) container_of(d, struct rproc, dev)
static ssize_t recovery_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rproc *rproc = to_rproc(dev);
return sprintf(buf, "%s", rproc->recovery_disabled ? "disabled\n" : "enabled\n");
}
/*
* By writing to the 'recovery' sysfs entry, we control the behavior of the
* recovery mechanism dynamically. The default value of this entry is "enabled".
*
* The 'recovery' sysfs entry supports these commands:
*
* enabled: When enabled, the remote processor will be automatically
* recovered whenever it crashes. Moreover, if the remote
* processor crashes while recovery is disabled, it will
* be automatically recovered too as soon as recovery is enabled.
*
* disabled: When disabled, a remote processor will remain in a crashed
* state if it crashes. This is useful for debugging purposes;
* without it, debugging a crash is substantially harder.
*
* recover: This function will trigger an immediate recovery if the
* remote processor is in a crashed state, without changing
* or checking the recovery state (enabled/disabled).
* This is useful during debugging sessions, when one expects
* additional crashes to happen after enabling recovery. In this
* case, enabling recovery will make it hard to debug subsequent
* crashes, so it's recommended to keep recovery disabled, and
* instead use the "recover" command as needed.
*/
static ssize_t recovery_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rproc *rproc = to_rproc(dev);
if (sysfs_streq(buf, "enabled")) {
/* change the flag and begin the recovery process if needed */
rproc->recovery_disabled = false;
rproc_trigger_recovery(rproc);
} else if (sysfs_streq(buf, "disabled")) {
rproc->recovery_disabled = true;
} else if (sysfs_streq(buf, "recover")) {
/* begin the recovery process without changing the flag */
rproc_trigger_recovery(rproc);
} else {
return -EINVAL;
}
return count;
}
static DEVICE_ATTR_RW(recovery);
/*
* A coredump-configuration-to-string lookup table, for exposing a
* human readable configuration via sysfs. Always keep in sync with
* enum rproc_coredump_mechanism
*/
static const char * const rproc_coredump_str[] = {
[RPROC_COREDUMP_DISABLED] = "disabled",
[RPROC_COREDUMP_ENABLED] = "enabled",
[RPROC_COREDUMP_INLINE] = "inline",
};
/* Expose the current coredump configuration via debugfs */
static ssize_t coredump_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rproc *rproc = to_rproc(dev);
return sprintf(buf, "%s\n", rproc_coredump_str[rproc->dump_conf]);
}
/*
* By writing to the 'coredump' sysfs entry, we control the behavior of the
* coredump mechanism dynamically. The default value of this entry is "default".
*
* The 'coredump' sysfs entry supports these commands:
*
* disabled: This is the default coredump mechanism. Recovery will proceed
* without collecting any dump.
*
* default: When the remoteproc crashes the entire coredump will be
* copied to a separate buffer and exposed to userspace.
*
* inline: The coredump will not be copied to a separate buffer and the
* recovery process will have to wait until data is read by
* userspace. But this avoid usage of extra memory.
*/
static ssize_t coredump_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rproc *rproc = to_rproc(dev);
if (rproc->state == RPROC_CRASHED) {
dev_err(&rproc->dev, "can't change coredump configuration\n");
return -EBUSY;
}
if (sysfs_streq(buf, "disabled")) {
rproc->dump_conf = RPROC_COREDUMP_DISABLED;
} else if (sysfs_streq(buf, "enabled")) {
rproc->dump_conf = RPROC_COREDUMP_ENABLED;
} else if (sysfs_streq(buf, "inline")) {
rproc->dump_conf = RPROC_COREDUMP_INLINE;
} else {
dev_err(&rproc->dev, "Invalid coredump configuration\n");
return -EINVAL;
}
return count;
}
static DEVICE_ATTR_RW(coredump);
/* Expose the loaded / running firmware name via sysfs */
static ssize_t firmware_show(struct device *dev, struct device_attribute *attr,
char *buf)
@ -138,6 +255,8 @@ static ssize_t name_show(struct device *dev, struct device_attribute *attr,
static DEVICE_ATTR_RO(name);
static struct attribute *rproc_attrs[] = {
&dev_attr_coredump.attr,
&dev_attr_recovery.attr,
&dev_attr_firmware.attr,
&dev_attr_state.attr,
&dev_attr_name.attr,

2
drivers/remoteproc/stm32_rproc.c
View file

@ -685,7 +685,7 @@ static int stm32_rproc_get_m4_status(struct stm32_rproc *ddata,
* We couldn't get the coprocessor's state, assume
* it is not running.
*/
state = M4_STATE_OFF;
*state = M4_STATE_OFF;
return 0;
}

1395
drivers/remoteproc/ti_k3_r5_remoteproc.c Normal file
View file

File diff suppressed because it is too large Load diff

8
include/linux/remoteproc.h
View file

@ -442,16 +442,16 @@ enum rproc_crash_type {
/**
* enum rproc_dump_mechanism - Coredump options for core
* @RPROC_COREDUMP_DEFAULT: Copy dump to separate buffer and carry on with
* @RPROC_COREDUMP_DISABLED: Don't perform any dump
* @RPROC_COREDUMP_ENABLED: Copy dump to separate buffer and carry on with
recovery
* @RPROC_COREDUMP_INLINE: Read segments directly from device memory. Stall
recovery until all segments are read
* @RPROC_COREDUMP_DISABLED: Don't perform any dump
*/
enum rproc_dump_mechanism {
RPROC_COREDUMP_DEFAULT,
RPROC_COREDUMP_INLINE,
RPROC_COREDUMP_DISABLED,
RPROC_COREDUMP_ENABLED,
RPROC_COREDUMP_INLINE,
};
/**