mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-04 09:59:32 +00:00
shpchp: remove DBG_XXX_ROUTINE
This patch removes DBG_ENTER_ROUTINE, DBG_LEAVE_ROUTINE and related code. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
parent
3d9c18872f
commit
1555b33da0
1 changed files with 19 additions and 136 deletions
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@ -35,38 +35,6 @@
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#include "shpchp.h"
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#ifdef DEBUG
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#define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
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#define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
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#define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
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#define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
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#define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
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#define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
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/* Redefine this flagword to set debug level */
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#define DEBUG_LEVEL DBG_K_STANDARD
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#define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
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#define DBG_PRINT( dbg_flags, args... ) \
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do { \
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if ( DEBUG_LEVEL & ( dbg_flags ) ) \
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{ \
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int len; \
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len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
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__FILE__, __LINE__, __FUNCTION__ ); \
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sprintf( __dbg_str_buf + len, args ); \
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printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
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} \
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} while (0)
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#define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
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#define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
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#else
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#define DEFINE_DBG_BUFFER
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#define DBG_ENTER_ROUTINE
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#define DBG_LEAVE_ROUTINE
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#endif /* DEBUG */
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/* Slot Available Register I field definition */
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#define SLOT_33MHZ 0x0000001f
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#define SLOT_66MHZ_PCIX 0x00001f00
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@ -211,7 +179,6 @@
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#define SLOT_EVENT_LATCH 0x2
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#define SLOT_SERR_INT_MASK 0x3
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DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
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static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
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static irqreturn_t shpc_isr(int irq, void *dev_id);
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@ -268,8 +235,6 @@ static void int_poll_timeout(unsigned long data)
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{
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struct controller *ctrl = (struct controller *)data;
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DBG_ENTER_ROUTINE
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/* Poll for interrupt events. regs == NULL => polling */
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shpc_isr(0, ctrl);
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@ -278,8 +243,6 @@ static void int_poll_timeout(unsigned long data)
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shpchp_poll_time = 2; /* default polling interval is 2 sec */
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start_int_poll_timer(ctrl, shpchp_poll_time);
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DBG_LEAVE_ROUTINE
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}
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/*
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@ -353,8 +316,6 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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int retval = 0;
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u16 temp_word;
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DBG_ENTER_ROUTINE
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mutex_lock(&slot->ctrl->cmd_lock);
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if (!shpc_poll_ctrl_busy(ctrl)) {
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@ -389,19 +350,13 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
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}
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out:
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mutex_unlock(&slot->ctrl->cmd_lock);
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DBG_LEAVE_ROUTINE
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return retval;
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}
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static int hpc_check_cmd_status(struct controller *ctrl)
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{
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u16 cmd_status;
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int retval = 0;
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DBG_ENTER_ROUTINE
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cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
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u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
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switch (cmd_status >> 1) {
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case 0:
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@ -423,7 +378,6 @@ static int hpc_check_cmd_status(struct controller *ctrl)
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retval = cmd_status;
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}
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DBG_LEAVE_ROUTINE
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return retval;
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}
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@ -431,13 +385,8 @@ static int hpc_check_cmd_status(struct controller *ctrl)
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static int hpc_get_attention_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u8 state;
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DBG_ENTER_ROUTINE
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slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
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switch (state) {
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case ATN_LED_STATE_ON:
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@ -454,20 +403,14 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status)
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break;
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}
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DBG_LEAVE_ROUTINE
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return 0;
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}
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static int hpc_get_power_status(struct slot * slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u8 state;
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DBG_ENTER_ROUTINE
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slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
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switch (state) {
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case SLOT_STATE_PWRONLY:
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@ -484,7 +427,6 @@ static int hpc_get_power_status(struct slot * slot, u8 *status)
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break;
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}
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DBG_LEAVE_ROUTINE
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return 0;
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}
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@ -492,30 +434,21 @@ static int hpc_get_power_status(struct slot * slot, u8 *status)
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static int hpc_get_latch_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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DBG_ENTER_ROUTINE
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slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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*status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
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DBG_LEAVE_ROUTINE
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return 0;
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}
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static int hpc_get_adapter_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u8 state;
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
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DBG_ENTER_ROUTINE
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slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
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*status = (state != 0x3) ? 1 : 0;
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DBG_LEAVE_ROUTINE
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return 0;
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}
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@ -523,11 +456,8 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
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{
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struct controller *ctrl = slot->ctrl;
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DBG_ENTER_ROUTINE
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*prog_int = shpc_readb(ctrl, PROG_INTERFACE);
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DBG_LEAVE_ROUTINE
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return 0;
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}
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@ -539,8 +469,6 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
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u8 m66_cap = !!(slot_reg & MHZ66_CAP);
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u8 pi, pcix_cap;
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DBG_ENTER_ROUTINE
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if ((retval = hpc_get_prog_int(slot, &pi)))
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return retval;
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@ -582,21 +510,15 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
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}
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dbg("Adapter speed = %d\n", *value);
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DBG_LEAVE_ROUTINE
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return retval;
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}
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static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
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{
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struct controller *ctrl = slot->ctrl;
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u16 sec_bus_status;
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u8 pi;
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int retval = 0;
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DBG_ENTER_ROUTINE
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pi = shpc_readb(ctrl, PROG_INTERFACE);
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sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
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struct controller *ctrl = slot->ctrl;
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u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
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u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
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if (pi == 2) {
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*mode = (sec_bus_status & 0x0100) >> 8;
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@ -605,21 +527,14 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
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}
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dbg("Mode 1 ECC cap = %d\n", *mode);
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DBG_LEAVE_ROUTINE
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return retval;
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}
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static int hpc_query_power_fault(struct slot * slot)
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{
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struct controller *ctrl = slot->ctrl;
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u32 slot_reg;
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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DBG_ENTER_ROUTINE
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slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
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DBG_LEAVE_ROUTINE
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/* Note: Logic 0 => fault */
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return !(slot_reg & POWER_FAULT);
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}
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@ -666,8 +581,6 @@ static void hpc_release_ctlr(struct controller *ctrl)
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int i;
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u32 slot_reg, serr_int;
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DBG_ENTER_ROUTINE
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/*
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* Mask event interrupts and SERRs of all slots
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*/
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@ -708,61 +621,43 @@ static void hpc_release_ctlr(struct controller *ctrl)
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*/
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if (atomic_dec_and_test(&shpchp_num_controllers))
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destroy_workqueue(shpchp_wq);
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DBG_LEAVE_ROUTINE
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}
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static int hpc_power_on_slot(struct slot * slot)
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{
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int retval;
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DBG_ENTER_ROUTINE
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retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
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if (retval) {
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if (retval)
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err("%s: Write command failed!\n", __FUNCTION__);
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return retval;
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}
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DBG_LEAVE_ROUTINE
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return 0;
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return retval;
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}
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static int hpc_slot_enable(struct slot * slot)
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{
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int retval;
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DBG_ENTER_ROUTINE
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/* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
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retval = shpc_write_cmd(slot, slot->hp_slot,
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SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
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if (retval) {
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if (retval)
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err("%s: Write command failed!\n", __FUNCTION__);
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return retval;
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}
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DBG_LEAVE_ROUTINE
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return 0;
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return retval;
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}
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static int hpc_slot_disable(struct slot * slot)
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{
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int retval;
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DBG_ENTER_ROUTINE
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/* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
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retval = shpc_write_cmd(slot, slot->hp_slot,
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SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
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if (retval) {
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if (retval)
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err("%s: Write command failed!\n", __FUNCTION__);
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return retval;
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}
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DBG_LEAVE_ROUTINE
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return 0;
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return retval;
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}
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static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
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struct controller *ctrl = slot->ctrl;
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u8 pi, cmd;
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DBG_ENTER_ROUTINE
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pi = shpc_readb(ctrl, PROG_INTERFACE);
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if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
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return -EINVAL;
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if (retval)
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err("%s: Write command failed!\n", __FUNCTION__);
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DBG_LEAVE_ROUTINE
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return retval;
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}
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@ -920,8 +812,6 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
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u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
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u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
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DBG_ENTER_ROUTINE
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if (pi == 2) {
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if (slot_avail2 & SLOT_133MHZ_PCIX_533)
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bus_speed = PCI_SPEED_133MHz_PCIX_533;
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*value = bus_speed;
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dbg("Max bus speed = %d\n", bus_speed);
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DBG_LEAVE_ROUTINE
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return retval;
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}
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@ -967,8 +857,6 @@ static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
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u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
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u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
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DBG_ENTER_ROUTINE
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if ((pi == 1) && (speed_mode > 4)) {
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*value = PCI_SPEED_UNKNOWN;
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return -ENODEV;
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}
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dbg("Current bus speed = %d\n", bus_speed);
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DBG_LEAVE_ROUTINE
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return retval;
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}
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@ -1061,8 +948,6 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
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u32 tempdword, slot_reg, slot_config;
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u8 i;
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DBG_ENTER_ROUTINE
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ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
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if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
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dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
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}
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DBG_LEAVE_ROUTINE
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return 0;
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/* We end up here for the many possible ways to fail this API. */
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abort_iounmap:
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iounmap(ctrl->creg);
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abort:
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DBG_LEAVE_ROUTINE
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return rc;
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}
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