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clk: spear3xx: Use proper control register offset
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c
(SPEAr: Switch to common clock framework).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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1 changed files with 1 additions and 1 deletions
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@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
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/* array of all spear 320 clock lookups */
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#ifdef CONFIG_MACH_SPEAR320
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#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
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#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
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#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
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#define SPEAR320_UARTX_PCLK_MASK 0x1
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