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arm64: dts: msm8916: Add cpu cooling maps

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Add cpu cooling maps for cpu passive trip points. The cpu cooling
device states are mapped to cpufreq based scaling frequencies.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Rajendra Nayak 2018-03-07 10:30:02 +05:30 committed by Andy Gross
parent 68ae3d0cac
commit 15ee8f021d
1 changed files with 19 additions and 0 deletions
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19
arch/arm64/boot/dts/qcom/msm8916.dtsi
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@ -15,6 +15,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8916.h> #include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h> #include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/thermal/thermal.h>
/ { / {
model = "Qualcomm Technologies, Inc. MSM8916"; model = "Qualcomm Technologies, Inc. MSM8916";
@ -115,6 +116,7 @@ CPU0: cpu@0 {
cpu-idle-states = <&CPU_SPC>; cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>; clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>; operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
}; };
CPU1: cpu@1 { CPU1: cpu@1 {
@ -126,6 +128,7 @@ CPU1: cpu@1 {
cpu-idle-states = <&CPU_SPC>; cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>; clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>; operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
}; };
CPU2: cpu@2 { CPU2: cpu@2 {
@ -137,6 +140,7 @@ CPU2: cpu@2 {
cpu-idle-states = <&CPU_SPC>; cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>; clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>; operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
}; };
CPU3: cpu@3 { CPU3: cpu@3 {
@ -148,6 +152,7 @@ CPU3: cpu@3 {
cpu-idle-states = <&CPU_SPC>; cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>; clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>; operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
}; };
L2_0: l2-cache { L2_0: l2-cache {
@ -196,6 +201,13 @@ cpu_crit0: trip1 {
type = "critical"; type = "critical";
}; };
}; };
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
}; };
cpu-thermal1 { cpu-thermal1 {
@ -216,6 +228,13 @@ cpu_crit1: trip1 {
type = "critical"; type = "critical";
}; };
}; };
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
}; };
}; };