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clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()

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Fix clock index out of range check for module clocks in
rzg2l_cpg_clk_src_twocell_get().

Fixes: ef3c613ccd ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210617155432.18827-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2021-06-17 16:54:32 +01:00 committed by Geert Uytterhoeven
parent e37868f144
commit 1606e81543
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/renesas/renesas-rzg2l-cpg.c
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@ -222,7 +222,7 @@ static struct clk
case CPG_MOD:
type = "module";
if (clkidx > priv->num_mod_clks) {
if (clkidx >= priv->num_mod_clks) {
dev_err(dev, "Invalid %s clock index %u\n", type,
clkidx);
return ERR_PTR(-EINVAL);