mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
clk: rockchip: Handle clock tree for rk3288w variant
The revision rk3288w has a different clock tree about "hclk_vio" clock, according to the BSP kernel code. This patch handles this difference by detecting which device-tree we are using. If it is a "rockchip,rk3288-cru", let's register the clock tree as it was before. If the device-tree node is "rockchip,rk3288w-cru", we will apply the difference with this version of this SoC. Noticed that this new device-tree compatible must be handled in bootloader such as u-boot. Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com> Link: https://lore.kernel.org/r/20200602080644.11333-2-mylene.josserand@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
parent
7f6ffbb885
commit
1627f68363
1 changed files with 18 additions and 2 deletions
|
@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3288_CLKGATE_CON(3), 0, GFLAGS),
|
||||
DIV(0, "hclk_vio", "aclk_vio0", 0,
|
||||
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3288_CLKGATE_CON(3), 2, GFLAGS),
|
||||
|
@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
|
||||
};
|
||||
|
||||
static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
|
||||
DIV(0, "hclk_vio", "aclk_vio1", 0,
|
||||
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
};
|
||||
|
||||
static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
|
||||
DIV(0, "hclk_vio", "aclk_vio0", 0,
|
||||
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
};
|
||||
|
||||
static const char *const rk3288_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"aclk_peri",
|
||||
|
@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
|
|||
RK3288_GRF_SOC_STATUS1);
|
||||
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
|
||||
ARRAY_SIZE(rk3288_clk_branches));
|
||||
|
||||
if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
|
||||
rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
|
||||
ARRAY_SIZE(rk3288w_hclkvio_branch));
|
||||
else
|
||||
rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
|
||||
ARRAY_SIZE(rk3288_hclkvio_branch));
|
||||
|
||||
rockchip_clk_protect_critical(rk3288_critical_clocks,
|
||||
ARRAY_SIZE(rk3288_critical_clocks));
|
||||
|
||||
|
|
Loading…
Reference in a new issue