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mt76: mt7921: add MAC support
Add Rx packet description parsing, Tx packet description compositon, handle packet recycling and provide MAC information mt76 core needs to support mac80211. Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Co-developed-by: Soul Huang <Soul.Huang@mediatek.com> Signed-off-by: Soul Huang <Soul.Huang@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Sean Wang
Felix Fietkau
parent
1755f6ad0f
commit
163f4d22c1
4 changed files with 2457 additions and 0 deletions
1363
drivers/net/wireless/mediatek/mt76/mt7921/mac.c
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1363
drivers/net/wireless/mediatek/mt76/mt7921/mac.c
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File diff suppressed because it is too large
Load diff
333
drivers/net/wireless/mediatek/mt76/mt7921/mac.h
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333
drivers/net/wireless/mediatek/mt76/mt7921/mac.h
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/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2020 MediaTek Inc. */
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#ifndef __MT7921_MAC_H
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#define __MT7921_MAC_H
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#define MT_CT_PARSE_LEN 72
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#define MT_CT_DMA_BUF_NUM 2
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#define MT_RXD0_LENGTH GENMASK(15, 0)
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#define MT_RXD0_PKT_FLAG GENMASK(19, 16)
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#define MT_RXD0_PKT_TYPE GENMASK(31, 27)
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#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
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#define MT_RXD0_NORMAL_IP_SUM BIT(23)
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#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
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enum rx_pkt_type {
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PKT_TYPE_TXS,
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PKT_TYPE_TXRXV,
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PKT_TYPE_NORMAL,
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PKT_TYPE_RX_DUP_RFB,
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PKT_TYPE_RX_TMR,
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PKT_TYPE_RETRIEVE,
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PKT_TYPE_TXRX_NOTIFY,
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PKT_TYPE_RX_EVENT,
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PKT_TYPE_NORMAL_MCU,
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};
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/* RXD DW1 */
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#define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
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#define MT_RXD1_NORMAL_GROUP_1 BIT(11)
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#define MT_RXD1_NORMAL_GROUP_2 BIT(12)
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#define MT_RXD1_NORMAL_GROUP_3 BIT(13)
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#define MT_RXD1_NORMAL_GROUP_4 BIT(14)
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#define MT_RXD1_NORMAL_GROUP_5 BIT(15)
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#define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
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#define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
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#define MT_RXD1_NORMAL_CM BIT(23)
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#define MT_RXD1_NORMAL_CLM BIT(24)
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#define MT_RXD1_NORMAL_ICV_ERR BIT(25)
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#define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
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#define MT_RXD1_NORMAL_FCS_ERR BIT(27)
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#define MT_RXD1_NORMAL_BAND_IDX BIT(28)
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#define MT_RXD1_NORMAL_SPP_EN BIT(29)
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#define MT_RXD1_NORMAL_ADD_OM BIT(30)
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#define MT_RXD1_NORMAL_SEC_DONE BIT(31)
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/* RXD DW2 */
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#define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
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#define MT_RXD2_NORMAL_CO_ANT BIT(6)
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#define MT_RXD2_NORMAL_BF_CQI BIT(7)
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#define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
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#define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
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#define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
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#define MT_RXD2_NORMAL_TID GENMASK(19, 16)
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#define MT_RXD2_NORMAL_MU_BAR BIT(21)
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#define MT_RXD2_NORMAL_SW_BIT BIT(22)
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#define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
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#define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
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#define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
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#define MT_RXD2_NORMAL_INT_FRAME BIT(26)
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#define MT_RXD2_NORMAL_FRAG BIT(27)
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#define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
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#define MT_RXD2_NORMAL_NDATA BIT(29)
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#define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
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#define MT_RXD2_NORMAL_BF_REPORT BIT(31)
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/* RXD DW3 */
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#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
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#define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
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#define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
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#define MT_RXD3_NORMAL_U2M BIT(0)
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#define MT_RXD3_NORMAL_HTC_VLD BIT(0)
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#define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
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#define MT_RXD3_NORMAL_BEACON_MC BIT(20)
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#define MT_RXD3_NORMAL_BEACON_UC BIT(21)
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#define MT_RXD3_NORMAL_AMSDU BIT(22)
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#define MT_RXD3_NORMAL_MESH BIT(23)
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#define MT_RXD3_NORMAL_MHCP BIT(24)
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#define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
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#define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
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#define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
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#define MT_RXD3_NORMAL_MORE BIT(28)
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#define MT_RXD3_NORMAL_UNWANT BIT(29)
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#define MT_RXD3_NORMAL_RX_DROP BIT(30)
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#define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
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/* RXD DW4 */
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#define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
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#define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
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#define MT_RXD4_NORMAL_CLS BIT(10)
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#define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
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#define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
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#define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
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#define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
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#define MT_RXD3_NORMAL_PF_MODE BIT(29)
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#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
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/* P-RXV */
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#define MT_PRXV_TX_RATE GENMASK(6, 0)
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#define MT_PRXV_TX_DCM BIT(4)
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#define MT_PRXV_TX_ER_SU_106T BIT(5)
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#define MT_PRXV_NSTS GENMASK(9, 7)
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#define MT_PRXV_HT_AD_CODE BIT(11)
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#define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
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#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
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#define MT_PRXV_RCPI3 GENMASK(31, 24)
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#define MT_PRXV_RCPI2 GENMASK(23, 16)
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#define MT_PRXV_RCPI1 GENMASK(15, 8)
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#define MT_PRXV_RCPI0 GENMASK(7, 0)
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/* C-RXV */
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#define MT_CRXV_HT_STBC GENMASK(1, 0)
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#define MT_CRXV_TX_MODE GENMASK(7, 4)
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#define MT_CRXV_FRAME_MODE GENMASK(10, 8)
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#define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
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#define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
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#define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
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#define MT_CRXV_HE_PE_DISAMBIG BIT(23)
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#define MT_CRXV_HE_UPLINK BIT(31)
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#define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
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#define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
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#define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
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#define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
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#define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
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#define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
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#define MT_CRXV_HE_BEAM_CHNG BIT(13)
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#define MT_CRXV_HE_DOPPLER BIT(16)
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#define MT_CRXV_SNR GENMASK(18, 13)
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#define MT_CRXV_FOE_LO GENMASK(31, 19)
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#define MT_CRXV_FOE_HI GENMASK(6, 0)
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#define MT_CRXV_FOE_SHIFT 13
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enum tx_header_format {
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MT_HDR_FORMAT_802_3,
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MT_HDR_FORMAT_CMD,
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MT_HDR_FORMAT_802_11,
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MT_HDR_FORMAT_802_11_EXT,
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};
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enum tx_pkt_type {
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MT_TX_TYPE_CT,
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MT_TX_TYPE_SF,
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MT_TX_TYPE_CMD,
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MT_TX_TYPE_FW,
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};
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enum tx_port_idx {
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MT_TX_PORT_IDX_LMAC,
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MT_TX_PORT_IDX_MCU
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};
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enum tx_mcu_port_q_idx {
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MT_TX_MCU_PORT_RX_Q0 = 0x20,
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MT_TX_MCU_PORT_RX_Q1,
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MT_TX_MCU_PORT_RX_Q2,
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MT_TX_MCU_PORT_RX_Q3,
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MT_TX_MCU_PORT_RX_FWDL = 0x3e
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};
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#define MT_CT_INFO_APPLY_TXD BIT(0)
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#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
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#define MT_CT_INFO_MGMT_FRAME BIT(2)
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#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
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#define MT_CT_INFO_HSR2_TX BIT(4)
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#define MT_CT_INFO_FROM_HOST BIT(7)
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#define MT_TXD_SIZE (8 * 4)
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#define MT_TXD0_Q_IDX GENMASK(31, 25)
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#define MT_TXD0_PKT_FMT GENMASK(24, 23)
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#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
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#define MT_TXD0_TX_BYTES GENMASK(15, 0)
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#define MT_TXD1_LONG_FORMAT BIT(31)
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#define MT_TXD1_TGID BIT(30)
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#define MT_TXD1_OWN_MAC GENMASK(29, 24)
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#define MT_TXD1_AMSDU BIT(23)
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#define MT_TXD1_TID GENMASK(22, 20)
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#define MT_TXD1_HDR_PAD GENMASK(19, 18)
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#define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
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#define MT_TXD1_HDR_INFO GENMASK(15, 11)
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#define MT_TXD1_ETH_802_3 BIT(15)
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#define MT_TXD1_VTA BIT(10)
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#define MT_TXD1_WLAN_IDX GENMASK(9, 0)
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#define MT_TXD2_FIX_RATE BIT(31)
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#define MT_TXD2_FIXED_RATE BIT(30)
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#define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
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#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
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#define MT_TXD2_FRAG GENMASK(15, 14)
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#define MT_TXD2_HTC_VLD BIT(13)
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#define MT_TXD2_DURATION BIT(12)
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#define MT_TXD2_BIP BIT(11)
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#define MT_TXD2_MULTICAST BIT(10)
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#define MT_TXD2_RTS BIT(9)
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#define MT_TXD2_SOUNDING BIT(8)
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#define MT_TXD2_NDPA BIT(7)
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#define MT_TXD2_NDP BIT(6)
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#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
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#define MT_TXD2_SUB_TYPE GENMASK(3, 0)
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#define MT_TXD3_SN_VALID BIT(31)
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#define MT_TXD3_PN_VALID BIT(30)
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#define MT_TXD3_SW_POWER_MGMT BIT(29)
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#define MT_TXD3_BA_DISABLE BIT(28)
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#define MT_TXD3_SEQ GENMASK(27, 16)
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#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
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#define MT_TXD3_TX_COUNT GENMASK(10, 6)
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#define MT_TXD3_TIMING_MEASURE BIT(5)
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#define MT_TXD3_DAS BIT(4)
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#define MT_TXD3_EEOSP BIT(3)
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#define MT_TXD3_EMRD BIT(2)
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#define MT_TXD3_PROTECT_FRAME BIT(1)
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#define MT_TXD3_NO_ACK BIT(0)
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#define MT_TXD4_PN_LOW GENMASK(31, 0)
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#define MT_TXD5_PN_HIGH GENMASK(31, 16)
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#define MT_TXD5_MD BIT(15)
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#define MT_TXD5_ADD_BA BIT(14)
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#define MT_TXD5_TX_STATUS_HOST BIT(10)
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#define MT_TXD5_TX_STATUS_MCU BIT(9)
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#define MT_TXD5_TX_STATUS_FMT BIT(8)
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#define MT_TXD5_PID GENMASK(7, 0)
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#define MT_TXD6_TX_IBF BIT(31)
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#define MT_TXD6_TX_EBF BIT(30)
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#define MT_TXD6_TX_RATE GENMASK(29, 16)
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#define MT_TXD6_SGI GENMASK(15, 14)
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#define MT_TXD6_HELTF GENMASK(13, 12)
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#define MT_TXD6_LDPC BIT(11)
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#define MT_TXD6_SPE_ID_IDX BIT(10)
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#define MT_TXD6_ANT_ID GENMASK(7, 4)
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#define MT_TXD6_DYN_BW BIT(3)
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#define MT_TXD6_FIXED_BW BIT(2)
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#define MT_TXD6_BW GENMASK(1, 0)
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#define MT_TXD7_TXD_LEN GENMASK(31, 30)
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#define MT_TXD7_UDP_TCP_SUM BIT(29)
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#define MT_TXD7_IP_SUM BIT(28)
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#define MT_TXD7_TYPE GENMASK(21, 20)
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#define MT_TXD7_SUB_TYPE GENMASK(19, 16)
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#define MT_TXD7_PSE_FID GENMASK(27, 16)
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#define MT_TXD7_SPE_IDX GENMASK(15, 11)
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#define MT_TXD7_HW_AMSDU BIT(10)
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#define MT_TXD7_TX_TIME GENMASK(9, 0)
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#define MT_TX_RATE_STBC BIT(13)
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#define MT_TX_RATE_NSS GENMASK(12, 10)
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#define MT_TX_RATE_MODE GENMASK(9, 6)
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#define MT_TX_RATE_SU_EXT_TONE BIT(5)
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#define MT_TX_RATE_DCM BIT(4)
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#define MT_TX_RATE_IDX GENMASK(3, 0)
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#define MT_TXP_MAX_BUF_NUM 6
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struct mt7921_txp {
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__le16 flags;
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__le16 token;
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u8 bss_idx;
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__le16 rept_wds_wcid;
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u8 nbuf;
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__le32 buf[MT_TXP_MAX_BUF_NUM];
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__le16 len[MT_TXP_MAX_BUF_NUM];
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} __packed __aligned(4);
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struct mt7921_tx_free {
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__le16 rx_byte_cnt;
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__le16 ctrl;
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u8 txd_cnt;
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u8 rsv[3];
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__le32 info[];
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} __packed __aligned(4);
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#define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
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#define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
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#define MT_TX_FREE_LATENCY GENMASK(12, 0)
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/* 0: success, others: dropped */
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#define MT_TX_FREE_STATUS GENMASK(14, 13)
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#define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
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#define MT_TX_FREE_PAIR BIT(31)
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/* will support this field in further revision */
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#define MT_TX_FREE_RATE GENMASK(13, 0)
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static inline struct mt7921_txp_common *
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mt7921_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
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{
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u8 *txwi;
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if (!t)
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return NULL;
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txwi = mt76_get_txwi_ptr(dev, t);
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return (struct mt7921_txp_common *)(txwi + MT_TXD_SIZE);
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}
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#define MT_HW_TXP_MAX_MSDU_NUM 4
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#define MT_HW_TXP_MAX_BUF_NUM 4
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#define MT_MSDU_ID_VALID BIT(15)
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#define MT_TXD_LEN_MASK GENMASK(11, 0)
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#define MT_TXD_LEN_MSDU_LAST BIT(14)
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#define MT_TXD_LEN_AMSDU_LAST BIT(15)
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#define MT_TXD_LEN_LAST BIT(15)
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struct mt7921_txp_ptr {
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__le32 buf0;
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__le16 len0;
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__le16 len1;
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__le32 buf1;
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} __packed __aligned(4);
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struct mt7921_hw_txp {
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__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
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struct mt7921_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
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} __packed __aligned(4);
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struct mt7921_txp_common {
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union {
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struct mt7921_hw_txp hw;
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};
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};
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#endif
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347
drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h
Normal file
347
drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h
Normal file
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/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2020 MediaTek Inc. */
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#ifndef __MT7921_H
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#define __MT7921_H
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#include <linux/interrupt.h>
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#include <linux/ktime.h>
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#include "../mt76.h"
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#include "regs.h"
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#define MT7921_MAX_INTERFACES 4
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#define MT7921_MAX_WMM_SETS 4
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#define MT7921_WTBL_SIZE 20
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#define MT7921_WTBL_RESERVED (MT7921_WTBL_SIZE - 1)
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#define MT7921_WTBL_STA (MT7921_WTBL_RESERVED - \
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MT7921_MAX_INTERFACES)
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#define MT7921_HW_SCAN_TIMEOUT (HZ / 10)
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#define MT7921_WATCHDOG_TIME (HZ / 10)
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#define MT7921_RESET_TIMEOUT (30 * HZ)
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|
||||
#define MT7921_TX_RING_SIZE 2048
|
||||
#define MT7921_TX_MCU_RING_SIZE 256
|
||||
#define MT7921_TX_FWDL_RING_SIZE 128
|
||||
|
||||
#define MT7921_RX_RING_SIZE 1536
|
||||
#define MT7921_RX_MCU_RING_SIZE 512
|
||||
|
||||
#define MT7921_FIRMWARE_WM "mediatek/WIFI_RAM_CODE_MT7961_1.bin"
|
||||
#define MT7921_ROM_PATCH "mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin"
|
||||
|
||||
#define MT7921_EEPROM_SIZE 3584
|
||||
#define MT7921_TOKEN_SIZE 8192
|
||||
#define MT7921_TOKEN_FREE_THR 64
|
||||
|
||||
#define MT7921_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
|
||||
#define MT7921_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
|
||||
#define MT7921_5G_RATE_DEFAULT 0x4b /* OFDM 6M */
|
||||
#define MT7921_2G_RATE_DEFAULT 0x0 /* CCK 1M */
|
||||
|
||||
#define MT7921_SKU_RATE_NUM 161
|
||||
#define MT7921_SKU_MAX_DELTA_IDX MT7921_SKU_RATE_NUM
|
||||
#define MT7921_SKU_TABLE_SIZE (MT7921_SKU_RATE_NUM + 1)
|
||||
|
||||
#define MT7921_SCAN_IE_LEN 600
|
||||
|
||||
struct mt7921_vif;
|
||||
struct mt7921_sta;
|
||||
|
||||
enum mt7921_txq_id {
|
||||
MT7921_TXQ_BAND0,
|
||||
MT7921_TXQ_BAND1,
|
||||
MT7921_TXQ_FWDL = 16,
|
||||
MT7921_TXQ_MCU_WM,
|
||||
};
|
||||
|
||||
enum mt7921_rxq_id {
|
||||
MT7921_RXQ_BAND0 = 0,
|
||||
MT7921_RXQ_BAND1,
|
||||
MT7921_RXQ_MCU_WM = 0,
|
||||
};
|
||||
|
||||
struct mt7921_sta_stats {
|
||||
struct rate_info prob_rate;
|
||||
struct rate_info tx_rate;
|
||||
|
||||
unsigned long per;
|
||||
unsigned long changed;
|
||||
unsigned long jiffies;
|
||||
};
|
||||
|
||||
struct mt7921_sta_key_conf {
|
||||
s8 keyidx;
|
||||
u8 key[16];
|
||||
};
|
||||
|
||||
struct mt7921_sta {
|
||||
struct mt76_wcid wcid; /* must be first */
|
||||
|
||||
struct mt7921_vif *vif;
|
||||
|
||||
struct list_head stats_list;
|
||||
struct list_head poll_list;
|
||||
u32 airtime_ac[8];
|
||||
|
||||
struct mt7921_sta_stats stats;
|
||||
|
||||
unsigned long ampdu_state;
|
||||
|
||||
struct mt7921_sta_key_conf bip;
|
||||
};
|
||||
|
||||
struct mt7921_vif {
|
||||
struct mt76_vif mt76; /* must be first */
|
||||
|
||||
struct mt7921_sta sta;
|
||||
struct mt7921_phy *phy;
|
||||
|
||||
struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
|
||||
};
|
||||
|
||||
struct mib_stats {
|
||||
u16 ack_fail_cnt;
|
||||
u16 fcs_err_cnt;
|
||||
u16 rts_cnt;
|
||||
u16 rts_retries_cnt;
|
||||
u16 ba_miss_cnt;
|
||||
};
|
||||
|
||||
struct mt7921_phy {
|
||||
struct mt76_phy *mt76;
|
||||
struct mt7921_dev *dev;
|
||||
|
||||
struct ieee80211_sband_iftype_data iftype[2][NUM_NL80211_IFTYPES];
|
||||
|
||||
struct ieee80211_vif *monitor_vif;
|
||||
|
||||
u32 rxfilter;
|
||||
u64 omac_mask;
|
||||
|
||||
u16 noise;
|
||||
|
||||
s16 coverage_class;
|
||||
u8 slottime;
|
||||
|
||||
__le32 rx_ampdu_ts;
|
||||
u32 ampdu_ref;
|
||||
|
||||
struct mib_stats mib;
|
||||
struct list_head stats_list;
|
||||
|
||||
struct sk_buff_head scan_event_list;
|
||||
struct delayed_work scan_work;
|
||||
};
|
||||
|
||||
struct mt7921_dev {
|
||||
union { /* must be first */
|
||||
struct mt76_dev mt76;
|
||||
struct mt76_phy mphy;
|
||||
};
|
||||
|
||||
const struct mt76_bus_ops *bus_ops;
|
||||
struct mt7921_phy phy;
|
||||
struct tasklet_struct irq_tasklet;
|
||||
|
||||
u16 chainmask;
|
||||
|
||||
struct work_struct init_work;
|
||||
struct work_struct reset_work;
|
||||
wait_queue_head_t reset_wait;
|
||||
u32 reset_state;
|
||||
|
||||
struct list_head sta_poll_list;
|
||||
spinlock_t sta_poll_lock;
|
||||
|
||||
spinlock_t token_lock;
|
||||
int token_count;
|
||||
struct idr token;
|
||||
|
||||
u8 fw_debug;
|
||||
};
|
||||
|
||||
enum {
|
||||
HW_BSSID_0 = 0x0,
|
||||
HW_BSSID_1,
|
||||
HW_BSSID_2,
|
||||
HW_BSSID_3,
|
||||
HW_BSSID_MAX = HW_BSSID_3,
|
||||
EXT_BSSID_START = 0x10,
|
||||
EXT_BSSID_1,
|
||||
EXT_BSSID_15 = 0x1f,
|
||||
EXT_BSSID_MAX = EXT_BSSID_15,
|
||||
REPEATER_BSSID_START = 0x20,
|
||||
REPEATER_BSSID_MAX = 0x3f,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT_LMAC_AC00,
|
||||
MT_LMAC_AC01,
|
||||
MT_LMAC_AC02,
|
||||
MT_LMAC_AC03,
|
||||
MT_LMAC_ALTX0 = 0x10,
|
||||
MT_LMAC_BMC0,
|
||||
MT_LMAC_BCN0,
|
||||
};
|
||||
|
||||
static inline struct mt7921_phy *
|
||||
mt7921_hw_phy(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct mt76_phy *phy = hw->priv;
|
||||
|
||||
return phy->priv;
|
||||
}
|
||||
|
||||
static inline struct mt7921_dev *
|
||||
mt7921_hw_dev(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct mt76_phy *phy = hw->priv;
|
||||
|
||||
return container_of(phy->dev, struct mt7921_dev, mt76);
|
||||
}
|
||||
|
||||
static inline u8 mt7921_lmac_mapping(struct mt7921_dev *dev, u8 ac)
|
||||
{
|
||||
/* LMAC uses the reverse order of mac80211 AC indexes */
|
||||
return 3 - ac;
|
||||
}
|
||||
|
||||
extern const struct ieee80211_ops mt7921_ops;
|
||||
extern struct pci_driver mt7921_pci_driver;
|
||||
|
||||
u32 mt7921_reg_map(struct mt7921_dev *dev, u32 addr);
|
||||
|
||||
int mt7921_register_device(struct mt7921_dev *dev);
|
||||
void mt7921_unregister_device(struct mt7921_dev *dev);
|
||||
int mt7921_eeprom_init(struct mt7921_dev *dev);
|
||||
void mt7921_eeprom_parse_band_config(struct mt7921_phy *phy);
|
||||
int mt7921_eeprom_get_target_power(struct mt7921_dev *dev,
|
||||
struct ieee80211_channel *chan,
|
||||
u8 chain_idx);
|
||||
void mt7921_eeprom_init_sku(struct mt7921_dev *dev);
|
||||
int mt7921_dma_init(struct mt7921_dev *dev);
|
||||
void mt7921_dma_prefetch(struct mt7921_dev *dev);
|
||||
void mt7921_dma_cleanup(struct mt7921_dev *dev);
|
||||
int mt7921_mcu_init(struct mt7921_dev *dev);
|
||||
int mt7921_mcu_add_bss_info(struct mt7921_phy *phy,
|
||||
struct ieee80211_vif *vif, int enable);
|
||||
int mt7921_mcu_add_key(struct mt7921_dev *dev, struct ieee80211_vif *vif,
|
||||
struct mt7921_sta *msta, struct ieee80211_key_conf *key,
|
||||
enum set_key_cmd cmd);
|
||||
int mt7921_set_channel(struct mt7921_phy *phy);
|
||||
int mt7921_mcu_set_chan_info(struct mt7921_phy *phy, int cmd);
|
||||
int mt7921_mcu_set_tx(struct mt7921_dev *dev, struct ieee80211_vif *vif);
|
||||
int mt7921_mcu_set_eeprom(struct mt7921_dev *dev);
|
||||
int mt7921_mcu_get_eeprom(struct mt7921_dev *dev, u32 offset);
|
||||
int mt7921_mcu_set_mac(struct mt7921_dev *dev, int band, bool enable,
|
||||
bool hdr_trans);
|
||||
int mt7921_mcu_set_rts_thresh(struct mt7921_phy *phy, u32 val);
|
||||
int mt7921_mcu_fw_log_2_host(struct mt7921_dev *dev, u8 ctrl);
|
||||
void mt7921_mcu_rx_event(struct mt7921_dev *dev, struct sk_buff *skb);
|
||||
void mt7921_mcu_exit(struct mt7921_dev *dev);
|
||||
|
||||
static inline bool is_mt7921(struct mt76_dev *dev)
|
||||
{
|
||||
return mt76_chip(dev) == 0x7961;
|
||||
}
|
||||
|
||||
static inline void mt7921_irq_enable(struct mt7921_dev *dev, u32 mask)
|
||||
{
|
||||
mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
|
||||
|
||||
tasklet_schedule(&dev->irq_tasklet);
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mt7921_reg_map_l1(struct mt7921_dev *dev, u32 addr)
|
||||
{
|
||||
u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
|
||||
u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
|
||||
|
||||
mt76_rmw_field(dev, MT_HIF_REMAP_L1, MT_HIF_REMAP_L1_MASK, base);
|
||||
/* use read to push write */
|
||||
mt76_rr(dev, MT_HIF_REMAP_L1);
|
||||
|
||||
return MT_HIF_REMAP_BASE_L1 + offset;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mt7921_l1_rr(struct mt7921_dev *dev, u32 addr)
|
||||
{
|
||||
return mt76_rr(dev, mt7921_reg_map_l1(dev, addr));
|
||||
}
|
||||
|
||||
static inline void
|
||||
mt7921_l1_wr(struct mt7921_dev *dev, u32 addr, u32 val)
|
||||
{
|
||||
mt76_wr(dev, mt7921_reg_map_l1(dev, addr), val);
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mt7921_l1_rmw(struct mt7921_dev *dev, u32 addr, u32 mask, u32 val)
|
||||
{
|
||||
val |= mt7921_l1_rr(dev, addr) & ~mask;
|
||||
mt7921_l1_wr(dev, addr, val);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
#define mt7921_l1_set(dev, addr, val) mt7921_l1_rmw(dev, addr, 0, val)
|
||||
#define mt7921_l1_clear(dev, addr, val) mt7921_l1_rmw(dev, addr, val, 0)
|
||||
|
||||
bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask);
|
||||
void mt7921_mac_reset_counters(struct mt7921_phy *phy);
|
||||
void mt7921_mac_write_txwi(struct mt7921_dev *dev, __le32 *txwi,
|
||||
struct sk_buff *skb, struct mt76_wcid *wcid,
|
||||
struct ieee80211_key_conf *key, bool beacon);
|
||||
void mt7921_mac_set_timing(struct mt7921_phy *phy);
|
||||
int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb);
|
||||
void mt7921_mac_fill_rx_vector(struct mt7921_dev *dev, struct sk_buff *skb);
|
||||
void mt7921_mac_tx_free(struct mt7921_dev *dev, struct sk_buff *skb);
|
||||
int mt7921_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta);
|
||||
void mt7921_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta);
|
||||
void mt7921_mac_work(struct work_struct *work);
|
||||
void mt7921_mac_reset_work(struct work_struct *work);
|
||||
int mt7921_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
|
||||
enum mt76_txq_id qid, struct mt76_wcid *wcid,
|
||||
struct ieee80211_sta *sta,
|
||||
struct mt76_tx_info *tx_info);
|
||||
void mt7921_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
|
||||
int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc);
|
||||
void mt7921_tx_token_put(struct mt7921_dev *dev);
|
||||
void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
|
||||
struct sk_buff *skb);
|
||||
void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
|
||||
void mt7921_stats_work(struct work_struct *work);
|
||||
void mt7921_txp_skb_unmap(struct mt76_dev *dev,
|
||||
struct mt76_txwi_cache *txwi);
|
||||
void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
|
||||
void mt7921_update_channel(struct mt76_dev *mdev);
|
||||
int mt7921_init_debugfs(struct mt7921_dev *dev);
|
||||
int
|
||||
mt7921_mcu_uni_add_dev(struct mt7921_dev *dev,
|
||||
struct ieee80211_vif *vif, bool enable);
|
||||
int
|
||||
mt7921_mcu_uni_add_bss(struct mt7921_phy *phy, struct ieee80211_vif *vif,
|
||||
bool enable);
|
||||
|
||||
int
|
||||
mt7921_mcu_uni_add_sta(struct mt7921_dev *dev, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, bool enable);
|
||||
int mt7921_mcu_uni_tx_ba(struct mt7921_dev *dev,
|
||||
struct ieee80211_ampdu_params *params,
|
||||
bool enable);
|
||||
int mt7921_mcu_uni_rx_ba(struct mt7921_dev *dev,
|
||||
struct ieee80211_ampdu_params *params,
|
||||
bool enable);
|
||||
void mt7921_scan_work(struct work_struct *work);
|
||||
int mt7921_mcu_set_channel_domain(struct mt7921_phy *phy);
|
||||
int mt7921_mcu_hw_scan(struct mt7921_phy *phy, struct ieee80211_vif *vif,
|
||||
struct ieee80211_scan_request *scan_req);
|
||||
int mt7921_mcu_cancel_hw_scan(struct mt7921_phy *phy,
|
||||
struct ieee80211_vif *vif);
|
||||
u32 mt7921_get_wtbl_info(struct mt7921_dev *dev, u16 wlan_idx);
|
||||
#endif
|
||||
414
drivers/net/wireless/mediatek/mt76/mt7921/regs.h
Normal file
414
drivers/net/wireless/mediatek/mt76/mt7921/regs.h
Normal file
|
|
@ -0,0 +1,414 @@
|
|||
/* SPDX-License-Identifier: ISC */
|
||||
/* Copyright (C) 2020 MediaTek Inc. */
|
||||
|
||||
#ifndef __MT7921_REGS_H
|
||||
#define __MT7921_REGS_H
|
||||
|
||||
/* MCU WFDMA1 */
|
||||
#define MT_MCU_WFDMA1_BASE 0x3000
|
||||
#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
|
||||
|
||||
#define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
|
||||
#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
|
||||
#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
|
||||
#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
|
||||
#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
|
||||
|
||||
#define MT_PLE_BASE 0x8000
|
||||
#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
|
||||
|
||||
#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
|
||||
#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
|
||||
#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
|
||||
#define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
|
||||
|
||||
#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
|
||||
((n) << 2))
|
||||
#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
|
||||
|
||||
#define MT_MDP_BASE 0xf000
|
||||
#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
|
||||
|
||||
#define MT_MDP_DCR0 MT_MDP(0x000)
|
||||
#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
|
||||
#define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
|
||||
|
||||
#define MT_MDP_DCR1 MT_MDP(0x004)
|
||||
#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
|
||||
|
||||
#define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
|
||||
#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
|
||||
#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
|
||||
#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
|
||||
|
||||
#define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
|
||||
#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
|
||||
#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
|
||||
#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
|
||||
#define MT_MDP_TO_HIF 0
|
||||
#define MT_MDP_TO_WM 1
|
||||
|
||||
/* TMAC: band 0(0x21000), band 1(0xa1000) */
|
||||
#define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000)
|
||||
#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
|
||||
#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
|
||||
|
||||
#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
|
||||
#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
|
||||
#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
|
||||
#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
|
||||
|
||||
#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
|
||||
#define MT_IFS_EIFS GENMASK(8, 0)
|
||||
#define MT_IFS_RIFS GENMASK(14, 10)
|
||||
#define MT_IFS_SIFS GENMASK(22, 16)
|
||||
#define MT_IFS_SLOT GENMASK(30, 24)
|
||||
|
||||
#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
|
||||
#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
|
||||
#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
|
||||
#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
|
||||
|
||||
#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c)
|
||||
#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0)
|
||||
|
||||
#define MT_WF_DMA_BASE(_band) ((_band) ? 0xa1e00 : 0x21e00)
|
||||
#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
|
||||
#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
|
||||
#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
|
||||
|
||||
/* LPON: band 0(0x24200), band 1(0xa4200) */
|
||||
#define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200)
|
||||
#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
|
||||
#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084)
|
||||
|
||||
#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4)
|
||||
#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
|
||||
#define MT_LPON_TCR_SW_WRITE BIT(0)
|
||||
|
||||
/* MIB: band 0(0x24800), band 1(0xa4800) */
|
||||
#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
|
||||
#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
|
||||
#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
|
||||
|
||||
#define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
|
||||
#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
|
||||
|
||||
#define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
|
||||
#define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
|
||||
|
||||
#define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090)
|
||||
#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
|
||||
|
||||
#define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098)
|
||||
#define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
|
||||
#define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c)
|
||||
#define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
|
||||
|
||||
#define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
|
||||
#define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
|
||||
#define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
|
||||
|
||||
#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
|
||||
#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
|
||||
#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
|
||||
|
||||
#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
|
||||
#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
|
||||
#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
|
||||
|
||||
#define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4))
|
||||
#define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)
|
||||
|
||||
#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2))
|
||||
#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2))
|
||||
#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2))
|
||||
#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
|
||||
|
||||
#define MT_WTBLON_TOP_BASE 0x34000
|
||||
#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
|
||||
#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0)
|
||||
#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
|
||||
|
||||
#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030)
|
||||
#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
|
||||
#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
|
||||
#define MT_WTBL_UPDATE_BUSY BIT(31)
|
||||
|
||||
#define MT_WTBL_BASE 0x38000
|
||||
#define MT_WTBL_LMAC_ID GENMASK(14, 8)
|
||||
#define MT_WTBL_LMAC_DW GENMASK(7, 2)
|
||||
#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
|
||||
FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
|
||||
FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
|
||||
|
||||
/* AGG: band 0(0x20800), band 1(0xa0800) */
|
||||
#define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800)
|
||||
#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4)
|
||||
#define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4)
|
||||
#define MT_AGG_PCR0_MM_PROT BIT(0)
|
||||
#define MT_AGG_PCR0_GF_PROT BIT(1)
|
||||
#define MT_AGG_PCR0_BW20_PROT BIT(2)
|
||||
#define MT_AGG_PCR0_BW40_PROT BIT(4)
|
||||
#define MT_AGG_PCR0_BW80_PROT BIT(6)
|
||||
#define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8)
|
||||
#define MT_AGG_PCR0_VHT_PROT BIT(13)
|
||||
#define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
|
||||
|
||||
#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
|
||||
#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
|
||||
|
||||
#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
|
||||
#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
|
||||
#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
|
||||
|
||||
#define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098)
|
||||
#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)
|
||||
#define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
|
||||
#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)
|
||||
#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)
|
||||
|
||||
#define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0)
|
||||
#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4)
|
||||
|
||||
/* ARB: band 0(0x20c00), band 1(0xa0c00) */
|
||||
#define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00)
|
||||
#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
|
||||
#define MT_ARB_SCR_TX_DISABLE BIT(8)
|
||||
#define MT_ARB_SCR_RX_DISABLE BIT(9)
|
||||
|
||||
#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4)
|
||||
|
||||
/* RMAC: band 0(0x21400), band 1(0xa1400) */
|
||||
#define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400)
|
||||
#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
|
||||
|
||||
#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
|
||||
#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
|
||||
#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
|
||||
#define MT_WF_RFCR_DROP_VERSION BIT(3)
|
||||
#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
|
||||
#define MT_WF_RFCR_DROP_MCAST BIT(5)
|
||||
#define MT_WF_RFCR_DROP_BCAST BIT(6)
|
||||
#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
|
||||
#define MT_WF_RFCR_DROP_A3_MAC BIT(8)
|
||||
#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
|
||||
#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
|
||||
#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
|
||||
#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
|
||||
#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
|
||||
#define MT_WF_RFCR_DROP_CTS BIT(14)
|
||||
#define MT_WF_RFCR_DROP_RTS BIT(15)
|
||||
#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
|
||||
#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
|
||||
#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
|
||||
#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
|
||||
#define MT_WF_RFCR_DROP_NDPA BIT(20)
|
||||
#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
|
||||
|
||||
#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
|
||||
#define MT_WF_RFCR1_DROP_ACK BIT(4)
|
||||
#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
|
||||
#define MT_WF_RFCR1_DROP_BA BIT(6)
|
||||
#define MT_WF_RFCR1_DROP_CFEND BIT(7)
|
||||
#define MT_WF_RFCR1_DROP_CFACK BIT(8)
|
||||
|
||||
#define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4)
|
||||
#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
|
||||
#define MT_WF_RMAC_MIB_RXTIME_EN BIT(30)
|
||||
|
||||
#define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8)
|
||||
#define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
|
||||
#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
|
||||
|
||||
/* WFDMA0 */
|
||||
#define MT_WFDMA0_BASE 0xd4000
|
||||
#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
|
||||
|
||||
#define MT_WFDMA0_RST MT_WFDMA0(0x100)
|
||||
#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
|
||||
#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
|
||||
|
||||
#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
|
||||
#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
|
||||
#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
|
||||
#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
|
||||
|
||||
#define MT_MCU_CMD MT_WFDMA0(0x1f0)
|
||||
#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
|
||||
#define MT_MCU_CMD_STOP_DMA BIT(2)
|
||||
#define MT_MCU_CMD_RESET_DONE BIT(3)
|
||||
#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
|
||||
#define MT_MCU_CMD_NORMAL_STATE BIT(5)
|
||||
#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
|
||||
|
||||
#define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200)
|
||||
#define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */
|
||||
#define HOST_RX_DONE_INT_STS2 BIT(2) /* Rx data */
|
||||
#define HOST_RX_DONE_INT_STS4 BIT(22) /* Rx mcu after fw downloaded */
|
||||
#define HOST_TX_DONE_INT_STS16 BIT(26)
|
||||
#define HOST_TX_DONE_INT_STS17 BIT(27) /* MCU tx done*/
|
||||
|
||||
#define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
|
||||
#define HOST_RX_DONE_INT_ENA0 BIT(0)
|
||||
#define HOST_RX_DONE_INT_ENA1 BIT(1)
|
||||
#define HOST_RX_DONE_INT_ENA2 BIT(2)
|
||||
#define HOST_RX_DONE_INT_ENA3 BIT(3)
|
||||
#define HOST_TX_DONE_INT_ENA0 BIT(4)
|
||||
#define HOST_TX_DONE_INT_ENA1 BIT(5)
|
||||
#define HOST_TX_DONE_INT_ENA2 BIT(6)
|
||||
#define HOST_TX_DONE_INT_ENA3 BIT(7)
|
||||
#define HOST_TX_DONE_INT_ENA4 BIT(8)
|
||||
#define HOST_TX_DONE_INT_ENA5 BIT(9)
|
||||
#define HOST_TX_DONE_INT_ENA6 BIT(10)
|
||||
#define HOST_TX_DONE_INT_ENA7 BIT(11)
|
||||
#define HOST_TX_DONE_INT_ENA8 BIT(12)
|
||||
#define HOST_TX_DONE_INT_ENA9 BIT(13)
|
||||
#define HOST_TX_DONE_INT_ENA10 BIT(14)
|
||||
#define HOST_TX_DONE_INT_ENA11 BIT(15)
|
||||
#define HOST_TX_DONE_INT_ENA12 BIT(16)
|
||||
#define HOST_TX_DONE_INT_ENA13 BIT(17)
|
||||
#define HOST_TX_DONE_INT_ENA14 BIT(18)
|
||||
#define HOST_RX_COHERENT_EN BIT(20)
|
||||
#define HOST_TX_COHERENT_EN BIT(21)
|
||||
#define HOST_RX_DONE_INT_ENA4 BIT(22)
|
||||
#define HOST_RX_DONE_INT_ENA5 BIT(23)
|
||||
#define HOST_TX_DONE_INT_ENA16 BIT(26)
|
||||
#define HOST_TX_DONE_INT_ENA17 BIT(27)
|
||||
#define MCU2HOST_SW_INT_ENA BIT(29)
|
||||
#define HOST_TX_DONE_INT_ENA18 BIT(30)
|
||||
|
||||
/* WFDMA interrupt */
|
||||
#define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2
|
||||
#define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0
|
||||
#define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA4
|
||||
#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \
|
||||
MT_INT_RX_DONE_WM | \
|
||||
MT_INT_RX_DONE_WM2)
|
||||
#define MT_INT_TX_DONE_MCU_WM HOST_TX_DONE_INT_ENA17
|
||||
#define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16
|
||||
#define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0
|
||||
#define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA
|
||||
|
||||
#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \
|
||||
MT_INT_TX_DONE_FWDL)
|
||||
#define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \
|
||||
MT_INT_TX_DONE_BAND0 | \
|
||||
GENMASK(18, 4))
|
||||
|
||||
#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
|
||||
#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
|
||||
#define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1)
|
||||
#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
|
||||
#define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3)
|
||||
#define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6)
|
||||
#define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
|
||||
#define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15)
|
||||
#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
|
||||
#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
|
||||
#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
|
||||
#define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30)
|
||||
|
||||
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
|
||||
#define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
|
||||
#define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE BIT(6)
|
||||
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
|
||||
|
||||
#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
|
||||
|
||||
#define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600)
|
||||
#define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604)
|
||||
#define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608)
|
||||
#define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c)
|
||||
#define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610)
|
||||
#define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614)
|
||||
#define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618)
|
||||
#define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640)
|
||||
#define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644)
|
||||
|
||||
#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
|
||||
#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
|
||||
#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
|
||||
#define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c)
|
||||
#define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690)
|
||||
#define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694)
|
||||
|
||||
#define MT_TX_RING_BASE MT_WFDMA0(0x300)
|
||||
#define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500)
|
||||
|
||||
/* WFDMA CSR */
|
||||
#define MT_WFDMA_EXT_CSR_BASE 0xd7000
|
||||
#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
|
||||
#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
|
||||
#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
|
||||
|
||||
#define MT_INFRA_CFG_BASE 0xfe000
|
||||
#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
|
||||
|
||||
#define MT_HIF_REMAP_L1 MT_INFRA(0x260)
|
||||
#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
|
||||
#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
|
||||
#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
|
||||
#define MT_HIF_REMAP_BASE_L1 0xe0000
|
||||
|
||||
#define MT_SWDEF_BASE 0x41f200
|
||||
#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
|
||||
#define MT_SWDEF_MODE MT_SWDEF(0x3c)
|
||||
#define MT_SWDEF_NORMAL_MODE 0
|
||||
#define MT_SWDEF_ICAP_MODE 1
|
||||
#define MT_SWDEF_SPECTRUM_MODE 2
|
||||
|
||||
#define MT_TOP_BASE 0x18060000
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#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
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|
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#define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
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#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
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#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
|
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|
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#define MT_TOP_MISC MT_TOP(0xf0)
|
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#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
|
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|
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#define MT_HW_BOUND 0x70010020
|
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#define MT_HW_CHIPID 0x70010200
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#define MT_HW_REV 0x70010204
|
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|
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#define MT_PCIE_MAC_BASE 0x74030000
|
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#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
|
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#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
|
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|
||||
#define MT_DMA_SHDL(ofs) (0xd6000 + (ofs))
|
||||
#define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004)
|
||||
#define MT_DMASHDL_DMASHDL_BYPASS BIT(28)
|
||||
#define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008)
|
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#define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c)
|
||||
#define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010)
|
||||
#define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c)
|
||||
#define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
|
||||
#define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)
|
||||
|
||||
#define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2))
|
||||
#define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
|
||||
#define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)
|
||||
|
||||
#define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2))
|
||||
#define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
|
||||
#define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8))
|
||||
|
||||
#define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2))
|
||||
|
||||
#define MT_CONN_ON_MISC 0x7c0600f0
|
||||
#define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue