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arm64: dts: mt8183: add scp node

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Add scp node to mt8183 and mt8183-evb

Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Link: https://lore.kernel.org/r/20191112110330.179649-5-pihsun@chromium.org
Link: https://lore.kernel.org/r/20200909081422.2412795-1-pihsun@chromium.org
[mb: squashed both patches]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Eddie Huang 2019-11-12 19:03:27 +08:00 committed by Matthias Brugger
parent 9d955478a8
commit 1652dbf736
3 changed files with 53 additions and 0 deletions
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11
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View file

@ -25,6 +25,17 @@ memory@40000000 {
chosen {
stdout-path = "serial0:921600n8";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
};
&auxadc {

30
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View file

@ -90,6 +90,18 @@ pp3300_alw: regulator6 {
regulator-max-microvolt = <3300000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
max98357a: codec0 {
compatible = "maxim,max98357a";
sdmode-gpios = <&pio 175 0>;
@ -524,6 +536,13 @@ pins_clk {
};
};
scp_pins: scp {
pins_scp_uart {
pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
<PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
};
};
spi0_pins: spi0 {
pins_spi{
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
@ -651,6 +670,17 @@ pins_wifi_wakeup {
};
};
&scp {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&scp_pins>;
cros_ec {
compatible = "google,cros-ec-rpmsg";
mtk,rpmsg-name = "cros-ec-rpmsg";
};
};
&soc_data {
status = "okay";
};

12
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file

@ -339,6 +339,18 @@ pwrap: pwrap@1000d000 {
clock-names = "spi", "wrap";
};
scp: scp@10500000 {
compatible = "mediatek,mt8183-scp";
reg = <0 0x10500000 0 0x80000>,
<0 0x105c0000 0 0x19080>;
reg-names = "sram", "cfg";
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_SCPSYS>;
clock-names = "main";
memory-region = <&scp_mem_reserved>;
status = "disabled";
};
systimer: timer@10017000 {
compatible = "mediatek,mt8183-timer",
"mediatek,mt6765-timer";