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iommu/arm-smmu: Add support for MSI on SMMUv3
Despite being a platform device, the SMMUv3 is capable of signaling interrupts using MSIs. Hook it into the platform MSI framework and enjoy faults being reported in a new and exciting way. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> [will: tidied up the binding example and reworked most of the code] Signed-off-by: Will Deacon <will.deacon@arm.com>
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c88ae5de71
commit
166bdbd231
3 changed files with 117 additions and 8 deletions
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@ -36,5 +36,24 @@ the PCIe specification.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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- msi-parent : See the generic MSI binding described in
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devicetree/bindings/interrupt-controller/msi.txt
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for a description of the msi-parent property.
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- hisilicon,broken-prefetch-cmd
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: Avoid sending CMD_PREFETCH_* commands to the SMMU.
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** Example
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smmu@2b400000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x2b400000 0x0 0x20000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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dma-coherent;
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#iommu-cells = <0>;
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msi-parent = <&its 0xff0000>;
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};
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@ -362,6 +362,7 @@ config ARM_SMMU_V3
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depends on ARM64 && PCI
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select IOMMU_API
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select IOMMU_IO_PGTABLE_LPAE
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select GENERIC_MSI_IRQ_DOMAIN
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help
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Support for implementations of the ARM System MMU architecture
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version 3 providing translation support to a PCIe root complex.
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@ -26,6 +26,7 @@
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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@ -402,6 +403,31 @@ enum pri_resp {
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PRI_RESP_SUCC,
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};
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enum arm_smmu_msi_index {
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EVTQ_MSI_INDEX,
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GERROR_MSI_INDEX,
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PRIQ_MSI_INDEX,
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ARM_SMMU_MAX_MSIS,
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};
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static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
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[EVTQ_MSI_INDEX] = {
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ARM_SMMU_EVTQ_IRQ_CFG0,
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ARM_SMMU_EVTQ_IRQ_CFG1,
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ARM_SMMU_EVTQ_IRQ_CFG2,
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},
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[GERROR_MSI_INDEX] = {
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ARM_SMMU_GERROR_IRQ_CFG0,
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ARM_SMMU_GERROR_IRQ_CFG1,
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ARM_SMMU_GERROR_IRQ_CFG2,
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},
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[PRIQ_MSI_INDEX] = {
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ARM_SMMU_PRIQ_IRQ_CFG0,
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ARM_SMMU_PRIQ_IRQ_CFG1,
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ARM_SMMU_PRIQ_IRQ_CFG2,
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},
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};
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struct arm_smmu_cmdq_ent {
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/* Common fields */
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u8 opcode;
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@ -2176,6 +2202,72 @@ static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val,
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1, ARM_SMMU_POLL_TIMEOUT_US);
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}
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static void arm_smmu_free_msis(void *data)
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{
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struct device *dev = data;
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platform_msi_domain_free_irqs(dev);
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}
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static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
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{
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phys_addr_t doorbell;
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struct device *dev = msi_desc_to_dev(desc);
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struct arm_smmu_device *smmu = dev_get_drvdata(dev);
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phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];
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doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
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doorbell &= MSI_CFG0_ADDR_MASK << MSI_CFG0_ADDR_SHIFT;
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writeq_relaxed(doorbell, smmu->base + cfg[0]);
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writel_relaxed(msg->data, smmu->base + cfg[1]);
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writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
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}
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static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
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{
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struct msi_desc *desc;
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int ret, nvec = ARM_SMMU_MAX_MSIS;
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struct device *dev = smmu->dev;
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/* Clear the MSI address regs */
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writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
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writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
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if (smmu->features & ARM_SMMU_FEAT_PRI)
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writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);
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else
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nvec--;
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if (!(smmu->features & ARM_SMMU_FEAT_MSI))
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return;
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/* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */
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ret = platform_msi_domain_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg);
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if (ret) {
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dev_warn(dev, "failed to allocate MSIs\n");
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return;
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}
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for_each_msi_entry(desc, dev) {
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switch (desc->platform.msi_index) {
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case EVTQ_MSI_INDEX:
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smmu->evtq.q.irq = desc->irq;
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break;
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case GERROR_MSI_INDEX:
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smmu->gerr_irq = desc->irq;
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break;
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case PRIQ_MSI_INDEX:
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smmu->priq.q.irq = desc->irq;
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break;
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default: /* Unknown */
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continue;
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}
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}
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/* Add callback to free MSIs on teardown */
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devm_add_action(dev, arm_smmu_free_msis, dev);
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}
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static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
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{
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int ret, irq;
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@ -2189,11 +2281,9 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
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return ret;
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}
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/* Clear the MSI address regs */
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writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
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writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
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arm_smmu_setup_msis(smmu);
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/* Request wired interrupt lines */
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/* Request interrupt lines */
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irq = smmu->evtq.q.irq;
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if (irq) {
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ret = devm_request_threaded_irq(smmu->dev, irq,
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@ -2222,8 +2312,6 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
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}
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if (smmu->features & ARM_SMMU_FEAT_PRI) {
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writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);
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irq = smmu->priq.q.irq;
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if (irq) {
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ret = devm_request_threaded_irq(smmu->dev, irq,
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@ -2597,13 +2685,14 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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/* Record our private device structure */
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platform_set_drvdata(pdev, smmu);
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/* Reset the device */
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ret = arm_smmu_device_reset(smmu);
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if (ret)
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goto out_free_structures;
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/* Record our private device structure */
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platform_set_drvdata(pdev, smmu);
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return 0;
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out_free_structures:
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