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phy: qcom-qmp-ufs: Add SM8550 support
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230117224148.1914627-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 changed files with 96 additions and 0 deletions
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@ -103,6 +103,13 @@ static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
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};
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};
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static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
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[QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
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[QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
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};
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static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
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static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
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@ -607,6 +614,61 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
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QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
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QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
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};
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};
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static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
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};
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static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
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QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
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};
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static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
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};
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static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
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QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
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QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
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QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
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QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
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QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
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};
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struct qmp_ufs_offsets {
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struct qmp_ufs_offsets {
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u16 serdes;
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u16 serdes;
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u16 pcs;
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u16 pcs;
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@ -729,6 +791,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets = {
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.rx2 = 0xa00,
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.rx2 = 0xa00,
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};
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};
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static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
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.serdes = 0,
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.pcs = 0x0400,
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.tx = 0x1000,
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.rx = 0x1200,
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.tx2 = 0x1800,
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.rx2 = 0x1a00,
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};
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static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
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static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
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.lanes = 1,
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.lanes = 1,
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@ -968,6 +1039,28 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
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.regs = ufsphy_v5_regs_layout,
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.regs = ufsphy_v5_regs_layout,
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};
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};
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static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
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.lanes = 2,
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.offsets = &qmp_ufs_offsets_v6,
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.tbls = {
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.serdes = sm8550_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
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.tx = sm8550_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
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.rx = sm8550_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
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.pcs = sm8550_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = ufsphy_v6_regs_layout,
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};
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static void qmp_ufs_configure_lane(void __iomem *base,
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static void qmp_ufs_configure_lane(void __iomem *base,
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const struct qmp_phy_init_tbl tbl[],
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const struct qmp_phy_init_tbl tbl[],
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int num,
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int num,
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@ -1479,6 +1572,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
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}, {
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}, {
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.compatible = "qcom,sm8450-qmp-ufs-phy",
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.compatible = "qcom,sm8450-qmp-ufs-phy",
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.data = &sm8450_ufsphy_cfg,
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.data = &sm8450_ufsphy_cfg,
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}, {
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.compatible = "qcom,sm8550-qmp-ufs-phy",
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.data = &sm8550_ufsphy_cfg,
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},
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},
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{ },
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{ },
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};
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};
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