TI K3 device tree updates for v5.19
New Features: J721e: * Enable DSS, DP, HDMI on J721e EVM and SK AM62: * MCAN, MCU GPIO, ECAP APWM, DMA, Etherent and several peripheral on AM62 SK EVM AM64: * Enable Wireless LAN support Fixes: Drop incorrect MCU UART clock rates -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmJ09SgQHHZpZ25lc2hy QHRpLmNvbQAKCRDERh5FfJEW4xthB/0XAFR46Pzyb4EX09hhFyEmjei6y+ZcQ2EC aH0Ynu+WTnHlD1NkX9SoMSfrU+VtBxQCFJFgoljrb6BnubEcwldfg2uzFVCoi5VN 3qS55SCjJJQV0u57UadytF+AU0qdcRsCpIiumtoTiImVeTaIc7UU1s64ErlYthKF RJCvoWYKXvfIuhz3u72jIb7OGmUtSa6jtpTXBoIchZXGaCFeQw9fHKKO/0sjtFAk a4lQa64TvS20SJ4iPFd6gK0befZQHG7+fm5v00RkyGqwqKuI4vwZv0CRKROuyIoD rk44ifIReSufneRwqWhHggQlP7OmI+Ly233hxW4q12UT6CUEWWpC =e3yn -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ5BsIACgkQmmx57+YA GNnr5hAAmxH43IjNRfJT5GbITOf0hIaoG9ygWNRiuIvnQD8HIVD8KCQ402zpb/OK VP9Gq7G1CQ22mT0rNipjvZE15WdN2CVRrmc+PInGlhCgkzjwOtDjCKs5IjSpbS7z QvI/oCxSWPnVbSrGRyND8xGdfDC3Tnd4U4RxOE1nHZ35d7GMTIX/tjDLrL35NDqK lf8bgHEL5c3Mdcep1vURZ7hlLwKP+zxtfKJ8fe0A0GjmFfKJXWcZA8/JvM8Id+8+ m+BwyMAvupacb3l8aDxmsz8bE0ulz/B9yAlzun8IYZwHqRUN82sQkKoj/fX5eSdH wi1jhDpEpse0ElOrIWAX7/FCdVN2CvCaKGG7yYlD+bH7V4qx5O4btTGE7zWIRfuc lNx6t2yE+bF0YZOS1BQ6MSFlAtOFV5Cd9PX5qyJAlo+s0M85r0ckzORD3EzgOMaW dUERlRTSozAuI/7pqYXmEKIcNku7hDDanlt4mOsaWvoZO8HvAqkoepxo8omPkCwm BQa/2dT1kvvNk9plqVLghfxWl/fp2r3Ra764+kSVAObCb1AW9AEJfmua9xLg+kCA S7/Tu6gH5Gf2PiQFFNSzLJAiOWzPSIAynLoreA8uPt2p2NEnbHvMN7rQUaXELttm 5qbxsPpp4yb4VaBwy32hZmSoJGa+8xBlAAILfIzlLhxPtzTyW2s= =sY5d -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt TI K3 device tree updates for v5.19 New Features: J721e: * Enable DSS, DP, HDMI on J721e EVM and SK AM62: * MCAN, MCU GPIO, ECAP APWM, DMA, Etherent and several peripheral on AM62 SK EVM AM64: * Enable Wireless LAN support Fixes: Drop incorrect MCU UART clock rates * tag 'ti-k3-dt-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: dts: ti: k3-j721e-sk: Enable HDMI arm64: dts: ti: k3-j721e-sk: Enable DisplayPort arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm arm64: dts: ti: k3-j721e-*: add DP & DP PHY arm64: dts: ti: k3-am62: Add SA3UL ranges in cbass_main arm64: dts: ti: k3-am62: Add support for MCAN arm64: dts: ti: k3-am62-mcu: Enable MCU GPIO module arm64: dts: ti: k3-am625-sk: Add ECAP APWM nodes arm64: dts: ti: k3-am625-sk: Enable on board peripherals arm64: dts: ti: k3-am62: Add more peripheral nodes arm64: dts: ti: k3-am642-sk: Enable WLAN connected to SDHCI0 arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates Link: https://lore.kernel.org/r/3dc2011b-eb6d-dcd5-3921-57f6a1cf6d8e@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
168b43ac21
|
|
@ -6,6 +6,14 @@
|
|||
*/
|
||||
|
||||
&cbass_main {
|
||||
oc_sram: sram@70000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x70000000 0x00 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x70000000 0x10000>;
|
||||
};
|
||||
|
||||
gic500: interrupt-controller@1800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -40,6 +48,12 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x00100000 0x20000>;
|
||||
|
||||
phy_gmii_sel: phy@4044 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4044 0x8>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
dmss: bus@48000000 {
|
||||
|
|
@ -61,6 +75,69 @@
|
|||
interrupt-names = "rx_012";
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
inta_main_dmss: interrupt-controller@48000000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x00 0x48000000 0x00 0x100000>;
|
||||
#interrupt-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <28>;
|
||||
ti,interrupt-ranges = <4 68 36>;
|
||||
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
|
||||
};
|
||||
|
||||
main_bcdma: dma-controller@485c0100 {
|
||||
compatible = "ti,am64-dmss-bcdma";
|
||||
reg = <0x00 0x485c0100 0x00 0x100>,
|
||||
<0x00 0x4c000000 0x00 0x20000>,
|
||||
<0x00 0x4a820000 0x00 0x20000>,
|
||||
<0x00 0x4aa40000 0x00 0x20000>,
|
||||
<0x00 0x4bc00000 0x00 0x100000>;
|
||||
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <3>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <26>;
|
||||
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
|
||||
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
|
||||
};
|
||||
|
||||
main_pktdma: dma-controller@485c0000 {
|
||||
compatible = "ti,am64-dmss-pktdma";
|
||||
reg = <0x00 0x485c0000 0x00 0x100>,
|
||||
<0x00 0x4a800000 0x00 0x20000>,
|
||||
<0x00 0x4aa00000 0x00 0x40000>,
|
||||
<0x00 0x4b800000 0x00 0x400000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <30>;
|
||||
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
|
||||
<0x24>, /* CPSW_TX_CHAN */
|
||||
<0x25>, /* SAUL_TX_0_CHAN */
|
||||
<0x26>; /* SAUL_TX_1_CHAN */
|
||||
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
|
||||
<0x11>, /* RING_CPSW_TX_CHAN */
|
||||
<0x12>, /* RING_SAUL_TX_0_CHAN */
|
||||
<0x13>; /* RING_SAUL_TX_1_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
|
||||
<0x2b>, /* CPSW_RX_CHAN */
|
||||
<0x2d>, /* SAUL_RX_0_CHAN */
|
||||
<0x2f>, /* SAUL_RX_1_CHAN */
|
||||
<0x31>, /* SAUL_RX_2_CHAN */
|
||||
<0x33>; /* SAUL_RX_3_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
|
||||
<0x2c>, /* FLOW_CPSW_RX_CHAN */
|
||||
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
|
||||
<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
|
||||
};
|
||||
};
|
||||
|
||||
dmsc: system-controller@44043000 {
|
||||
|
|
@ -203,6 +280,36 @@
|
|||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 172 0>;
|
||||
};
|
||||
|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 173 0>;
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 174 0>;
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
|
|
@ -249,6 +356,165 @@
|
|||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
sdhci0: mmc@fa10000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
assigned-clocks = <&k3_clks 57 6>;
|
||||
assigned-clock-parents = <&k3_clks 57 8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
ti,trm-icp = <0x2>;
|
||||
bus-width = <8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x9>;
|
||||
ti,otap-del-sel-hs200 = <0x6>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@fa00000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci2: mmc@fa20000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
};
|
||||
|
||||
fss: bus@fc00000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x00 0x0fc00000 0x00 0x70000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ospi0: spi@fc40000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x00 0x0fc40000 0x00 0x100>,
|
||||
<0x05 0x00000000 0x01 0x00000000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
clocks = <&k3_clks 75 7>;
|
||||
assigned-clocks = <&k3_clks 75 7>;
|
||||
assigned-clock-parents = <&k3_clks 75 8>;
|
||||
assigned-clock-rates = <166666666>;
|
||||
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g: ethernet@8000000 {
|
||||
compatible = "ti,am642-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x00 0x08000000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
assigned-clocks = <&k3_clks 13 3>;
|
||||
assigned-clock-parents = <&k3_clks 13 11>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_pktdma 0xc600 15>,
|
||||
<&main_pktdma 0xc601 15>,
|
||||
<&main_pktdma 0xc602 15>,
|
||||
<&main_pktdma 0xc603 15>,
|
||||
<&main_pktdma 0xc604 15>,
|
||||
<&main_pktdma 0xc605 15>,
|
||||
<&main_pktdma 0xc606 15>,
|
||||
<&main_pktdma 0xc607 15>,
|
||||
<&main_pktdma 0x4600 15>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
||||
"tx7", "rx";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-efuse = <&wkup_conf 0x200>;
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
reg = <2>;
|
||||
ti,mac-only;
|
||||
label = "port2";
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 13 3>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@2a000000 {
|
||||
compatible = "ti,am64-hwspinlock";
|
||||
reg = <0x00 0x2a000000 0x00 0x1000>;
|
||||
|
|
@ -264,4 +530,45 @@
|
|||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
ecap0: pwm@23100000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23100000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 51 0>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
ecap1: pwm@23110000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23110000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 52 0>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
ecap2: pwm@23120000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23120000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 53 0>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_mcan0: can@20701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20701000 0x00 0x200>,
|
||||
<0x00 0x20708000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,4 +33,52 @@
|
|||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b00000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b10000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
|
||||
mcu_gpio_intr: interrupt-controller@4210000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x04210000 0x00 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <5>;
|
||||
ti,interrupt-ranges = <0 104 4>;
|
||||
};
|
||||
|
||||
mcu_gpio0: gpio@4201000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x4201000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&mcu_gpio_intr>;
|
||||
interrupts = <30>, <31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <24>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 79 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@
|
|||
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
|
||||
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
|
||||
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
|
||||
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
|
||||
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am625.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -17,6 +18,12 @@
|
|||
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
mmc2 = &sdhci2;
|
||||
spi0 = &ospi0;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -87,6 +94,33 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-3 {
|
||||
/* TPS22918DBVR */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-4 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_5v0>;
|
||||
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -124,11 +158,114 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_i2c2_pins_default: main-i2c2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
|
||||
AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
|
||||
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
|
||||
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
|
||||
AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
|
||||
AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
|
||||
AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
|
||||
AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
|
||||
AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
|
||||
AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
|
||||
AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
|
||||
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
|
||||
AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
|
||||
AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
|
||||
AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
|
||||
AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
|
||||
AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
usr_led_pins_default: usr-led-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mdio1_pins_default: main-mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
|
||||
AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii1_pins_default: main-rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
|
||||
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
|
||||
AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
|
||||
AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
|
||||
AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
|
||||
AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
|
||||
AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
|
||||
AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
|
||||
AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
|
||||
AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
|
||||
AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
|
||||
AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii2_pins_default: main-rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
|
||||
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
|
||||
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
|
||||
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
|
||||
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
|
||||
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
|
||||
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
|
||||
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
|
||||
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
|
||||
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
|
||||
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
|
||||
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
|
||||
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
|
||||
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
|
||||
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
|
||||
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
|
||||
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
|
||||
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
|
||||
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
|
||||
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
|
||||
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
|
||||
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
|
|
@ -188,6 +325,33 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "EXP_PS_3V3_En",
|
||||
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
|
||||
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
|
||||
"UART1_FET_BUF_EN", "WL_LT_EN",
|
||||
"GPIO_HDMI_RSTn", "CSI_GPIO1",
|
||||
"CSI_GPIO2", "PRU_3V3_EN",
|
||||
"HDMI_INTn", "TEST_GPIO2",
|
||||
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
|
||||
"MCASP1_FET_SEL", "UART1_FET_SEL",
|
||||
"TSINT#", "IO_EXP_TEST_LED";
|
||||
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
|
|
@ -198,9 +362,134 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mdio1_pins_default
|
||||
&main_rgmii1_pins_default
|
||||
&main_rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6c0000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecap1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecap2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@
|
|||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
|
|
@ -21,7 +20,6 @@
|
|||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 160 0>;
|
||||
|
|
|
|||
|
|
@ -125,6 +125,31 @@
|
|||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
com8_ls_en: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "com8_ls_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
pinctrl-0 = <&main_com8_ls_en_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan_en: regulator-2 {
|
||||
/* output of SN74AVC4T245RSVR */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wlan_en";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
enable-active-high;
|
||||
pinctrl-0 = <&main_wlan_en_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vin-supply = <&com8_ls_en>;
|
||||
gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -216,6 +241,23 @@
|
|||
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
main_wlan_en_pins_default: main-wlan-en-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_wlan_pins_default: main-wlan-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
|
|
@ -293,6 +335,26 @@
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
vmmc-supply = <&wlan_en>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1837";
|
||||
reg = <2>;
|
||||
pinctrl-0 = <&main_wlan_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
|
|
|
|||
|
|
@ -148,6 +148,28 @@
|
|||
pinctrl-0 = <&main_mcan2_gpio_pins_default>;
|
||||
standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
dp_pwr_3v3: regulator-dp-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dp-pwr";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
dp0: connector {
|
||||
compatible = "dp-connector";
|
||||
label = "DP0";
|
||||
type = "full-size";
|
||||
dp-pwr-supply = <&dp_pwr_3v3>;
|
||||
|
||||
port {
|
||||
dp_connector_in: endpoint {
|
||||
remote-endpoint = <&dp0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -190,6 +212,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
dp0_pins_default: dp0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
|
||||
|
|
@ -658,6 +686,33 @@
|
|||
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
port {
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&dp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dp0_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dp0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
dp0_out: endpoint {
|
||||
remote-endpoint = <&dp_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -793,6 +848,24 @@
|
|||
};
|
||||
};
|
||||
|
||||
&serdes4 {
|
||||
torrent_phy_dp: phy@0 {
|
||||
reg = <0>;
|
||||
resets = <&serdes_wiz4 1>;
|
||||
cdns,phy-type = <PHY_TYPE_DP>;
|
||||
cdns,num-lanes = <4>;
|
||||
cdns,max-bit-rate = <5400>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mhdp {
|
||||
phys = <&torrent_phy_dp>;
|
||||
phy-names = "dpphy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp0_pins_default>;
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
|
|
@ -843,10 +916,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/phy/phy-ti.h>
|
||||
#include <dt-bindings/mux/mux.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
|
||||
|
|
@ -789,6 +790,47 @@
|
|||
#size-cells = <2>;
|
||||
};
|
||||
|
||||
serdes_wiz4: wiz@5050000 {
|
||||
compatible = "ti,am64-wiz-10g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 297 9>;
|
||||
assigned-clock-parents = <&k3_clks 297 10>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
num-lanes = <4>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
ranges = <0x05050000 0x00 0x05050000 0x010000>,
|
||||
<0x0a030a00 0x00 0x0a030a00 0x40>;
|
||||
|
||||
serdes4: serdes@5050000 {
|
||||
/*
|
||||
* Note: we also map DPTX PHY registers as the Torrent
|
||||
* needs to manage those.
|
||||
*/
|
||||
compatible = "ti,j721e-serdes-10g";
|
||||
reg = <0x05050000 0x010000>,
|
||||
<0x0a030a00 0x40>; /* DPTX PHY */
|
||||
reg-names = "torrent_phy", "dptx_phy";
|
||||
|
||||
resets = <&serdes_wiz4 0>;
|
||||
reset-names = "torrent_reset";
|
||||
clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
|
||||
clock-names = "refclk";
|
||||
assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
|
||||
<&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
|
||||
assigned-clock-parents = <&k3_clks 297 9>,
|
||||
<&k3_clks 297 9>,
|
||||
<&k3_clks 297 9>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
|
|
@ -1267,6 +1309,37 @@
|
|||
};
|
||||
};
|
||||
|
||||
mhdp: dp-bridge@a000000 {
|
||||
compatible = "ti,j721e-mhdp8546";
|
||||
/*
|
||||
* Note: we do not map DPTX PHY area, as that is handled by
|
||||
* the PHY driver.
|
||||
*/
|
||||
reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
|
||||
<0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
|
||||
reg-names = "mhdptx", "j721e-intg";
|
||||
|
||||
clocks = <&k3_clks 151 36>;
|
||||
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dp0_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,j721e-dss";
|
||||
reg =
|
||||
|
|
@ -1317,8 +1390,6 @@
|
|||
"common_s2";
|
||||
|
||||
dss_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -213,6 +213,71 @@
|
|||
enable-active-high;
|
||||
};
|
||||
|
||||
dp0: connector {
|
||||
compatible = "dp-connector";
|
||||
label = "DP0";
|
||||
type = "full-size";
|
||||
dp-pwr-supply = <&dp_pwr_3v3>;
|
||||
|
||||
port {
|
||||
dp_connector_in: endpoint {
|
||||
remote-endpoint = <&dp0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
type = "a";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_hpd_pins_default>;
|
||||
|
||||
ddc-i2c-bus = <&main_i2c1>;
|
||||
|
||||
/* HDMI_HPD */
|
||||
hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&tfp410_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dvi-bridge {
|
||||
compatible = "ti,tfp410";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pdn_pins_default>;
|
||||
|
||||
powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
|
||||
ti,deskew = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tfp410_in: endpoint {
|
||||
remote-endpoint = <&dpi1_out>;
|
||||
pclk-sample = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tfp410_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -317,6 +382,18 @@
|
|||
>;
|
||||
};
|
||||
|
||||
hdmi_hpd_pins_default: hdmi-hpd-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
|
||||
>;
|
||||
};
|
||||
|
||||
hdmi_pdn_pins_default: hdmi-pdn-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
|
||||
>;
|
||||
};
|
||||
|
||||
/* Reset for M.2 E Key slot on PCIe0 */
|
||||
ekey_reset_pins_default: ekey-reset-pns-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -624,6 +701,24 @@
|
|||
};
|
||||
};
|
||||
|
||||
&serdes4 {
|
||||
torrent_phy_dp: phy@0 {
|
||||
reg = <0>;
|
||||
resets = <&serdes_wiz4 1>;
|
||||
cdns,phy-type = <PHY_TYPE_DP>;
|
||||
cdns,num-lanes = <4>;
|
||||
cdns,max-bit-rate = <5400>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mhdp {
|
||||
phys = <&torrent_phy_dp>;
|
||||
phy-names = "dpphy";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp0_pins_default>;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
|
|
@ -702,6 +797,46 @@
|
|||
<&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpi1_out: endpoint {
|
||||
remote-endpoint = <&tfp410_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dp0_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dp0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
dp0_out: endpoint {
|
||||
remote-endpoint = <&dp_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
/* Unused */
|
||||
status = "disabled";
|
||||
|
|
@ -836,10 +971,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue