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iommu/amd: Fix IOMMU perf counter clobbering during init
commit8c17bbf6c8
upstream. init_iommu_perf_ctr() clobbers the register when it checks write access to IOMMU perf counters and fails to restore when they are writable. Add save and restore to fix it. Signed-off-by: Shuah Khan <skhan@linuxfoundation.org> Fixes:30861ddc9c
("perf/x86/amd: Add IOMMU Performance Counter resource management") Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 18 additions and 6 deletions
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@ -1655,27 +1655,39 @@ static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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static void init_iommu_perf_ctr(struct amd_iommu *iommu)
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{
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struct pci_dev *pdev = iommu->dev;
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u64 val = 0xabcd, val2 = 0;
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u64 val = 0xabcd, val2 = 0, save_reg = 0;
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if (!iommu_feature(iommu, FEATURE_PC))
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return;
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amd_iommu_pc_present = true;
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/* save the value to restore, if writable */
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if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false))
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goto pc_false;
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/* Check if the performance counters can be written to */
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if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
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(iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
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(val != val2)) {
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pci_err(pdev, "Unable to write to IOMMU perf counter.\n");
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amd_iommu_pc_present = false;
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return;
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}
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(val != val2))
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goto pc_false;
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/* restore */
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if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true))
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goto pc_false;
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pci_info(pdev, "IOMMU performance counters supported\n");
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val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
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iommu->max_banks = (u8) ((val >> 12) & 0x3f);
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iommu->max_counters = (u8) ((val >> 7) & 0xf);
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return;
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pc_false:
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pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n");
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amd_iommu_pc_present = false;
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return;
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}
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static ssize_t amd_iommu_show_cap(struct device *dev,
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